diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2017-02-19 05:30:32 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2017-02-19 05:30:32 -0500 |
| commit | f2e2410a505ef48516f121ce1b2232ba7aa389af (patch) | |
| tree | dbe4c8482b37e854302410318fc474f507310724 /tests/long | |
| parent | 184c6d7ebd7faa0869f294526a54a239a216b7c8 (diff) | |
| download | gem5-f2e2410a505ef48516f121ce1b2232ba7aa389af.tar.xz | |
stats: Get all stats updated to reflect current behaviour
Line everything up again.
Diffstat (limited to 'tests/long')
32 files changed, 38248 insertions, 38213 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 4852a1186..75078a9be 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,110 +1,110 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.893228 # Number of seconds simulated -sim_ticks 1893227633000 # Number of ticks simulated -final_tick 1893227633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1893227678500 # Number of ticks simulated +final_tick 1893227678500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25790 # Simulator instruction rate (inst/s) -host_op_rate 25790 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 869674472 # Simulator tick rate (ticks/s) -host_mem_usage 393476 # Number of bytes of host memory used -host_seconds 2176.94 # Real time elapsed on the host -sim_insts 56143729 # Number of instructions simulated -sim_ops 56143729 # Number of ops (including micro ops) simulated +host_inst_rate 31053 # Simulator instruction rate (inst/s) +host_op_rate 31053 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1047239405 # Simulator tick rate (ticks/s) +host_mem_usage 384600 # Number of bytes of host memory used +host_seconds 1807.83 # Real time elapsed on the host +sim_insts 56138739 # Number of instructions simulated +sim_ops 56138739 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1047552 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1046400 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24860352 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25908864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1047552 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1047552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7567040 # Number of bytes written to this memory -system.physmem.bytes_written::total 7567040 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16368 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25907712 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1046400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1046400 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7566528 # Number of bytes written to this memory +system.physmem.bytes_written::total 7566528 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 16350 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 388443 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404826 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118235 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118235 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 553315 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13131201 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 404808 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118227 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118227 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 552707 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13131200 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 507 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13685023 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 553315 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 553315 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3996899 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3996899 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3996899 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 553315 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13131201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13684414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 552707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 552707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3996629 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3996629 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3996629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 552707 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13131200 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 507 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17681922 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404826 # Number of read requests accepted -system.physmem.writeReqs 118235 # Number of write requests accepted -system.physmem.readBursts 404826 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118235 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25901888 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue -system.physmem.bytesWritten 7565888 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25908864 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7567040 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17681043 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404808 # Number of read requests accepted +system.physmem.writeReqs 118227 # Number of write requests accepted +system.physmem.readBursts 404808 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 118227 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25900800 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6912 # Total number of bytes read from write queue +system.physmem.bytesWritten 7564480 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25907712 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7566528 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 108 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25487 # Per bank write bursts system.physmem.perBankRdBursts::1 25708 # Per bank write bursts -system.physmem.perBankRdBursts::2 25813 # Per bank write bursts -system.physmem.perBankRdBursts::3 25780 # Per bank write bursts -system.physmem.perBankRdBursts::4 25224 # Per bank write bursts +system.physmem.perBankRdBursts::2 25811 # Per bank write bursts +system.physmem.perBankRdBursts::3 25775 # Per bank write bursts +system.physmem.perBankRdBursts::4 25223 # Per bank write bursts system.physmem.perBankRdBursts::5 24955 # Per bank write bursts system.physmem.perBankRdBursts::6 24789 # Per bank write bursts -system.physmem.perBankRdBursts::7 24580 # Per bank write bursts -system.physmem.perBankRdBursts::8 25111 # Per bank write bursts +system.physmem.perBankRdBursts::7 24582 # Per bank write bursts +system.physmem.perBankRdBursts::8 25110 # Per bank write bursts system.physmem.perBankRdBursts::9 25258 # Per bank write bursts -system.physmem.perBankRdBursts::10 25520 # Per bank write bursts +system.physmem.perBankRdBursts::10 25516 # Per bank write bursts system.physmem.perBankRdBursts::11 24876 # Per bank write bursts -system.physmem.perBankRdBursts::12 24529 # Per bank write bursts -system.physmem.perBankRdBursts::13 25563 # Per bank write bursts -system.physmem.perBankRdBursts::14 25801 # Per bank write bursts +system.physmem.perBankRdBursts::12 24528 # Per bank write bursts +system.physmem.perBankRdBursts::13 25560 # Per bank write bursts +system.physmem.perBankRdBursts::14 25799 # Per bank write bursts system.physmem.perBankRdBursts::15 25723 # Per bank write bursts -system.physmem.perBankWrBursts::0 7828 # Per bank write bursts -system.physmem.perBankWrBursts::1 7672 # Per bank write bursts -system.physmem.perBankWrBursts::2 8070 # Per bank write bursts -system.physmem.perBankWrBursts::3 7747 # Per bank write bursts -system.physmem.perBankWrBursts::4 7316 # Per bank write bursts -system.physmem.perBankWrBursts::5 6943 # Per bank write bursts -system.physmem.perBankWrBursts::6 6787 # Per bank write bursts -system.physmem.perBankWrBursts::7 6421 # Per bank write bursts -system.physmem.perBankWrBursts::8 7240 # Per bank write bursts -system.physmem.perBankWrBursts::9 6874 # Per bank write bursts -system.physmem.perBankWrBursts::10 7389 # Per bank write bursts -system.physmem.perBankWrBursts::11 6891 # Per bank write bursts -system.physmem.perBankWrBursts::12 7084 # Per bank write bursts -system.physmem.perBankWrBursts::13 8012 # Per bank write bursts -system.physmem.perBankWrBursts::14 7998 # Per bank write bursts -system.physmem.perBankWrBursts::15 7945 # Per bank write bursts +system.physmem.perBankWrBursts::0 7831 # Per bank write bursts +system.physmem.perBankWrBursts::1 7673 # Per bank write bursts +system.physmem.perBankWrBursts::2 8069 # Per bank write bursts +system.physmem.perBankWrBursts::3 7745 # Per bank write bursts +system.physmem.perBankWrBursts::4 7318 # Per bank write bursts +system.physmem.perBankWrBursts::5 6942 # Per bank write bursts +system.physmem.perBankWrBursts::6 6789 # Per bank write bursts +system.physmem.perBankWrBursts::7 6426 # Per bank write bursts +system.physmem.perBankWrBursts::8 7239 # Per bank write bursts +system.physmem.perBankWrBursts::9 6872 # Per bank write bursts +system.physmem.perBankWrBursts::10 7384 # Per bank write bursts +system.physmem.perBankWrBursts::11 6889 # Per bank write bursts +system.physmem.perBankWrBursts::12 7081 # Per bank write bursts +system.physmem.perBankWrBursts::13 8010 # Per bank write bursts +system.physmem.perBankWrBursts::14 7995 # Per bank write bursts +system.physmem.perBankWrBursts::15 7932 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 56 # Number of times write queue was full causing retry -system.physmem.totGap 1893218679000 # Total gap between requests +system.physmem.numWrRetry 72 # Number of times write queue was full causing retry +system.physmem.totGap 1893218795000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404826 # Read request sizes (log2) +system.physmem.readPktSize::6 404808 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118235 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402419 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118227 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -149,205 +149,206 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 136 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63385 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 528.007825 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 321.906071 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 413.488828 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14518 22.90% 22.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11005 17.36% 40.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4663 7.36% 47.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3176 5.01% 52.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2328 3.67% 56.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2299 3.63% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1937 3.06% 62.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1572 2.48% 65.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21887 34.53% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63385 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5244 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 77.176964 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2915.674794 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5241 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6619 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 189 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63391 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 527.918474 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 322.301426 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.348187 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14401 22.72% 22.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11109 17.52% 40.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4782 7.54% 47.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3159 4.98% 52.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2221 3.50% 56.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2316 3.65% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1932 3.05% 62.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1599 2.52% 65.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21872 34.50% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63391 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5234 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 77.317348 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2918.457754 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5231 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5244 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5244 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.543288 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.756988 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.319215 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4714 89.89% 89.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 44 0.84% 90.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 176 3.36% 94.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 4 0.08% 94.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 4 0.08% 94.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 12 0.23% 94.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 7 0.13% 94.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 2 0.04% 94.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 32 0.61% 95.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.10% 95.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 158 3.01% 98.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 14 0.27% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 6 0.11% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 4 0.08% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 6 0.11% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 3 0.06% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 2 0.04% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 2 0.04% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 11 0.21% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.08% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 14 0.27% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 9 0.17% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 4 0.08% 99.89% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5234 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5234 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.582155 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.722612 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.927693 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4724 90.26% 90.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 39 0.75% 91.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 163 3.11% 94.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 4 0.08% 94.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 3 0.06% 94.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 11 0.21% 94.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 8 0.15% 94.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 2 0.04% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 33 0.63% 95.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 4 0.08% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 144 2.75% 98.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 23 0.44% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 9 0.17% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 3 0.06% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 7 0.13% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 3 0.06% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 10 0.19% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 5 0.10% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 14 0.27% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 10 0.19% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 3 0.06% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 5 0.10% 99.89% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::224-231 2 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 3 0.06% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5244 # Writes before turning the bus around for reads -system.physmem.totQLat 5894702000 # Total ticks spent queuing -system.physmem.totMemAccLat 13483145750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2023585000 # Total ticks spent in databus transfers -system.physmem.avgQLat 14565.00 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-359 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5234 # Writes before turning the bus around for reads +system.physmem.totQLat 5912751750 # Total ticks spent queuing +system.physmem.totMemAccLat 13500876750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2023500000 # Total ticks spent in databus transfers +system.physmem.avgQLat 14610.21 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33315.00 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 33360.21 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.68 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.69 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.68 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 4.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.89 # Average write queue length when enqueuing -system.physmem.readRowHits 363769 # Number of row buffer hits during reads -system.physmem.writeRowHits 95780 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.88 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.01 # Row buffer hit rate for writes -system.physmem.avgGap 3619498.83 # Average gap between requests -system.physmem.pageHitRate 87.88 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 221604180 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 117785415 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1444679040 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 306852480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4717362000.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4796151000 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 296411520 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 10938570180 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 5566653120 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 443189598645 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 471596477220 # Total energy per rank (pJ) -system.physmem_0.averagePower 249.096553 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1881819292000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 462054000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2003948000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1843451492500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 14496450250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8825649500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 23988038750 # Time in different power states -system.physmem_1.actEnergy 230964720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122760660 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1445000340 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 310240260 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4792348080.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4813778250 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 297177120 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 11174584380 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 5627937120 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 443035577925 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 471852130095 # Total energy per rank (pJ) -system.physmem_1.averagePower 249.231588 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1881891335250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 468372250 # Time in different power states -system.physmem_1.memoryStateTime::REF 2035962000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1842731534750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 14656099500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 8829934000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 24505730500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 15259378 # Number of BP lookups -system.cpu.branchPred.condPredicted 13119579 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 525820 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12061992 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4569562 # Number of BTB hits +system.physmem.avgWrQLen 24.80 # Average write queue length when enqueuing +system.physmem.readRowHits 363798 # Number of row buffer hits during reads +system.physmem.writeRowHits 95706 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.89 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.95 # Row buffer hit rate for writes +system.physmem.avgGap 3619678.98 # Average gap between requests +system.physmem.pageHitRate 87.87 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 222139680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 118070040 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1444636200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 306899460 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4706913120.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4768209600 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 303610560 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 10937646210 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 5541404160 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 443214367815 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 471564552855 # Total energy per rank (pJ) +system.physmem_0.averagePower 249.079684 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1881862215000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 479498250 # Time in different power states +system.physmem_0.memoryStateTime::REF 1999510000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1843562153500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 14430696500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8769616250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 23986204000 # Time in different power states +system.physmem_1.actEnergy 230472060 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 122498805 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1444921800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 310078440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 4819392240.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4890695190 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 314585760 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 11137759530 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 5641159680 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 443008801920 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 471922426215 # Total energy per rank (pJ) +system.physmem_1.averagePower 249.268712 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1881676600250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 514596250 # Time in different power states +system.physmem_1.memoryStateTime::REF 2047516000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1842563195250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 14690458500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8987140500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 24424772000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 15251875 # Number of BP lookups +system.cpu.branchPred.condPredicted 13114549 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 526465 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12070936 # Number of BTB lookups +system.cpu.branchPred.BTBHits 4577345 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 37.883975 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 862888 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 32219 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6522078 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 538261 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5983817 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 225046 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 37.920382 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 863154 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33512 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 6526029 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 541717 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5984312 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 221941 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9322510 # DTB read hits -system.cpu.dtb.read_misses 17386 # DTB read misses +system.cpu.dtb.read_hits 9319487 # DTB read hits +system.cpu.dtb.read_misses 17755 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 764595 # DTB read accesses -system.cpu.dtb.write_hits 6393584 # DTB write hits -system.cpu.dtb.write_misses 2379 # DTB write misses +system.cpu.dtb.read_accesses 764786 # DTB read accesses +system.cpu.dtb.write_hits 6392965 # DTB write hits +system.cpu.dtb.write_misses 2560 # DTB write misses system.cpu.dtb.write_acv 158 # DTB write access violations -system.cpu.dtb.write_accesses 298734 # DTB write accesses -system.cpu.dtb.data_hits 15716094 # DTB hits -system.cpu.dtb.data_misses 19765 # DTB misses +system.cpu.dtb.write_accesses 298884 # DTB write accesses +system.cpu.dtb.data_hits 15712452 # DTB hits +system.cpu.dtb.data_misses 20315 # DTB misses system.cpu.dtb.data_acv 369 # DTB access violations -system.cpu.dtb.data_accesses 1063329 # DTB accesses -system.cpu.itb.fetch_hits 4018414 # ITB hits -system.cpu.itb.fetch_misses 6313 # ITB misses -system.cpu.itb.fetch_acv 710 # ITB acv -system.cpu.itb.fetch_accesses 4024727 # ITB accesses +system.cpu.dtb.data_accesses 1063670 # DTB accesses +system.cpu.itb.fetch_hits 4023125 # ITB hits +system.cpu.itb.fetch_misses 6293 # ITB misses +system.cpu.itb.fetch_acv 687 # ITB acv +system.cpu.itb.fetch_accesses 4029418 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -360,88 +361,88 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numPwrStateTransitions 12750 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 6375 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 281835914.509804 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 440008281.220830 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 6375 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 224500 # Distribution of time spent in the clock gated state +system.cpu.numPwrStateTransitions 12752 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 6376 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 281784609.786700 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 439970621.768515 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 6376 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 121000 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 6375 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 96523678000 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1796703955000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 193068084 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::total 6376 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 96569006500 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1796658672000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 193159059 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56143729 # Number of instructions committed -system.cpu.committedOps 56143729 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2983109 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 6375 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3593387182 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.438818 # CPI: cycles per instruction -system.cpu.ipc 0.290798 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 3199033 5.70% 5.70% # Class of committed instruction -system.cpu.op_class_0::IntAlu 36198718 64.48% 70.17% # Class of committed instruction -system.cpu.op_class_0::IntMult 60825 0.11% 70.28% # Class of committed instruction +system.cpu.committedInsts 56138739 # Number of instructions committed +system.cpu.committedOps 56138739 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2973387 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 6376 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3593296298 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.440745 # CPI: cycles per instruction +system.cpu.ipc 0.290635 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 3199075 5.70% 5.70% # Class of committed instruction +system.cpu.op_class_0::IntAlu 36194440 64.47% 70.17% # Class of committed instruction +system.cpu.op_class_0::IntMult 60814 0.11% 70.28% # Class of committed instruction system.cpu.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.op_class_0::FloatAdd 38079 0.07% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::MemRead 9175039 16.34% 86.70% # Class of committed instruction -system.cpu.op_class_0::MemWrite 6234994 11.11% 97.80% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::MemRead 9174678 16.34% 86.70% # Class of committed instruction +system.cpu.op_class_0::MemWrite 6234348 11.11% 97.80% # Class of committed instruction system.cpu.op_class_0::FloatMemRead 144497 0.26% 98.06% # Class of committed instruction system.cpu.op_class_0::FloatMemWrite 137980 0.25% 98.31% # Class of committed instruction -system.cpu.op_class_0::IprAccess 950928 1.69% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 951192 1.69% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 56143729 # Class of committed instruction +system.cpu.op_class_0::total 56138739 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211453 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74770 40.93% 40.93% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211522 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74796 40.93% 40.93% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% 41.00% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1905 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105857 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182663 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73403 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105900 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182732 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73429 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1905 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73403 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148842 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1837707081000 97.07% 97.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 86418000 0.00% 97.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 712034000 0.04% 97.11% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 54721100500 2.89% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1893226633500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981717 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73429 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148894 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1837688968000 97.07% 97.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 86405500 0.00% 97.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 711997500 0.04% 97.11% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 54739315500 2.89% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1893226686500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693417 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814845 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693381 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814822 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed @@ -449,7 +450,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4173 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175496 91.22% 93.42% # number of callpals executed +system.cpu.kern.callpal::swpipl 175565 91.22% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6808 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -458,31 +459,31 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5130 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192387 # number of callpals executed +system.cpu.kern.callpal::total 192456 # number of callpals executed system.cpu.kern.mode_switch::kernel 5875 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.mode_switch::user 1736 # number of protection mode switches system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1907 -system.cpu.kern.mode_good::user 1739 +system.cpu.kern.mode_good::kernel 1904 +system.cpu.kern.mode_good::user 1736 system.cpu.kern.mode_good::idle 168 -system.cpu.kern.mode_switch_good::kernel 0.324596 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.324085 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.080229 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392872 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 37288586500 1.97% 1.97% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4317914500 0.23% 2.20% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1851620122500 97.80% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.392375 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 37303090500 1.97% 1.97% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4315388500 0.23% 2.20% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1851608197500 97.80% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4174 # number of times the context was actually changed -system.cpu.tickCycles 85319079 # Number of cycles that the object actually ticked -system.cpu.idleCycles 107749005 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1394486 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.980102 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13946466 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1394998 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.997481 # Average number of references to valid blocks. +system.cpu.tickCycles 85358190 # Number of cycles that the object actually ticked +system.cpu.idleCycles 107800869 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1394352 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.980074 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 13943564 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1394864 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.996361 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 99338500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.980102 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.980074 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999961 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999961 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -490,369 +491,369 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 225 system.cpu.dcache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63927467 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63927467 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 7985618 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7985618 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5578297 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5578297 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183538 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183538 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 198978 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 198978 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13563915 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13563915 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13563915 # number of overall hits -system.cpu.dcache.overall_hits::total 13563915 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1096590 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1096590 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 573634 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 573634 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 16462 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 16462 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1670224 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1670224 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1670224 # number of overall misses -system.cpu.dcache.overall_misses::total 1670224 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33587119500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33587119500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25315634500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25315634500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222567500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 222567500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 58902754000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 58902754000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 58902754000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 58902754000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9082208 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9082208 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6151931 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6151931 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200000 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200000 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 198978 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 198978 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15234139 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15234139 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15234139 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15234139 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120740 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120740 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093245 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093245 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082310 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082310 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.109637 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.109637 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.109637 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.109637 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30628.693951 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30628.693951 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44132.032794 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44132.032794 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13520.076540 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13520.076540 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35266.379839 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35266.379839 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35266.379839 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35266.379839 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63916074 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63916074 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 7983580 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7983580 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5577346 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5577346 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183586 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183586 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199016 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199016 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13560926 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13560926 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13560926 # number of overall hits +system.cpu.dcache.overall_hits::total 13560926 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1096421 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1096421 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 573901 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 573901 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 16452 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 16452 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1670322 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1670322 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1670322 # number of overall misses +system.cpu.dcache.overall_misses::total 1670322 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33580747500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33580747500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25364054000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25364054000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 223095000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 223095000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 58944801500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 58944801500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 58944801500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 58944801500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9080001 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9080001 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6151247 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6151247 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200038 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200038 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199016 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199016 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15231248 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15231248 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15231248 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15231248 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120751 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120751 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093298 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093298 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082244 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082244 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.109664 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.109664 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.109664 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.109664 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30627.603357 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30627.603357 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44195.870019 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44195.870019 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13560.357403 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13560.357403 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35289.484004 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35289.484004 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35289.484004 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35289.484004 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 837775 # number of writebacks -system.cpu.dcache.writebacks::total 837775 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21966 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 21966 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269674 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 269674 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 837673 # number of writebacks +system.cpu.dcache.writebacks::total 837673 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21981 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 21981 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269878 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 269878 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 291640 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 291640 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 291640 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 291640 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074624 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074624 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 303960 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 303960 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16459 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 16459 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1378584 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378584 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1378584 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378584 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 291859 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 291859 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 291859 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 291859 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074440 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1074440 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304023 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304023 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16449 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 16449 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1378463 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1378463 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1378463 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1378463 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32024640000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32024640000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12912591500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12912591500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205405000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205405000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44937231500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 44937231500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44937231500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 44937231500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534181500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534181500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534181500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534181500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118322 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118322 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049409 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049409 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082295 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082295 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090493 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090493 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090493 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090493 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29800.786135 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29800.786135 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42481.219568 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42481.219568 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12479.798287 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12479.798287 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32596.658238 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 32596.658238 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32596.658238 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32596.658238 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221382.611833 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221382.611833 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92682.987978 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92682.987978 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1476860 # number of replacements -system.cpu.icache.tags.tagsinuse 509.256241 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 19221452 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1477371 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 13.010579 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 36168783500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.256241 # Average occupied blocks per requestor +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32016506000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32016506000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12938125500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12938125500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205942500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205942500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44954631500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 44954631500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44954631500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 44954631500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534159000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534159000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534159000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534159000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118330 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118330 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049425 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049425 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082229 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082229 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090502 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090502 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090502 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090502 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29798.319124 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29798.319124 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42556.403627 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42556.403627 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12520.062010 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12520.062010 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32612.142292 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 32612.142292 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32612.142292 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32612.142292 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221379.365079 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221379.365079 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92681.628708 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92681.628708 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1477259 # number of replacements +system.cpu.icache.tags.tagsinuse 509.256262 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 19240724 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1477770 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 13.020107 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 36168160500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.256262 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.994641 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.994641 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 400 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 398 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 22176547 # Number of tag accesses -system.cpu.icache.tags.data_accesses 22176547 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 19221455 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 19221455 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 19221455 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 19221455 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 19221455 # number of overall hits -system.cpu.icache.overall_hits::total 19221455 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1477546 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1477546 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1477546 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1477546 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1477546 # number of overall misses -system.cpu.icache.overall_misses::total 1477546 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20691200000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20691200000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20691200000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20691200000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20691200000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20691200000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 20699001 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 20699001 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 20699001 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 20699001 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 20699001 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 20699001 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071382 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.071382 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.071382 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.071382 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.071382 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.071382 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14003.760289 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14003.760289 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14003.760289 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14003.760289 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14003.760289 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14003.760289 # average overall miss latency +system.cpu.icache.tags.tag_accesses 22196619 # Number of tag accesses +system.cpu.icache.tags.data_accesses 22196619 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 19240727 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 19240727 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 19240727 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 19240727 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 19240727 # number of overall hits +system.cpu.icache.overall_hits::total 19240727 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1477946 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1477946 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1477946 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1477946 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1477946 # number of overall misses +system.cpu.icache.overall_misses::total 1477946 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20694155000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20694155000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20694155000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20694155000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20694155000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20694155000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 20718673 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 20718673 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 20718673 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 20718673 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 20718673 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 20718673 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071334 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.071334 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.071334 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.071334 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.071334 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.071334 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14001.969625 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14001.969625 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14001.969625 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14001.969625 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14001.969625 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14001.969625 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1476860 # number of writebacks -system.cpu.icache.writebacks::total 1476860 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1477546 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1477546 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1477546 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1477546 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1477546 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1477546 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19213654000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19213654000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19213654000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19213654000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19213654000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19213654000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071382 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071382 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071382 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.071382 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071382 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.071382 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13003.760289 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13003.760289 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13003.760289 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13003.760289 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13003.760289 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13003.760289 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 339644 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65408.616626 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5336317 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 405166 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 13.170693 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6813000000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 268.269404 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5779.515007 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 59360.832216 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.004093 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088188 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.905774 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998056 # Average percentage of cache occupancy +system.cpu.icache.writebacks::writebacks 1477259 # number of writebacks +system.cpu.icache.writebacks::total 1477259 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1477946 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1477946 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1477946 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1477946 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1477946 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1477946 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19216209000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19216209000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19216209000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19216209000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19216209000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19216209000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071334 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071334 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071334 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.071334 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071334 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.071334 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13001.969625 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13001.969625 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13001.969625 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13001.969625 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13001.969625 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13001.969625 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 339629 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65408.640121 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5336861 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 405151 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 13.172523 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 6812650000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 268.308507 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5784.509565 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 59355.822049 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.004094 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088265 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.905698 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998057 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 585 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5148 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59335 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59336 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 46341070 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 46341070 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 837775 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 837775 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1476292 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1476292 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 15 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 15 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187328 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187328 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1461124 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1461124 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 818824 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 818824 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1461124 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1006152 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2467276 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1461124 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1006152 # number of overall hits -system.cpu.l2cache.overall_hits::total 2467276 # number of overall hits +system.cpu.l2cache.tags.tag_accesses 46345268 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 46345268 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 837673 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 837673 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1476684 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1476684 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 16 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187384 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187384 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1461541 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1461541 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 818635 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 818635 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1461541 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1006019 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2467560 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1461541 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1006019 # number of overall hits +system.cpu.l2cache.overall_hits::total 2467560 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 116642 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116642 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16369 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 16369 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272228 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 272228 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 16369 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 388870 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 405239 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 16369 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 388870 # number of overall misses -system.cpu.l2cache.overall_misses::total 405239 # number of overall misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 116650 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 116650 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16351 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 16351 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272221 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 272221 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 16351 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 388871 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 405222 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 16351 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 388871 # number of overall misses +system.cpu.l2cache.overall_misses::total 405222 # number of overall misses system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 331500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 331500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10483953000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10483953000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1616348000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1616348000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21973293500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 21973293500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1616348000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 32457246500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34073594500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1616348000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 32457246500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34073594500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 837775 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 837775 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1476292 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1476292 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 21 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 303970 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 303970 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1477493 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1477493 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1091052 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1091052 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1477493 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1395022 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2872515 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1477493 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1395022 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2872515 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.285714 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.285714 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383729 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383729 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011079 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011079 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249510 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249510 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011079 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.278755 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.141075 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011079 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.278755 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.141075 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10508664000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10508664000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1613902000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1613902000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21967740000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 21967740000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1613902000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 32476404000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34090306000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1613902000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 32476404000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34090306000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 837673 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 837673 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1476684 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1476684 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 22 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 22 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304034 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304034 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1477892 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1477892 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1090856 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1090856 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1477892 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1394890 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2872782 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1477892 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1394890 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2872782 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.272727 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.272727 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383674 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383674 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011064 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011064 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249548 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249548 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011064 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.278783 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.141056 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011064 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.278783 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.141056 # miss rate for overall accesses system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 55250 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 55250 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89881.457794 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89881.457794 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 98744.455984 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 98744.455984 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80716.507854 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80716.507854 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 98744.455984 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83465.545041 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84082.712918 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 98744.455984 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83465.545041 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84082.712918 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90087.132447 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90087.132447 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 98703.565531 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 98703.565531 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80698.182727 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80698.182727 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 98703.565531 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83514.594814 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 84127.480739 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 98703.565531 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83514.594814 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 84127.480739 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 76723 # number of writebacks -system.cpu.l2cache.writebacks::total 76723 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 76715 # number of writebacks +system.cpu.l2cache.writebacks::total 76715 # number of writebacks system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116642 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116642 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16369 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16369 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272228 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272228 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16369 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388870 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 405239 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16369 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388870 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 405239 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116650 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116650 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16351 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16351 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272221 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272221 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16351 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388871 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 405222 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16351 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388871 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 405222 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable @@ -861,103 +862,103 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16553 system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 271500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 271500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9317533000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9317533000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1452658000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1452658000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19254021000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19254021000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1452658000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28571554000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30024212000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1452658000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28571554000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30024212000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447536000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447536000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447536000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447536000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383729 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383729 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011079 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011079 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249510 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249510 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011079 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278755 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141075 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011079 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278755 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.141075 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9342164000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9342164000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1450392000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1450392000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19248668000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19248668000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1450392000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28590832000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30041224000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1450392000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28590832000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30041224000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447515000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447515000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447515000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447515000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.272727 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.272727 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383674 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383674 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011064 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011064 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249548 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249548 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011064 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278783 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141056 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011064 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278783 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141056 # mshr miss rate for overall accesses system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 45250 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 45250 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79881.457794 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79881.457794 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 88744.455984 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 88744.455984 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70727.555578 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70727.555578 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 88744.455984 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73473.278988 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74090.134464 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 88744.455984 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73473.278988 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74090.134464 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208879.653680 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208879.653680 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87448.559174 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87448.559174 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5743935 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2871442 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2378 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 998 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 998 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80087.132447 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80087.132447 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 88703.565531 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 88703.565531 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70709.710125 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70709.710125 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 88703.565531 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73522.664328 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74135.224642 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 88703.565531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73522.664328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74135.224642 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208876.623377 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208876.623377 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87447.290521 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87447.290521 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5744469 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2871707 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2386 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 999 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 999 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2575661 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2575864 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9623 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9623 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 914498 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1476860 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 819632 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 303970 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 303970 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1477546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 23 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 240 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4431899 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217835 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8649734 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189078592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142951868 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 332030460 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 340255 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4923648 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3229187 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001046 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.032331 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 914388 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1477259 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 819593 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 22 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 22 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1477946 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091017 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 237 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 2 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4433097 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217440 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8650537 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189129664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142936828 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 332066492 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 340239 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4923200 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 3229438 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001049 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.032373 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3225808 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3379 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3226050 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3388 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3229187 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5199690500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3229438 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5200254500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 292383 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 292883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2216461215 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2217065706 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2104266491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2104067991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -971,7 +972,7 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51175 # Transaction distribution @@ -1002,46 +1003,46 @@ system.iobus.pkt_size_system.bridge.master::total 44348 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2705956 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5413000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 5413500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 807000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 792000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 181000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 180500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15127500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15611000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2305500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5984000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5971500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216248283 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216263272 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23483000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.299538 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.299521 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1735874305000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.299538 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.081221 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.081221 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1735874841000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.299521 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.081220 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.081220 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1052,12 +1053,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 29884383 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 29884383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4931902900 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4931902900 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4961787283 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4961787283 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4961787283 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4961787283 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4948356889 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4948356889 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4978241272 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4978241272 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4978241272 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4978241272 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1076,17 +1077,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 172742.098266 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 172742.098266 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118692.310839 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118692.310839 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 118916.411815 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118916.411815 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 118916.411815 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118916.411815 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 893 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119088.296327 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 119088.296327 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 119310.755470 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119310.755470 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 119310.755470 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119310.755470 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 1846 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 8 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 14 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 111.625000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 131.857143 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks @@ -1100,12 +1101,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 21234383 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 21234383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2851851307 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2851851307 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2873085690 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2873085690 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2873085690 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2873085690 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2868303297 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2868303297 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2889537680 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2889537680 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2889537680 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2889537680 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1116,74 +1117,74 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 122742.098266 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 122742.098266 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68633.310238 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68633.310238 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68857.655842 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68857.655842 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68857.655842 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68857.655842 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 827515 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 381393 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69029.247617 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69029.247617 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69251.951588 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 69251.951588 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69251.951588 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 69251.951588 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 827499 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 381391 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 524 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 295677 # Transaction distribution +system.membus.trans_dist::ReadResp 295651 # Transaction distribution system.membus.trans_dist::WriteReq 9623 # Transaction distribution system.membus.trans_dist::WriteResp 9623 # Transaction distribution -system.membus.trans_dist::WritebackDirty 118235 # Transaction distribution -system.membus.trans_dist::CleanEvict 262254 # Transaction distribution +system.membus.trans_dist::WritebackDirty 118227 # Transaction distribution +system.membus.trans_dist::CleanEvict 262247 # Transaction distribution system.membus.trans_dist::UpgradeReq 138 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 116510 # Transaction distribution -system.membus.trans_dist::ReadExResp 116510 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288770 # Transaction distribution -system.membus.trans_dist::BadAddressError 23 # Transaction distribution +system.membus.trans_dist::ReadExReq 116518 # Transaction distribution +system.membus.trans_dist::ReadExResp 116518 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 288745 # Transaction distribution +system.membus.trans_dist::BadAddressError 24 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 127 # Transaction distribution +system.membus.trans_dist::InvalidateResp 124 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148837 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 46 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181989 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148786 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 48 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181940 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1265414 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1265365 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44348 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30818176 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30862524 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30816512 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30860860 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33520252 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 561 # Total snoops (count) +system.membus.pkt_size::total 33518588 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 558 # Total snoops (count) system.membus.snoopTraffic 27584 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 463523 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001461 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.038189 # Request fanout histogram +system.membus.snoop_fanout::samples 463506 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001454 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.038105 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 462846 99.85% 99.85% # Request fanout histogram -system.membus.snoop_fanout::1 677 0.15% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 462832 99.85% 99.85% # Request fanout histogram +system.membus.snoop_fanout::1 674 0.15% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 463523 # Request fanout histogram -system.membus.reqLayer0.occupancy 29930000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 463506 # Request fanout histogram +system.membus.reqLayer0.occupancy 30386000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1319547835 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1319436087 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 29000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 30000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2160176250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2160035750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1081022 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1079521 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1215,28 +1216,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 53cfb4ebd..1e6aa4a0d 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,125 +1,125 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.909484 # Number of seconds simulated -sim_ticks 1909483951500 # Number of ticks simulated -final_tick 1909483951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.910457 # Number of seconds simulated +sim_ticks 1910457097500 # Number of ticks simulated +final_tick 1910457097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 164890 # Simulator instruction rate (inst/s) -host_op_rate 164890 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5556117262 # Simulator tick rate (ticks/s) -host_mem_usage 341236 # Number of bytes of host memory used -host_seconds 343.67 # Real time elapsed on the host -sim_insts 56668174 # Number of instructions simulated -sim_ops 56668174 # Number of ops (including micro ops) simulated +host_inst_rate 237868 # Simulator instruction rate (inst/s) +host_op_rate 237868 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8017235800 # Simulator tick rate (ticks/s) +host_mem_usage 340828 # Number of bytes of host memory used +host_seconds 238.29 # Real time elapsed on the host +sim_insts 56682446 # Number of instructions simulated +sim_ops 56682446 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 857600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24440064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 121024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 888256 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.inst 856512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24438912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 120704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 888384 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26307904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 857600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 121024 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 978624 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7910400 # Number of bytes written to this memory -system.physmem.bytes_written::total 7910400 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13400 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 381876 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1891 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 13879 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26305472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 856512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 120704 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 977216 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7909632 # Number of bytes written to this memory +system.physmem.bytes_written::total 7909632 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13383 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 381858 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1886 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 13881 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 411061 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123600 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123600 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 449127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12799303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 63380 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 465181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13777494 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 449127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 63380 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 512507 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4142690 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4142690 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4142690 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 449127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12799303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 63380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 465181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17920184 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 411061 # Number of read requests accepted -system.physmem.writeReqs 123600 # Number of write requests accepted -system.physmem.readBursts 411061 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123600 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26300672 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue -system.physmem.bytesWritten 7909120 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26307904 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7910400 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 411023 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123588 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123588 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 448328 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12792180 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 63181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 465011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 502 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13769203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 448328 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 63181 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 511509 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4140178 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4140178 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4140178 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 448328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12792180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 63181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 465011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 502 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17909381 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 411023 # Number of read requests accepted +system.physmem.writeReqs 123588 # Number of write requests accepted +system.physmem.readBursts 411023 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123588 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26298624 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6848 # Total number of bytes read from write queue +system.physmem.bytesWritten 7907712 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26305472 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7909632 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 107 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26241 # Per bank write bursts -system.physmem.perBankRdBursts::1 25988 # Per bank write bursts -system.physmem.perBankRdBursts::2 25972 # Per bank write bursts -system.physmem.perBankRdBursts::3 25684 # Per bank write bursts -system.physmem.perBankRdBursts::4 25579 # Per bank write bursts -system.physmem.perBankRdBursts::5 25567 # Per bank write bursts -system.physmem.perBankRdBursts::6 25634 # Per bank write bursts -system.physmem.perBankRdBursts::7 25346 # Per bank write bursts -system.physmem.perBankRdBursts::8 25590 # Per bank write bursts -system.physmem.perBankRdBursts::9 25694 # Per bank write bursts -system.physmem.perBankRdBursts::10 25928 # Per bank write bursts -system.physmem.perBankRdBursts::11 25514 # Per bank write bursts +system.physmem.perBankRdBursts::0 26243 # Per bank write bursts +system.physmem.perBankRdBursts::1 25982 # Per bank write bursts +system.physmem.perBankRdBursts::2 25968 # Per bank write bursts +system.physmem.perBankRdBursts::3 25688 # Per bank write bursts +system.physmem.perBankRdBursts::4 25576 # Per bank write bursts +system.physmem.perBankRdBursts::5 25569 # Per bank write bursts +system.physmem.perBankRdBursts::6 25629 # Per bank write bursts +system.physmem.perBankRdBursts::7 25342 # Per bank write bursts +system.physmem.perBankRdBursts::8 25591 # Per bank write bursts +system.physmem.perBankRdBursts::9 25697 # Per bank write bursts +system.physmem.perBankRdBursts::10 25920 # Per bank write bursts +system.physmem.perBankRdBursts::11 25515 # Per bank write bursts system.physmem.perBankRdBursts::12 26076 # Per bank write bursts -system.physmem.perBankRdBursts::13 25422 # Per bank write bursts -system.physmem.perBankRdBursts::14 25093 # Per bank write bursts -system.physmem.perBankRdBursts::15 25620 # Per bank write bursts -system.physmem.perBankWrBursts::0 8582 # Per bank write bursts -system.physmem.perBankWrBursts::1 8090 # Per bank write bursts -system.physmem.perBankWrBursts::2 7941 # Per bank write bursts -system.physmem.perBankWrBursts::3 7423 # Per bank write bursts -system.physmem.perBankWrBursts::4 7276 # Per bank write bursts -system.physmem.perBankWrBursts::5 7412 # Per bank write bursts -system.physmem.perBankWrBursts::6 7548 # Per bank write bursts -system.physmem.perBankWrBursts::7 7160 # Per bank write bursts -system.physmem.perBankWrBursts::8 7532 # Per bank write bursts -system.physmem.perBankWrBursts::9 7637 # Per bank write bursts -system.physmem.perBankWrBursts::10 7817 # Per bank write bursts -system.physmem.perBankWrBursts::11 7733 # Per bank write bursts -system.physmem.perBankWrBursts::12 8265 # Per bank write bursts -system.physmem.perBankWrBursts::13 7849 # Per bank write bursts -system.physmem.perBankWrBursts::14 7512 # Per bank write bursts -system.physmem.perBankWrBursts::15 7803 # Per bank write bursts +system.physmem.perBankRdBursts::13 25417 # Per bank write bursts +system.physmem.perBankRdBursts::14 25094 # Per bank write bursts +system.physmem.perBankRdBursts::15 25609 # Per bank write bursts +system.physmem.perBankWrBursts::0 8586 # Per bank write bursts +system.physmem.perBankWrBursts::1 8089 # Per bank write bursts +system.physmem.perBankWrBursts::2 7939 # Per bank write bursts +system.physmem.perBankWrBursts::3 7426 # Per bank write bursts +system.physmem.perBankWrBursts::4 7272 # Per bank write bursts +system.physmem.perBankWrBursts::5 7413 # Per bank write bursts +system.physmem.perBankWrBursts::6 7547 # Per bank write bursts +system.physmem.perBankWrBursts::7 7156 # Per bank write bursts +system.physmem.perBankWrBursts::8 7533 # Per bank write bursts +system.physmem.perBankWrBursts::9 7641 # Per bank write bursts +system.physmem.perBankWrBursts::10 7810 # Per bank write bursts +system.physmem.perBankWrBursts::11 7729 # Per bank write bursts +system.physmem.perBankWrBursts::12 8256 # Per bank write bursts +system.physmem.perBankWrBursts::13 7847 # Per bank write bursts +system.physmem.perBankWrBursts::14 7516 # Per bank write bursts +system.physmem.perBankWrBursts::15 7798 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 80 # Number of times write queue was full causing retry -system.physmem.totGap 1909479571500 # Total gap between requests +system.physmem.numWrRetry 69 # Number of times write queue was full causing retry +system.physmem.totGap 1910452747500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 411061 # Read request sizes (log2) +system.physmem.readPktSize::6 411023 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 123600 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 316679 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 38784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 25115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 123588 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 316637 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 38767 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 25132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see @@ -159,205 +159,206 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7441 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7944 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 213 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64366 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 531.481590 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 324.184214 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 415.960810 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14447 22.45% 22.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11484 17.84% 40.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5025 7.81% 48.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2916 4.53% 52.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2241 3.48% 56.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1886 2.93% 59.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1937 3.01% 62.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1616 2.51% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22814 35.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64366 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5520 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 74.445833 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2823.039428 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5517 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7914 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 160 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64267 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 532.249522 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 325.147595 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.887517 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14293 22.24% 22.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11517 17.92% 40.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5102 7.94% 48.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2862 4.45% 52.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2222 3.46% 56.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1875 2.92% 58.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1935 3.01% 61.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1643 2.56% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22818 35.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64267 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5506 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 74.626952 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2826.578445 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5503 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5520 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5520 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.387681 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.753213 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.953412 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4982 90.25% 90.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 46 0.83% 91.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 181 3.28% 94.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 8 0.14% 94.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 3 0.05% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 15 0.27% 94.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 3 0.05% 94.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 1 0.02% 94.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 37 0.67% 95.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 6 0.11% 95.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 147 2.66% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 11 0.20% 98.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 11 0.20% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 1 0.02% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 13 0.24% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 5 0.09% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 2 0.04% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 2 0.04% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 4 0.07% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 6 0.11% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 8 0.14% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 11 0.20% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 1 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 8 0.14% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 6 0.11% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5520 # Writes before turning the bus around for reads -system.physmem.totQLat 8180795500 # Total ticks spent queuing -system.physmem.totMemAccLat 15886070500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2054740000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19907.13 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5506 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5506 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.440610 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.769678 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.128904 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4988 90.59% 90.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 40 0.73% 91.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 160 2.91% 94.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 10 0.18% 94.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 4 0.07% 94.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 18 0.33% 94.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 5 0.09% 94.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 6 0.11% 95.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 35 0.64% 95.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 4 0.07% 95.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 137 2.49% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 15 0.27% 98.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 13 0.24% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 3 0.05% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 8 0.15% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 3 0.05% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 5 0.09% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 3 0.05% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 1 0.02% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 5 0.09% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 9 0.16% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 10 0.18% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 9 0.16% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 8 0.15% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 3 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5506 # Writes before turning the bus around for reads +system.physmem.totQLat 8133947000 # Total ticks spent queuing +system.physmem.totMemAccLat 15838622000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2054580000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19794.67 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38657.13 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 38544.67 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.14 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 4.14 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.22 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.94 # Average write queue length when enqueuing -system.physmem.readRowHits 370615 # Number of row buffer hits during reads -system.physmem.writeRowHits 99546 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.54 # Row buffer hit rate for writes -system.physmem.avgGap 3571383.68 # Average gap between requests -system.physmem.pageHitRate 87.95 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229044060 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 121739805 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1470918540 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 320675040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3850719600.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4272567240 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 246889440 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 8425769640 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 4664365920 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 449143940805 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 472747584480 # Total energy per rank (pJ) -system.physmem_0.averagePower 247.578716 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1899455525250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 389729500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1635812000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1868844860000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 12146835250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7989359750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 18477355000 # Time in different power states -system.physmem_1.actEnergy 230536320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122529165 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1463250180 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 324412560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3755450400.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4276202130 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 236380800 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 8298087360 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 4412246880 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 449354887095 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 472475862540 # Total energy per rank (pJ) -system.physmem_1.averagePower 247.436414 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1899482388000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 371395250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1595272000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1869798792500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 11490281750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 8030486500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 18197723500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu0.branchPred.lookups 16749334 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14325553 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 462257 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 10374415 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4757954 # Number of BTB hits +system.physmem.avgRdQLen 2.17 # Average read queue length when enqueuing +system.physmem.avgWrQLen 27.12 # Average write queue length when enqueuing +system.physmem.readRowHits 370641 # Number of row buffer hits during reads +system.physmem.writeRowHits 99565 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.20 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.56 # Row buffer hit rate for writes +system.physmem.avgGap 3573538.04 # Average gap between requests +system.physmem.pageHitRate 87.97 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 228629940 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 121519695 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1470818580 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 320654160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3862397760.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4332596790 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 252811200 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 8421848610 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 4670504160 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 449339904270 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 473022982485 # Total energy per rank (pJ) +system.physmem_0.averagePower 247.596757 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1900281265750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 402747000 # Time in different power states +system.physmem_0.memoryStateTime::REF 1640746000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1869662817000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 12162830000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8118960750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 18468996750 # Time in different power states +system.physmem_1.actEnergy 230243580 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 122373570 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1463121660 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 324318600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3740699040.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4231975260 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 230624160 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 8237523150 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 4445714880 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 449624008125 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 472652324325 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.402742 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1900567958250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 356565750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1589032000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1870929942000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 11577456000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7939162500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 18064939250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu0.branchPred.lookups 16804357 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14368910 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 476654 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 10787243 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4777357 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 45.862384 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 926589 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 34524 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4807269 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 496703 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 4310566 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 206845 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 44.287099 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 929095 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 33008 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 5112942 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 499455 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 4613487 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 206250 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9423503 # DTB read hits -system.cpu0.dtb.read_misses 34044 # DTB read misses -system.cpu0.dtb.read_acv 602 # DTB read access violations -system.cpu0.dtb.read_accesses 567323 # DTB read accesses -system.cpu0.dtb.write_hits 5707426 # DTB write hits -system.cpu0.dtb.write_misses 8375 # DTB write misses -system.cpu0.dtb.write_acv 432 # DTB write access violations -system.cpu0.dtb.write_accesses 185068 # DTB write accesses -system.cpu0.dtb.data_hits 15130929 # DTB hits -system.cpu0.dtb.data_misses 42419 # DTB misses -system.cpu0.dtb.data_acv 1034 # DTB access violations -system.cpu0.dtb.data_accesses 752391 # DTB accesses -system.cpu0.itb.fetch_hits 1309826 # ITB hits -system.cpu0.itb.fetch_misses 6979 # ITB misses -system.cpu0.itb.fetch_acv 608 # ITB acv -system.cpu0.itb.fetch_accesses 1316805 # ITB accesses +system.cpu0.dtb.read_hits 9429395 # DTB read hits +system.cpu0.dtb.read_misses 34826 # DTB read misses +system.cpu0.dtb.read_acv 601 # DTB read access violations +system.cpu0.dtb.read_accesses 567385 # DTB read accesses +system.cpu0.dtb.write_hits 5710239 # DTB write hits +system.cpu0.dtb.write_misses 8500 # DTB write misses +system.cpu0.dtb.write_acv 413 # DTB write access violations +system.cpu0.dtb.write_accesses 185113 # DTB write accesses +system.cpu0.dtb.data_hits 15139634 # DTB hits +system.cpu0.dtb.data_misses 43326 # DTB misses +system.cpu0.dtb.data_acv 1014 # DTB access violations +system.cpu0.dtb.data_accesses 752498 # DTB accesses +system.cpu0.itb.fetch_hits 1313411 # ITB hits +system.cpu0.itb.fetch_misses 6916 # ITB misses +system.cpu0.itb.fetch_acv 613 # ITB acv +system.cpu0.itb.fetch_accesses 1320327 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -370,152 +371,152 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numPwrStateTransitions 12955 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 6478 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 285544950.833745 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 440803858.104390 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 6477 99.98% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.numPwrStateTransitions 12957 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 6479 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 285646442.815249 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 440880288.422179 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 6479 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 39000 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 6478 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 59723759999 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849760191501 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 119453997 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::total 6479 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 59753794500 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 1850703303000 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 119514068 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 25744550 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 73396662 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 16749334 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6181246 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 86853986 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1333740 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 1 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 29854 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 138979 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 426939 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8448706 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 314842 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 113861488 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.644614 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.955082 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 25767559 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 73719684 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 16804357 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6205907 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 86932839 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1362768 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 60 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 30191 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 137457 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 417781 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 385 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8508507 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 323806 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 113967656 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.646847 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.957898 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 100232411 88.03% 88.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 886423 0.78% 88.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1866278 1.64% 90.45% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 772305 0.68% 91.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2608424 2.29% 93.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 580288 0.51% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 680998 0.60% 94.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 835244 0.73% 95.26% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5399117 4.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 100279992 87.99% 87.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 883136 0.77% 88.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1879288 1.65% 90.41% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 773699 0.68% 91.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2621733 2.30% 93.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 582123 0.51% 93.90% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 690580 0.61% 94.51% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 840992 0.74% 95.25% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5416113 4.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 113861488 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.140216 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.614435 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 20674409 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 82009104 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8737077 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1802336 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 638561 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 612096 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 28873 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 63730808 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 85670 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 638561 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 21537349 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 55655987 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 17571911 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9607617 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 8850061 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 61287779 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 195487 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2001492 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 247198 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 4966656 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 41332689 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 73998496 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 73867344 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 122420 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 33806898 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 7525791 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1421231 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 231053 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12310515 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9804371 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6066029 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1436076 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 935297 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 54210960 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1853678 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 52617678 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 75373 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9354795 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 4029114 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1289525 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 113861488 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.462120 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.203620 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 113967656 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.140606 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.616829 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 20688539 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 82043348 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8777506 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1804992 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 653270 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 4633985 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 29119 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 64001211 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 84558 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 653270 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 21557209 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 55702323 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17600356 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9645124 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 8809372 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 61498566 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 199219 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2004403 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 243805 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 4929982 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 41484246 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 74256527 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 74125426 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 122370 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 33821902 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 7662344 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1423361 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 232902 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12334048 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9834851 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6076556 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1449838 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 941199 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 54338035 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1857223 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 52670686 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 76725 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9465955 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 4150833 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1293033 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 113967656 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.462155 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.203590 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 92467205 81.21% 81.21% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9144132 8.03% 89.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3819872 3.35% 92.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2741139 2.41% 95.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2853722 2.51% 97.51% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1412384 1.24% 98.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 945124 0.83% 99.58% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 360447 0.32% 99.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 117463 0.10% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 92547755 81.21% 81.21% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9157312 8.04% 89.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3826452 3.36% 92.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2741793 2.41% 95.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2858470 2.51% 97.51% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1410754 1.24% 98.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 945179 0.83% 99.58% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 363161 0.32% 99.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 116780 0.10% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 113861488 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 113967656 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 167498 16.72% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMisc 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 489097 48.82% 65.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 297116 29.66% 95.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMemRead 26550 2.65% 97.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMemWrite 21561 2.15% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 167135 16.69% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMisc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 489044 48.84% 65.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 297041 29.67% 95.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemRead 26511 2.65% 97.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemWrite 21568 2.15% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2541 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 36104376 68.62% 68.62% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 55717 0.11% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2539 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 36140522 68.62% 68.62% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 55958 0.11% 68.73% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 25404 0.05% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 25396 0.05% 68.78% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.78% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.78% # Type of FU issued system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.78% # Type of FU issued @@ -543,444 +544,444 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.78% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9732272 18.50% 87.27% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5684196 10.80% 98.08% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMemRead 122332 0.23% 98.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMemWrite 110816 0.21% 98.52% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 778757 1.48% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9743290 18.50% 87.28% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5689891 10.80% 98.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemRead 122252 0.23% 98.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemWrite 110721 0.21% 98.52% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 778850 1.48% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 52617678 # Type of FU issued -system.cpu0.iq.rate 0.440485 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1001822 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019040 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 219604859 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 65162997 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50893555 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 569180 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 274272 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 257685 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 53309029 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 307930 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 608555 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 52670686 # Type of FU issued +system.cpu0.iq.rate 0.440707 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1001299 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019011 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 219818324 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 65405263 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 50914307 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 568728 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 273845 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 257541 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 53361731 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 307715 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 607759 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1940010 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3457 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 18333 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 663404 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1969497 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4520 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 18416 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 673256 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18340 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 362661 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18394 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 367969 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 638561 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 52164612 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1031418 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 59600447 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 153776 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9804371 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6066029 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1643055 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39666 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 791016 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 18333 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 179892 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 504278 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 684170 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 51936356 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9483037 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 681322 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 653270 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 52238307 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1038475 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 59749161 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 168806 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9834851 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6076556 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1644704 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40383 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 797635 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 18416 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 191736 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 507842 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 699578 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 51971663 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9489993 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 699023 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3535809 # number of nop insts executed -system.cpu0.iew.exec_refs 15215766 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8258108 # Number of branches executed -system.cpu0.iew.exec_stores 5732729 # Number of stores executed -system.cpu0.iew.exec_rate 0.434781 # Inst execution rate -system.cpu0.iew.wb_sent 51332154 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 51151240 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26231692 # num instructions producing a value -system.cpu0.iew.wb_consumers 36261297 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.428209 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.723407 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 9848757 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 564153 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 610679 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 112148809 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.442210 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.364760 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 3553903 # number of nop insts executed +system.cpu0.iew.exec_refs 15226009 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8258878 # Number of branches executed +system.cpu0.iew.exec_stores 5736016 # Number of stores executed +system.cpu0.iew.exec_rate 0.434858 # Inst execution rate +system.cpu0.iew.wb_sent 51356635 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 51171848 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26241416 # num instructions producing a value +system.cpu0.iew.wb_consumers 36276103 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.428166 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.723380 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 9976632 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 564190 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 625296 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 112216183 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.442120 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.363987 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 94602668 84.35% 84.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6980008 6.22% 90.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3776982 3.37% 93.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2002013 1.79% 95.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1561505 1.39% 97.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 569175 0.51% 97.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 418696 0.37% 98.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 452906 0.40% 98.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1784856 1.59% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 94653327 84.35% 84.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6985358 6.22% 90.57% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3782709 3.37% 93.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2004229 1.79% 95.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1568389 1.40% 97.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 570810 0.51% 97.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 418508 0.37% 98.01% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 451920 0.40% 98.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1780933 1.59% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 112148809 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 49593272 # Number of instructions committed -system.cpu0.commit.committedOps 49593272 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 112216183 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 49613021 # Number of instructions committed +system.cpu0.commit.committedOps 49613021 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13266986 # Number of memory references committed -system.cpu0.commit.loads 7864361 # Number of loads committed -system.cpu0.commit.membars 192313 # Number of memory barriers committed -system.cpu0.commit.branches 7507748 # Number of branches committed -system.cpu0.commit.fp_insts 248828 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 45902219 # Number of committed integer instructions. -system.cpu0.commit.function_calls 632222 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2885965 5.82% 5.82% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 32382704 65.30% 71.12% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 54404 0.11% 71.23% # Class of committed instruction +system.cpu0.commit.refs 13268654 # Number of memory references committed +system.cpu0.commit.loads 7865354 # Number of loads committed +system.cpu0.commit.membars 192328 # Number of memory barriers committed +system.cpu0.commit.branches 7511599 # Number of branches committed +system.cpu0.commit.fp_insts 248727 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 45921534 # Number of committed integer instructions. +system.cpu0.commit.function_calls 632359 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2886254 5.82% 5.82% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 32400169 65.31% 71.12% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 54625 0.11% 71.23% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.23% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 24932 0.05% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 24929 0.05% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1267 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 7943457 16.02% 87.30% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5299157 10.69% 97.98% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMemRead 113217 0.23% 98.21% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMemWrite 109412 0.22% 98.43% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 778757 1.57% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1267 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 7944499 16.01% 87.30% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5299897 10.68% 97.98% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMemRead 113183 0.23% 98.21% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMemWrite 109348 0.22% 98.43% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 778850 1.57% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 49593272 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1784856 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 169631516 # The number of ROB reads -system.cpu0.rob.rob_writes 120597460 # The number of ROB writes -system.cpu0.timesIdled 479927 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 5592509 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3698912124 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 46709842 # Number of Instructions Simulated -system.cpu0.committedOps 46709842 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.557362 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.557362 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.391028 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.391028 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 67996788 # number of integer regfile reads -system.cpu0.int_regfile_writes 37259313 # number of integer regfile writes -system.cpu0.fp_regfile_reads 121463 # number of floating regfile reads -system.cpu0.fp_regfile_writes 130119 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1657761 # number of misc regfile reads -system.cpu0.misc_regfile_writes 782234 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 1252644 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.062362 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10655904 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1253074 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.503811 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 28164500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.062362 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988403 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988403 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 49613021 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1780933 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 169850432 # The number of ROB reads +system.cpu0.rob.rob_writes 120933247 # The number of ROB writes +system.cpu0.timesIdled 478916 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 5546412 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3700805346 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 46729302 # Number of Instructions Simulated +system.cpu0.committedOps 46729302 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.557583 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.557583 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.390994 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.390994 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 68048969 # number of integer regfile reads +system.cpu0.int_regfile_writes 37279666 # number of integer regfile writes +system.cpu0.fp_regfile_reads 121382 # number of floating regfile reads +system.cpu0.fp_regfile_writes 130068 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1658488 # number of misc regfile reads +system.cpu0.misc_regfile_writes 782262 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 1253915 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.032819 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10656048 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1254345 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.495309 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 28054500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.032819 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988345 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988345 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 409 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 407 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.839844 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 56905298 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 56905298 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 6776069 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6776069 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3521167 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3521167 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174528 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 174528 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 179927 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 179927 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10297236 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10297236 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10297236 # number of overall hits -system.cpu0.dcache.overall_hits::total 10297236 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1551541 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1551541 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1684277 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1684277 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20385 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20385 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3031 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 3031 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3235818 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3235818 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3235818 # number of overall misses -system.cpu0.dcache.overall_misses::total 3235818 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41541989000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 41541989000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 84989668522 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 84989668522 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 383673500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 383673500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 17049500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 17049500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 126531657522 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 126531657522 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 126531657522 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 126531657522 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8327610 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8327610 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5205444 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5205444 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194913 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 194913 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182958 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 182958 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13533054 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13533054 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13533054 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13533054 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.186313 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.186313 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323561 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.323561 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.104585 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.104585 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016567 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.016567 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.239105 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.239105 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.239105 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.239105 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26774.664028 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 26774.664028 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50460.624067 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 50460.624067 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18821.363748 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18821.363748 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5625.041241 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5625.041241 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39103.453137 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 39103.453137 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39103.453137 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 39103.453137 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 4484959 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 5749 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 107356 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 120 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 41.776510 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 47.908333 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 737573 # number of writebacks -system.cpu0.dcache.writebacks::total 737573 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 550277 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 550277 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1432731 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1432731 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5546 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5546 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1983008 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1983008 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1983008 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1983008 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1001264 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1001264 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251546 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 251546 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14839 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14839 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3031 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 3031 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1252810 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1252810 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1252810 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1252810 # number of overall MSHR misses +system.cpu0.dcache.tags.tag_accesses 56914873 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 56914873 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 6773563 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6773563 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3523907 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3523907 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174492 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 174492 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 179921 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 179921 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10297470 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10297470 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10297470 # number of overall hits +system.cpu0.dcache.overall_hits::total 10297470 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1555944 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1555944 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1682220 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1682220 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 19936 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19936 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3029 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 3029 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3238164 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3238164 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3238164 # number of overall misses +system.cpu0.dcache.overall_misses::total 3238164 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41483749500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 41483749500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 85008982052 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 85008982052 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 398193000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 398193000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 17043500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 17043500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 126492731552 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 126492731552 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 126492731552 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 126492731552 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8329507 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8329507 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5206127 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5206127 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194428 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 194428 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182950 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 182950 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13535634 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13535634 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13535634 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13535634 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.186799 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.186799 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323123 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.323123 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.102537 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.102537 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016556 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.016556 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.239233 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.239233 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.239233 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.239233 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26661.466929 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 26661.466929 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50533.807737 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50533.807737 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 19973.565409 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 19973.565409 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5626.774513 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5626.774513 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39063.102286 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 39063.102286 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39063.102286 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 39063.102286 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 4473141 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2637 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 108649 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 100 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 41.170568 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 26.370000 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 737996 # number of writebacks +system.cpu0.dcache.writebacks::total 737996 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 553324 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 553324 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1430604 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1430604 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5325 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5325 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1983928 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1983928 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1983928 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1983928 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1002620 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1002620 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251616 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 251616 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14611 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14611 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3029 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 3029 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1254236 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1254236 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1254236 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1254236 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 6977 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 6977 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9910 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 9910 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16887 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 16887 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 31631751000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 31631751000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 13189939409 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13189939409 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 172118000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 172118000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14018500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14018500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 44821690409 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 44821690409 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 44821690409 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 44821690409 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1557150500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1557150500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1557150500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1557150500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.120234 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.120234 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048324 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048324 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.076131 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.076131 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016567 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016567 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092574 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092574 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092574 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092574 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31591.818941 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31591.818941 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 52435.496525 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 52435.496525 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11599.029584 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11599.029584 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4625.041241 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4625.041241 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35776.925798 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35776.925798 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35776.925798 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35776.925798 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223183.388276 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223183.388276 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92210.013620 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92210.013620 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 892272 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.350681 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7503325 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 892783 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.404422 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 30334536500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.350681 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994826 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994826 # Average percentage of cache occupancy +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9909 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 9909 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16886 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 16886 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 31595131000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 31595131000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 13207477923 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13207477923 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 169739500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 169739500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14014500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14014500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 44802608923 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 44802608923 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 44802608923 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 44802608923 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1557264500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1557264500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1557264500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1557264500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.120370 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.120370 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048331 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048331 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075149 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075149 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016556 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016556 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092662 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092662 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092662 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092662 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31512.568072 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31512.568072 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 52490.612374 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 52490.612374 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11617.240435 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11617.240435 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4626.774513 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4626.774513 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35721.035693 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35721.035693 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35721.035693 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35721.035693 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223199.727677 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223199.727677 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92222.225512 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92222.225512 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 891919 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.368701 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7561136 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 892430 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.472526 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 30335024500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.368701 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994861 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.994861 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 501 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 9341754 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 9341754 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 7503325 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7503325 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7503325 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7503325 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7503325 # number of overall hits -system.cpu0.icache.overall_hits::total 7503325 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 945376 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 945376 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 945376 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 945376 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 945376 # number of overall misses -system.cpu0.icache.overall_misses::total 945376 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13858102494 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13858102494 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13858102494 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13858102494 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13858102494 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13858102494 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8448701 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8448701 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8448701 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8448701 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8448701 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8448701 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111896 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.111896 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111896 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.111896 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111896 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.111896 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14658.826217 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14658.826217 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14658.826217 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14658.826217 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14658.826217 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14658.826217 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6578 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 9401165 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 9401165 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 7561136 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7561136 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7561136 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7561136 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7561136 # number of overall hits +system.cpu0.icache.overall_hits::total 7561136 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 947367 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 947367 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 947367 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 947367 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 947367 # number of overall misses +system.cpu0.icache.overall_misses::total 947367 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13858743493 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13858743493 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13858743493 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13858743493 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13858743493 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13858743493 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8508503 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8508503 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8508503 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8508503 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8508503 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8508503 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111344 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.111344 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111344 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.111344 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111344 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.111344 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14628.695630 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14628.695630 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14628.695630 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14628.695630 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14628.695630 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14628.695630 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 7760 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 245 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 263 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.848980 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.505703 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 892272 # number of writebacks -system.cpu0.icache.writebacks::total 892272 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 52323 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 52323 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 52323 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 52323 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 52323 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 52323 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 893053 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 893053 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 893053 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 893053 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 893053 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 893053 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12259429995 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12259429995 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12259429995 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12259429995 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12259429995 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12259429995 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105703 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.105703 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.105703 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13727.550319 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13727.550319 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13727.550319 # average overall mshr miss latency -system.cpu1.branchPred.lookups 4441555 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3820450 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 114047 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2322340 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 883836 # Number of BTB hits +system.cpu0.icache.writebacks::writebacks 891919 # number of writebacks +system.cpu0.icache.writebacks::total 891919 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54705 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 54705 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 54705 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 54705 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 54705 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 54705 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 892662 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 892662 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 892662 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 892662 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 892662 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 892662 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12247880494 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12247880494 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12247880494 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12247880494 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12247880494 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12247880494 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.104914 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.104914 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.104914 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.104914 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.104914 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.104914 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13720.624933 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13720.624933 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13720.624933 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13720.624933 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13720.624933 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13720.624933 # average overall mshr miss latency +system.cpu1.branchPred.lookups 4440494 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3820633 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 114977 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2284731 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 882766 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 38.057993 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 229553 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 8671 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 1262341 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 163265 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1099076 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 40828 # Number of mispredicted indirect branches. +system.cpu1.branchPred.BTBHitPct 38.637634 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 229523 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 8540 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 1232926 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 164040 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1068886 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 40452 # Number of mispredicted indirect branches. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2431988 # DTB read hits -system.cpu1.dtb.read_misses 15687 # DTB read misses -system.cpu1.dtb.read_acv 78 # DTB read access violations -system.cpu1.dtb.read_accesses 432427 # DTB read accesses -system.cpu1.dtb.write_hits 1439876 # DTB write hits -system.cpu1.dtb.write_misses 3853 # DTB write misses -system.cpu1.dtb.write_acv 69 # DTB write access violations -system.cpu1.dtb.write_accesses 163205 # DTB write accesses -system.cpu1.dtb.data_hits 3871864 # DTB hits -system.cpu1.dtb.data_misses 19540 # DTB misses +system.cpu1.dtb.read_hits 2425125 # DTB read hits +system.cpu1.dtb.read_misses 16040 # DTB read misses +system.cpu1.dtb.read_acv 82 # DTB read access violations +system.cpu1.dtb.read_accesses 432289 # DTB read accesses +system.cpu1.dtb.write_hits 1438640 # DTB write hits +system.cpu1.dtb.write_misses 3531 # DTB write misses +system.cpu1.dtb.write_acv 65 # DTB write access violations +system.cpu1.dtb.write_accesses 162605 # DTB write accesses +system.cpu1.dtb.data_hits 3863765 # DTB hits +system.cpu1.dtb.data_misses 19571 # DTB misses system.cpu1.dtb.data_acv 147 # DTB access violations -system.cpu1.dtb.data_accesses 595632 # DTB accesses -system.cpu1.itb.fetch_hits 677957 # ITB hits -system.cpu1.itb.fetch_misses 3440 # ITB misses -system.cpu1.itb.fetch_acv 149 # ITB acv -system.cpu1.itb.fetch_accesses 681397 # ITB accesses +system.cpu1.dtb.data_accesses 594894 # DTB accesses +system.cpu1.itb.fetch_hits 679335 # ITB hits +system.cpu1.itb.fetch_misses 3486 # ITB misses +system.cpu1.itb.fetch_acv 144 # ITB acv +system.cpu1.itb.fetch_accesses 682821 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -993,584 +994,585 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numPwrStateTransitions 5092 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2546 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 746545753.142184 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 396892720.756326 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 2546 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 350000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 975495000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2546 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 8778464000 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1900705487500 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 17559475 # number of cpu cycles simulated +system.cpu1.numPwrStateTransitions 5088 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2544 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 747516916.077044 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 396242813.132808 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 2544 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 975504000 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2544 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 8774063000 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 1901683034500 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 17550671 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 7089129 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 17628986 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4441555 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1276654 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 9239971 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 379390 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 26991 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 67759 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 51232 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 58 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1981137 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 84838 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 16664835 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.057855 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.464288 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 7093737 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 17628277 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4440494 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1276329 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 9234250 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 381282 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 2 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 26389 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 68063 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 51076 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1982953 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 84304 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 16664213 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.057852 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.464693 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 13565594 81.40% 81.40% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 195508 1.17% 82.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 331371 1.99% 84.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 236250 1.42% 85.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 403775 2.42% 88.40% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 149802 0.90% 89.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 175422 1.05% 90.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 211560 1.27% 91.63% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1395553 8.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 13566532 81.41% 81.41% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 196080 1.18% 82.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 329765 1.98% 84.57% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 235529 1.41% 85.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 402874 2.42% 88.40% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 150126 0.90% 89.30% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 175137 1.05% 90.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 212228 1.27% 91.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1395942 8.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 16664835 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.252943 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.003959 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5800433 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 8202202 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2197206 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 282756 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 182237 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 153534 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7597 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 14400936 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 23892 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 182237 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5989487 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 906248 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 6023778 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2292128 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1270955 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 13634993 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 3736 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 109479 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 34532 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 648624 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 9050025 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 16251882 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 16185746 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59544 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 7082137 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1967880 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 511648 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 53659 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2285085 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2543631 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1545283 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 323334 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 171078 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 11953372 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 586667 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 11470583 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 27894 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2581702 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1224765 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 432970 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 16664835 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.688311 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.414763 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 16664213 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.253010 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.004422 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5803889 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 8198941 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2195429 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 282754 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 183199 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 845965 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 7619 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 14397519 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 23764 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 183199 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5993501 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 917111 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6016357 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2289218 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1264825 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 13624374 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 3775 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 108540 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 34178 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 643759 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 9046149 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 16244839 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 16178929 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59321 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 7078981 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1967160 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 511491 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 53621 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2283119 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2539964 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1543921 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 323106 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 168966 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 11939663 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 585885 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 11455956 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 28942 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2572399 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1228155 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 432246 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 16664213 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.687459 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.414504 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 11964424 71.79% 71.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2022081 12.13% 83.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 866450 5.20% 89.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 621081 3.73% 92.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 573042 3.44% 96.29% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 300412 1.80% 98.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 196836 1.18% 99.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 86957 0.52% 99.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 33552 0.20% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 11970475 71.83% 71.83% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2021121 12.13% 83.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 863574 5.18% 89.14% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 618225 3.71% 92.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 572472 3.44% 96.29% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 300775 1.80% 98.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 197233 1.18% 99.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 86853 0.52% 99.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 33485 0.20% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 16664835 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 16664213 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 33610 10.34% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMisc 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 173421 53.34% 63.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 102626 31.57% 95.25% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMemRead 8052 2.48% 97.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMemWrite 7405 2.28% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 33486 10.24% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMisc 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 173880 53.16% 63.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 104341 31.90% 95.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemRead 7997 2.44% 97.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemWrite 7375 2.25% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 4751 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 7105969 61.95% 61.99% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 17120 0.15% 62.14% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 14007 0.12% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2511504 21.90% 84.18% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1426032 12.43% 96.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMemRead 45143 0.39% 97.00% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMemWrite 43776 0.38% 97.39% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 299906 2.61% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 4756 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 7097834 61.96% 62.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 17086 0.15% 62.15% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 14002 0.12% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2506692 21.88% 84.17% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1424790 12.44% 96.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemRead 45041 0.39% 97.00% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemWrite 43535 0.38% 97.38% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 299845 2.62% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 11470583 # Type of FU issued -system.cpu1.iq.rate 0.653242 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 325114 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.028343 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 39732906 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 15018676 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 10950208 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 226102 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 108058 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 105069 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 11670188 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 120758 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 118257 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 11455956 # Type of FU issued +system.cpu1.iq.rate 0.652736 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 327079 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.028551 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 39706848 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 14995495 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 10932885 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 225297 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 107483 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 104737 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 11657954 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 120325 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 118525 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 553253 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1093 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 5172 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 179987 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 552207 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1214 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 5210 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 179004 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 535 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 99855 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 539 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 99906 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 182237 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 561579 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 275117 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 13190679 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 58497 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2543631 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1545283 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 532703 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 6805 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 266988 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 5172 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 45989 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 148806 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 194795 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 11280251 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2456871 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 190331 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 183199 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 564470 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 284501 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 13175740 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 58730 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2539964 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1543921 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 532175 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 7107 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 276039 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 5210 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 46730 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 149015 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 195745 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 11262138 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2450359 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 193817 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 650640 # number of nop insts executed -system.cpu1.iew.exec_refs 3907176 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1689156 # Number of branches executed -system.cpu1.iew.exec_stores 1450305 # Number of stores executed -system.cpu1.iew.exec_rate 0.642403 # Inst execution rate -system.cpu1.iew.wb_sent 11110028 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 11055277 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 5286560 # num instructions producing a value -system.cpu1.iew.wb_consumers 7445661 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.629590 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.710019 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 2598878 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 153697 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 169517 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 16202334 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.644600 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.619525 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 650192 # number of nop insts executed +system.cpu1.iew.exec_refs 3899095 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1684701 # Number of branches executed +system.cpu1.iew.exec_stores 1448736 # Number of stores executed +system.cpu1.iew.exec_rate 0.641693 # Inst execution rate +system.cpu1.iew.wb_sent 11092333 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 11037622 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 5277529 # num instructions producing a value +system.cpu1.iew.wb_consumers 7434192 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.628900 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.709899 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 2589103 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 153639 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 170452 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 16200161 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.644352 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.619659 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 12420063 76.66% 76.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1746761 10.78% 87.44% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 624490 3.85% 91.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 388127 2.40% 93.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 294767 1.82% 95.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 125393 0.77% 96.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 112323 0.69% 96.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 119344 0.74% 97.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 371066 2.29% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 12420478 76.67% 76.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1746852 10.78% 87.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 623239 3.85% 91.30% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 386399 2.39% 93.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 294857 1.82% 95.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 125210 0.77% 96.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 112311 0.69% 96.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 119786 0.74% 97.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 371029 2.29% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 16202334 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 10444029 # Number of instructions committed -system.cpu1.commit.committedOps 10444029 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 16200161 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 10438605 # Number of instructions committed +system.cpu1.commit.committedOps 10438605 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3355674 # Number of memory references committed -system.cpu1.commit.loads 1990378 # Number of loads committed -system.cpu1.commit.membars 48933 # Number of memory barriers committed -system.cpu1.commit.branches 1499197 # Number of branches committed -system.cpu1.commit.fp_insts 102946 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 9701123 # Number of committed integer instructions. -system.cpu1.commit.function_calls 163891 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 490447 4.70% 4.70% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 6215282 59.51% 64.21% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 16829 0.16% 64.37% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.37% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 13998 0.13% 64.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 64.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1994471 19.10% 83.62% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1324148 12.68% 96.30% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMemRead 44840 0.43% 96.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMemWrite 41733 0.40% 97.13% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 299906 2.87% 100.00% # Class of committed instruction +system.cpu1.commit.refs 3352674 # Number of memory references committed +system.cpu1.commit.loads 1987757 # Number of loads committed +system.cpu1.commit.membars 48909 # Number of memory barriers committed +system.cpu1.commit.branches 1497531 # Number of branches committed +system.cpu1.commit.fp_insts 102779 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 9696003 # Number of committed integer instructions. +system.cpu1.commit.function_calls 163829 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 490211 4.70% 4.70% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 6213226 59.52% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 16788 0.16% 64.38% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.38% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 13993 0.13% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1991924 19.08% 83.62% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1323832 12.68% 96.30% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemRead 44742 0.43% 96.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemWrite 41669 0.40% 97.13% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 299845 2.87% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 10444029 # Class of committed instruction -system.cpu1.commit.bw_lim_events 371066 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 28763808 # The number of ROB reads -system.cpu1.rob.rob_writes 26546353 # The number of ROB writes -system.cpu1.timesIdled 134909 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 894640 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3801408429 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 9958332 # Number of Instructions Simulated -system.cpu1.committedOps 9958332 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.763295 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.763295 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.567120 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.567120 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 14511646 # number of integer regfile reads -system.cpu1.int_regfile_writes 7905629 # number of integer regfile writes -system.cpu1.fp_regfile_reads 58867 # number of floating regfile reads -system.cpu1.fp_regfile_writes 57930 # number of floating regfile writes -system.cpu1.misc_regfile_reads 573957 # number of misc regfile reads -system.cpu1.misc_regfile_writes 245081 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 131073 # number of replacements -system.cpu1.dcache.tags.tagsinuse 488.756113 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3063603 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 131585 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.282312 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 49534380500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 488.756113 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.954602 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.954602 # Average percentage of cache occupancy +system.cpu1.commit.op_class_0::total 10438605 # Class of committed instruction +system.cpu1.commit.bw_lim_events 371029 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 28746473 # The number of ROB reads +system.cpu1.rob.rob_writes 26517839 # The number of ROB writes +system.cpu1.timesIdled 134718 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 886458 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3803363525 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 9953144 # Number of Instructions Simulated +system.cpu1.committedOps 9953144 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.763329 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.763329 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.567109 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.567109 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 14490611 # number of integer regfile reads +system.cpu1.int_regfile_writes 7893529 # number of integer regfile writes +system.cpu1.fp_regfile_reads 58631 # number of floating regfile reads +system.cpu1.fp_regfile_writes 57835 # number of floating regfile writes +system.cpu1.misc_regfile_reads 573327 # number of misc regfile reads +system.cpu1.misc_regfile_writes 245000 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 130880 # number of replacements +system.cpu1.dcache.tags.tagsinuse 488.755319 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3056587 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 131392 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.263113 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 49534102500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 488.755319 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.954600 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.954600 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 225 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 14519091 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 14519091 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 1948296 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1948296 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1026442 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1026442 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40668 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 40668 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 37243 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 37243 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2974738 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2974738 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2974738 # number of overall hits -system.cpu1.dcache.overall_hits::total 2974738 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 241303 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 241303 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 292103 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 292103 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5304 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5304 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3101 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3101 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 533406 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 533406 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 533406 # number of overall misses -system.cpu1.dcache.overall_misses::total 533406 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3375705500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3375705500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12203212844 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 12203212844 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 54365500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 54365500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 17261500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 17261500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 15578918344 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 15578918344 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 15578918344 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 15578918344 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2189599 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2189599 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1318545 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1318545 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 45972 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 45972 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 40344 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 40344 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3508144 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3508144 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3508144 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3508144 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110204 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.110204 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.221534 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.221534 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.115375 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.115375 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.076864 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.076864 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.152048 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.152048 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.152048 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.152048 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13989.488320 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13989.488320 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41777.088370 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 41777.088370 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10249.905732 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10249.905732 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5566.430184 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5566.430184 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29206.492510 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 29206.492510 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29206.492510 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 29206.492510 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 720965 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 386 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 24769 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 19 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 29.107554 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 20.315789 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 84598 # number of writebacks -system.cpu1.dcache.writebacks::total 84598 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148074 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 148074 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 243671 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 243671 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 852 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 852 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 391745 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 391745 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 391745 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 391745 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 93229 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 93229 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 48432 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 48432 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4452 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4452 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3100 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 3100 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 141661 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 141661 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 141661 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 141661 # number of overall MSHR misses +system.cpu1.dcache.tags.tag_accesses 14487576 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 14487576 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 1941589 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1941589 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1026269 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1026269 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40594 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 40594 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 37239 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 37239 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2967858 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2967858 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2967858 # number of overall hits +system.cpu1.dcache.overall_hits::total 2967858 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 240679 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 240679 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 291916 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 291916 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5260 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5260 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3088 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3088 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 532595 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 532595 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 532595 # number of overall misses +system.cpu1.dcache.overall_misses::total 532595 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3354943500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3354943500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12208160588 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 12208160588 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 53604000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 53604000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 17137500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 17137500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 15563104088 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 15563104088 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 15563104088 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 15563104088 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2182268 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2182268 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1318185 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1318185 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 45854 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 45854 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 40327 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 40327 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3500453 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3500453 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3500453 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3500453 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110288 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.110288 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.221453 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.221453 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.114712 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.114712 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.076574 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.076574 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.152150 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.152150 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.152150 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.152150 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13939.494098 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13939.494098 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41820.799778 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 41820.799778 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10190.874525 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10190.874525 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5549.708549 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5549.708549 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29221.273365 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 29221.273365 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29221.273365 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 29221.273365 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 720106 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 464 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 24866 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 14 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 28.959463 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 33.142857 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 84401 # number of writebacks +system.cpu1.dcache.writebacks::total 84401 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 147677 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 147677 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 243516 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 243516 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 792 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 792 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 391193 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 391193 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 391193 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 391193 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 93002 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 93002 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 48400 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 48400 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4468 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4468 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3088 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 3088 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 141402 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 141402 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 141402 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 141402 # number of overall MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 218 # number of ReadReq MSHR uncacheable system.cpu1.dcache.ReadReq_mshr_uncacheable::total 218 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3157 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3157 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3375 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3375 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1262260500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1262260500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1962212693 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1962212693 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 40045500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 40045500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14161500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14161500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3224473193 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3224473193 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3224473193 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3224473193 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 41860500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 41860500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 41860500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 41860500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042578 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042578 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036731 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036731 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.096842 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.096842 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.076839 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.076839 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040381 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.040381 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040381 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.040381 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13539.354707 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13539.354707 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40514.797923 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40514.797923 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8994.946092 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8994.946092 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4568.225806 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4568.225806 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22761.897721 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22761.897721 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22761.897721 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22761.897721 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 192020.642202 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192020.642202 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 12403.111111 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 12403.111111 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 256867 # number of replacements -system.cpu1.icache.tags.tagsinuse 470.812016 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1711658 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 257379 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 6.650341 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1882992885500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.812016 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919555 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.919555 # Average percentage of cache occupancy +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3156 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3156 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3374 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3374 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1257789500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1257789500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1961692747 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1961692747 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 39632000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 39632000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14049500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14049500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3219482247 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3219482247 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3219482247 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3219482247 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 41842500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 41842500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 41842500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 41842500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042617 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042617 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036717 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036717 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.097440 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.097440 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.076574 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.076574 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040395 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.040395 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040395 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.040395 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13524.327434 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13524.327434 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40530.841880 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40530.841880 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8870.188004 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8870.188004 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4549.708549 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4549.708549 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22768.293567 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22768.293567 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22768.293567 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22768.293567 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191938.073394 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191938.073394 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 12401.452282 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 12401.452282 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 256309 # number of replacements +system.cpu1.icache.tags.tagsinuse 470.814625 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1714023 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 256821 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 6.673999 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1883968823500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.814625 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919560 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.919560 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 2238596 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 2238596 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 1711658 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1711658 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1711658 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1711658 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1711658 # number of overall hits -system.cpu1.icache.overall_hits::total 1711658 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 269479 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 269479 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 269479 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 269479 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 269479 # number of overall misses -system.cpu1.icache.overall_misses::total 269479 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3760599998 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3760599998 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3760599998 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3760599998 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3760599998 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3760599998 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1981137 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1981137 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1981137 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1981137 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1981137 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1981137 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.136022 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.136022 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.136022 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.136022 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.136022 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.136022 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13955.076269 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13955.076269 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13955.076269 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13955.076269 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13955.076269 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13955.076269 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 535 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 2239848 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 2239848 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 1714023 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1714023 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1714023 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1714023 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1714023 # number of overall hits +system.cpu1.icache.overall_hits::total 1714023 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 268930 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 268930 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 268930 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 268930 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 268930 # number of overall misses +system.cpu1.icache.overall_misses::total 268930 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3748012499 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3748012499 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3748012499 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3748012499 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3748012499 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3748012499 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1982953 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1982953 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1982953 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1982953 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1982953 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1982953 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.135621 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.135621 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.135621 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.135621 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.135621 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.135621 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13936.758632 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13936.758632 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13936.758632 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13936.758632 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13936.758632 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13936.758632 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 558 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 47 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 46 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.382979 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.130435 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 256867 # number of writebacks -system.cpu1.icache.writebacks::total 256867 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12020 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 12020 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 12020 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 12020 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 12020 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 12020 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 257459 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 257459 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 257459 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 257459 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 257459 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 257459 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3369785998 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3369785998 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3369785998 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3369785998 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3369785998 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3369785998 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.129955 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.129955 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.129955 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.129955 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.129955 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.129955 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13088.631580 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13088.631580 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13088.631580 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13088.631580 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13088.631580 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13088.631580 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 256309 # number of writebacks +system.cpu1.icache.writebacks::total 256309 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12035 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 12035 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 12035 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 12035 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 12035 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 12035 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 256895 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 256895 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 256895 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 256895 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 256895 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 256895 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3358325499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3358325499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3358325499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3358325499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3358325499 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3358325499 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.129552 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.129552 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.129552 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.129552 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.129552 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.129552 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13072.755402 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13072.755402 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13072.755402 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13072.755402 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13072.755402 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13072.755402 # average overall mshr miss latency system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1583,12 +1585,12 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7374 # Transaction distribution system.iobus.trans_dist::ReadResp 7374 # Transaction distribution -system.iobus.trans_dist::WriteReq 54619 # Transaction distribution -system.iobus.trans_dist::WriteResp 54619 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11924 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 54617 # Transaction distribution +system.iobus.trans_dist::WriteResp 54617 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11920 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1597,11 +1599,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1814 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40524 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40520 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123986 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 123982 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47680 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1610,50 +1612,50 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 73922 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 73906 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2735578 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 12373500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2735562 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 12368500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 816500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 820500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 179500 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 176500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14090000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14153500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2829500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2825500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6041501 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6058000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 89000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216274759 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216256520 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27457000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27455000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41958000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41699 # number of replacements -system.iocache.tags.tagsinuse 0.506657 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.514549 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1714262526000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.506657 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.031666 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.031666 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1714263350000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.514549 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.032159 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.032159 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375579 # Number of tag accesses system.iocache.tags.data_accesses 375579 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses system.iocache.ReadReq_misses::total 179 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1662,14 +1664,14 @@ system.iocache.demand_misses::tsunami.ide 41731 # n system.iocache.demand_misses::total 41731 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses system.iocache.overall_misses::total 41731 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22653383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22653383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4913989376 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4913989376 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4936642759 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4936642759 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4936642759 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4936642759 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 22652883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22652883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4915863637 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4915863637 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4938516520 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4938516520 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4938516520 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4938516520 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1686,19 +1688,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126555.212291 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126555.212291 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118261.199846 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118261.199846 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 118296.775994 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118296.775994 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 118296.775994 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118296.775994 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 945 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126552.418994 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126552.418994 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118306.306243 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118306.306243 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 118341.676931 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118341.676931 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 118341.676931 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118341.676931 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 695 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 135 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 173.750000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks @@ -1710,14 +1712,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41731 system.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13703383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13703383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2833958851 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2833958851 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2847662234 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2847662234 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2847662234 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2847662234 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13702883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13702883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2835827584 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2835827584 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2849530467 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2849530467 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2849530467 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2849530467 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1726,454 +1728,455 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76555.212291 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76555.212291 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68202.706272 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68202.706272 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68238.533321 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68238.533321 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68238.533321 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68238.533321 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 345934 # number of replacements -system.l2c.tags.tagsinuse 65423.183339 # Cycle average of tags in use -system.l2c.tags.total_refs 4331268 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 411456 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 10.526686 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 6416563000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 293.472249 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5322.167822 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58815.337446 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 207.084290 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 785.121532 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.004478 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.081210 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.897451 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003160 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011980 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998279 # Average percentage of cache occupancy +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76552.418994 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76552.418994 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68247.679630 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68247.679630 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68283.301790 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68283.301790 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68283.301790 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68283.301790 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 345895 # number of replacements +system.l2c.tags.tagsinuse 65423.250509 # Cycle average of tags in use +system.l2c.tags.total_refs 4330734 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 411417 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.526386 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 6416604000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 292.398395 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5320.578215 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58825.194930 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 208.100344 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 776.978626 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.004462 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.081186 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.897601 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003175 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.011856 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998280 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1689 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1849 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 9122 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52734 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1663 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1868 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5665 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56191 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 38356372 # Number of tag accesses -system.l2c.tags.data_accesses 38356372 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 822171 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 822171 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 873935 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 873935 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 2863 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1523 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 4386 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 498 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 473 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 971 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 145860 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 30930 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 176790 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 879457 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 255503 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1134960 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 721850 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 84138 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 805988 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 879457 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 867710 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 255503 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 115068 # number of demand (read+write) hits -system.l2c.demand_hits::total 2117738 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 879457 # number of overall hits -system.l2c.overall_hits::cpu0.data 867710 # number of overall hits -system.l2c.overall_hits::cpu1.inst 255503 # number of overall hits -system.l2c.overall_hits::cpu1.data 115068 # number of overall hits -system.l2c.overall_hits::total 2117738 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4 # number of UpgradeReq misses +system.l2c.tags.tag_accesses 38351741 # Number of tag accesses +system.l2c.tags.data_accesses 38351741 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 822397 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 822397 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 872029 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 872029 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 2840 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 1502 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 4342 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 501 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 466 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 967 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 145832 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 30945 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 176777 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 879111 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 254952 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1134063 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 723239 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 83990 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 807229 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 879111 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 869071 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 254952 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 114935 # number of demand (read+write) hits +system.l2c.demand_hits::total 2118069 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 879111 # number of overall hits +system.l2c.overall_hits::cpu0.data 869071 # number of overall hits +system.l2c.overall_hits::cpu1.inst 254952 # number of overall hits +system.l2c.overall_hits::cpu1.data 114935 # number of overall hits +system.l2c.overall_hits::total 2118069 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 7 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 5 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 12 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 109487 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 12067 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 121554 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 13403 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 1908 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 15311 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 272678 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 1963 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 274641 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 13403 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 382165 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1908 # number of demand (read+write) misses +system.l2c.ReadExReq_misses::cpu0.data 109607 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 12062 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 121669 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 13385 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 1902 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 15287 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 272541 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 1968 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 274509 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.inst 13385 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 382148 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1902 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 14030 # number of demand (read+write) misses -system.l2c.demand_misses::total 411506 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13403 # number of overall misses -system.l2c.overall_misses::cpu0.data 382165 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1908 # number of overall misses +system.l2c.demand_misses::total 411465 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13385 # number of overall misses +system.l2c.overall_misses::cpu0.data 382148 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1902 # number of overall misses system.l2c.overall_misses::cpu1.data 14030 # number of overall misses -system.l2c.overall_misses::total 411506 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 390000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 86500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 476500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 11308218500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1532406000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 12840624500 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1352141000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 194316500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 1546457500 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 22230634500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 227734000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 22458368500 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1352141000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 33538853000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 194316500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1760140000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 36845450500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1352141000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 33538853000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 194316500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1760140000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 36845450500 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 822171 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 822171 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 873935 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 873935 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2871 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1527 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4398 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 498 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 474 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 972 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 255347 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 42997 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 298344 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 892860 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 257411 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1150271 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 994528 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 86101 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1080629 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 892860 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1249875 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 257411 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 129098 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2529244 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 892860 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1249875 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 257411 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 129098 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2529244 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.002786 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.002620 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.002729 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.002110 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.001029 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.428777 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.280647 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.407429 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.015011 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007412 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013311 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.274178 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.022799 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.254149 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015011 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.305763 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.007412 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.108677 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.162699 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015011 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.305763 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.007412 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.108677 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.162699 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 48750 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 21625 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 39708.333333 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 103283.663814 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 126991.464324 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 105637.202396 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 100883.458927 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 101843.029350 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 101003.037032 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 81527.055721 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 116013.245033 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 81773.546193 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 100883.458927 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 87760.137637 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 101843.029350 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 125455.452602 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 89538.063844 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 100883.458927 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 87760.137637 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 101843.029350 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 125455.452602 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 89538.063844 # average overall miss latency +system.l2c.overall_misses::total 411465 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 361500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 116000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 477500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 11326788500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1531540500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 12858329000 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1345659000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 188021500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 1533680500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 22177607000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 225042000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 22402649000 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1345659000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 33504395500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 188021500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1756582500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 36794658500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1345659000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 33504395500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 188021500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1756582500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 36794658500 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 822397 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 822397 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 872029 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 872029 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2847 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1507 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4354 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 501 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 467 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 968 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 255439 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 43007 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 298446 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 892496 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 256854 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1149350 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 995780 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 85958 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1081738 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 892496 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1251219 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 256854 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 128965 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2529534 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 892496 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1251219 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 256854 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 128965 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2529534 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.002459 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.003318 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.002756 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.002141 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.001033 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.429093 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.280466 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.407675 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.014997 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007405 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.013301 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.273696 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.022895 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.253767 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014997 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.305421 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.007405 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.108789 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.162664 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014997 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.305421 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.007405 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.108789 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.162664 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 51642.857143 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 23200 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 39791.666667 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 103340.010218 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 126972.351186 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 105682.869096 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 100534.852447 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 98854.626709 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 100325.799699 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 81373.470414 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 114350.609756 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 81609.888929 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 100534.852447 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 87673.873735 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 98854.626709 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 125201.888810 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 89423.543922 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 100534.852447 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 87673.873735 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 98854.626709 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 125201.888810 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 89423.543922 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 82080 # number of writebacks -system.l2c.writebacks::total 82080 # number of writebacks -system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits -system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 17 # number of ReadCleanReq MSHR hits -system.l2c.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 17 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits +system.l2c.writebacks::writebacks 82068 # number of writebacks +system.l2c.writebacks::total 82068 # number of writebacks +system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 16 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::total 16 # number of ReadCleanReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.data 1 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 1 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 16 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 17 # number of overall MSHR hits system.l2c.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses system.l2c.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 8 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 4 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 7 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 5 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 12 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 109487 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 12067 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 121554 # number of ReadExReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 13402 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1891 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::total 15293 # number of ReadCleanReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 272678 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1963 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 274641 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 13402 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 382165 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1891 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 14030 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 411488 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 13402 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 382165 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1891 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 14030 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 411488 # number of overall MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 109607 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 12062 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 121669 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 13385 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1886 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 15271 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 272541 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1967 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 274508 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13385 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 382148 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1886 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 14029 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 411448 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13385 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 382148 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1886 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 14029 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 411448 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.data 6977 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.data 218 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::total 7195 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 9910 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3157 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 13067 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 16887 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3375 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 20262 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 310000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 75000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 385000 # number of UpgradeReq MSHR miss cycles +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 9909 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3156 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 13065 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 16886 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3374 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 20260 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 291500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 94500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 386000 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 18500 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 18500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 10213348500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1411735501 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 11625084001 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1218034000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 174078000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 1392112000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19509738001 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 208104000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 19717842001 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1218034000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 29723086501 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 174078000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1619839501 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 32735038002 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1218034000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 29723086501 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 174078000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1619839501 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 32735038002 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1469912000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 39135500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1509047500 # number of ReadReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1469912000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 39135500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1509047500 # number of overall MSHR uncacheable cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 10230718500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1410920500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 11641639000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1211809000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 167908000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 1379717000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19458079003 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 205283000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 19663362003 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1211809000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 29688797503 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 167908000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1616203500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 32684718003 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1211809000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 29688797503 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 167908000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1616203500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 32684718003 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1470022500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 39117500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1509140000 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1470022500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 39117500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1509140000 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.002786 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.002620 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.002729 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.002110 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.428777 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.280647 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.407429 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.015010 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007346 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013295 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.274178 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.022799 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254149 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015010 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.305763 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007346 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.108677 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.162692 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015010 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.305763 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007346 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.108677 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.162692 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 38750 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18750 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 32083.333333 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.002459 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.003318 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.002756 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.002141 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.001033 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.429093 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.280466 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.407675 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.014997 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007343 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013287 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.273696 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.022883 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.253766 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014997 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.305421 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007343 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.108781 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.162658 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014997 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.305421 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007343 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.108781 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.162658 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 41642.857143 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18900 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 32166.666667 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 18500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93283.663814 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 116991.422972 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 95637.198290 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 91029.359838 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 71548.632457 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 106013.245033 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71794.968708 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77775.532822 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 115455.417035 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 79552.837512 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77775.532822 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 115455.417035 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 79552.837512 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210679.661746 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179520.642202 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209735.580264 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87043.998342 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 11595.703704 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 74476.729839 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 852121 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 399760 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 540 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93340.010218 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 116972.351186 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 95682.869096 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 90534.852447 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 89028.632025 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 90348.831118 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 71395.052499 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 104363.497712 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71631.289445 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90534.852447 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77689.265685 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 89028.632025 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 115204.469314 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 79438.271672 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90534.852447 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77689.265685 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 89028.632025 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 115204.469314 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 79438.271672 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210695.499498 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179438.073394 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209748.436414 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87055.697027 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 11593.805572 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 74488.647581 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 851998 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 399673 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 538 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7195 # Transaction distribution -system.membus.trans_dist::ReadResp 297263 # Transaction distribution -system.membus.trans_dist::WriteReq 13067 # Transaction distribution -system.membus.trans_dist::WriteResp 13067 # Transaction distribution -system.membus.trans_dist::WritebackDirty 123600 # Transaction distribution -system.membus.trans_dist::CleanEvict 263134 # Transaction distribution -system.membus.trans_dist::UpgradeReq 6631 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5160 # Transaction distribution +system.membus.trans_dist::ReadResp 297108 # Transaction distribution +system.membus.trans_dist::WriteReq 13065 # Transaction distribution +system.membus.trans_dist::WriteResp 13065 # Transaction distribution +system.membus.trans_dist::WritebackDirty 123588 # Transaction distribution +system.membus.trans_dist::CleanEvict 263109 # Transaction distribution +system.membus.trans_dist::UpgradeReq 6612 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5150 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 121851 # Transaction distribution -system.membus.trans_dist::ReadExResp 121443 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 290113 # Transaction distribution +system.membus.trans_dist::ReadExReq 121960 # Transaction distribution +system.membus.trans_dist::ReadExResp 121558 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289958 # Transaction distribution system.membus.trans_dist::BadAddressError 45 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 134 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40524 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179612 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40520 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179462 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 90 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1220226 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1220072 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83445 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83445 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1303671 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73922 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31560064 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31633986 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1303517 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73906 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31556864 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31630770 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34292226 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 12662 # Total snoops (count) -system.membus.snoopTraffic 28800 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 485569 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001425 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.037724 # Request fanout histogram +system.membus.pkt_size::total 34289010 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 12625 # Total snoops (count) +system.membus.snoopTraffic 28672 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 485492 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001421 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.037673 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 484877 99.86% 99.86% # Request fanout histogram -system.membus.snoop_fanout::1 692 0.14% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 484802 99.86% 99.86% # Request fanout histogram +system.membus.snoop_fanout::1 690 0.14% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 485569 # Request fanout histogram -system.membus.reqLayer0.occupancy 36441999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 485492 # Request fanout histogram +system.membus.reqLayer0.occupancy 36514000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1353891077 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1353680299 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 56500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 56000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2179677750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2179395750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1104580 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1105081 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5103299 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2546186 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 356313 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1076 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1008 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 5103450 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2546310 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 356575 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1075 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1007 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2260964 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13067 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13067 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 904251 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1149139 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 825400 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 10906 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 6131 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 17037 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 299755 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 299755 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1150512 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1103306 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2260935 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13065 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13065 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 904465 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1148228 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 826225 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 10843 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 6117 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 16960 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 299845 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 299845 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1149557 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1104232 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 45 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution system.toL2Bus.trans_dist::InvalidateResp 2 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2678185 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3810494 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 771737 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 418186 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7678602 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 114248448 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 127253332 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32913792 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13701358 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 288116930 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 382331 # Total snoops (count) -system.toL2Bus.snoopTraffic 6809920 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 2937042 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.126206 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.332589 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2677077 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3814281 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 770058 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 417575 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7678991 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 114202560 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 127366412 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32842432 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13680230 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 288091634 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 382034 # Total snoops (count) +system.toL2Bus.snoopTraffic 6794496 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 2936985 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.126280 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.332605 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2566846 87.40% 87.40% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 369740 12.59% 99.98% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 436 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 20 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2566512 87.39% 87.39% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 370085 12.60% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 367 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 21 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2937042 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4539664918 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2936985 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4539093837 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 302885 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 303384 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1341208229 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1340375720 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1910262297 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1912124205 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 387640565 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 386934286 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 217884535 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 217615473 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -2205,142 +2208,142 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6478 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 176731 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 62783 40.27% 40.27% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6479 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 176756 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 62790 40.27% 40.27% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 131 0.08% 40.36% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1927 1.24% 41.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 182 0.12% 41.71% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 90863 58.29% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 155886 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 61769 49.18% 49.18% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1927 1.53% 50.82% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 182 0.14% 50.96% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 61587 49.04% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 125596 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1864292107000 97.65% 97.65% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 64306500 0.00% 97.65% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 577089500 0.03% 97.68% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 88747000 0.00% 97.69% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 44160796000 2.31% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1909183046000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.983849 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_count::22 1928 1.24% 41.59% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 181 0.12% 41.71% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 90883 58.29% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 155913 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 61775 49.18% 49.18% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1928 1.53% 50.82% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 181 0.14% 50.96% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 61594 49.04% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 125609 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1865241808000 97.65% 97.65% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 64326000 0.00% 97.65% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 577244500 0.03% 97.68% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 87620000 0.00% 97.69% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 44188694000 2.31% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1910159692500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983835 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.677801 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.805691 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.677729 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.805635 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 294 0.18% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wripir 293 0.18% 0.18% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3351 2.05% 2.23% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3349 2.05% 2.23% # number of callpals executed system.cpu0.kern.callpal::tbi 48 0.03% 2.26% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed -system.cpu0.kern.callpal::swpipl 149332 91.35% 93.61% # number of callpals executed -system.cpu0.kern.callpal::rdps 5685 3.48% 97.09% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.26% # number of callpals executed +system.cpu0.kern.callpal::swpipl 149358 91.35% 93.61% # number of callpals executed +system.cpu0.kern.callpal::rdps 5686 3.48% 97.09% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.09% # number of callpals executed system.cpu0.kern.callpal::wrusp 1 0.00% 97.09% # number of callpals executed system.cpu0.kern.callpal::rdusp 8 0.00% 97.09% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::rti 4313 2.64% 99.73% # number of callpals executed +system.cpu0.kern.callpal::rti 4314 2.64% 99.73% # number of callpals executed system.cpu0.kern.callpal::callsys 303 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal::imb 132 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 163481 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6669 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1070 # number of protection mode switches +system.cpu0.kern.callpal::total 163506 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6667 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1071 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1070 -system.cpu0.kern.mode_good::user 1070 +system.cpu0.kern.mode_good::kernel 1071 +system.cpu0.kern.mode_good::user 1071 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.160444 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.160642 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.276522 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1907148784500 99.91% 99.91% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1683022000 0.09% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.276816 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1908119380500 99.91% 99.91% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1686628500 0.09% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3352 # number of times the context was actually changed +system.cpu0.kern.swap_context 3350 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2546 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 62928 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 19570 37.60% 37.60% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1925 3.70% 41.30% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 294 0.56% 41.86% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 30260 58.14% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 52049 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 19207 47.61% 47.61% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1925 4.77% 52.39% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 294 0.73% 53.11% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 18913 46.89% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 40339 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1874881279000 98.19% 98.19% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 565111500 0.03% 98.22% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 141720000 0.01% 98.22% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 33895004500 1.78% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1909483115000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.981451 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2544 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 62917 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 19565 37.60% 37.60% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1926 3.70% 41.30% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 293 0.56% 41.86% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 30256 58.14% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 52040 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 19203 47.61% 47.61% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1926 4.78% 52.39% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 293 0.73% 53.11% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 18910 46.89% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 40332 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1875855078000 98.19% 98.19% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 566007000 0.03% 98.22% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 141529500 0.01% 98.23% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 33893640500 1.77% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1910456255000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.981498 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.625017 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.775020 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.625000 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.775019 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 182 0.33% 0.34% # number of callpals executed +system.cpu1.kern.callpal::wripir 181 0.33% 0.33% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1230 2.25% 2.59% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1228 2.25% 2.59% # number of callpals executed system.cpu1.kern.callpal::tbi 5 0.01% 2.60% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 2.61% # number of callpals executed -system.cpu1.kern.callpal::swpipl 46579 85.30% 87.91% # number of callpals executed -system.cpu1.kern.callpal::rdps 3079 5.64% 93.55% # number of callpals executed +system.cpu1.kern.callpal::swpipl 46571 85.30% 87.91% # number of callpals executed +system.cpu1.kern.callpal::rdps 3080 5.64% 93.55% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 93.55% # number of callpals executed system.cpu1.kern.callpal::wrusp 6 0.01% 93.56% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.56% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.57% # number of callpals executed system.cpu1.kern.callpal::whami 3 0.01% 93.57% # number of callpals executed -system.cpu1.kern.callpal::rti 3250 5.95% 99.52% # number of callpals executed +system.cpu1.kern.callpal::rti 3249 5.95% 99.52% # number of callpals executed system.cpu1.kern.callpal::callsys 212 0.39% 99.91% # number of callpals executed system.cpu1.kern.callpal::imb 48 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 54607 # number of callpals executed +system.cpu1.kern.callpal::total 54596 # number of callpals executed system.cpu1.kern.mode_switch::kernel 1700 # number of protection mode switches -system.cpu1.kern.mode_switch::user 670 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2433 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 890 -system.cpu1.kern.mode_good::user 670 -system.cpu1.kern.mode_good::idle 220 -system.cpu1.kern.mode_switch_good::kernel 0.523529 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch::user 669 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2431 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 888 +system.cpu1.kern.mode_good::user 669 +system.cpu1.kern.mode_good::idle 219 +system.cpu1.kern.mode_switch_good::kernel 0.522353 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.090423 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.370602 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 5328500500 0.28% 0.28% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1057436000 0.06% 0.33% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1903097170500 99.67% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1231 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.090086 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.370000 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 5325548500 0.28% 0.28% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1057057500 0.06% 0.33% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1904073641000 99.67% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1229 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 5af666630..df3a97326 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,114 +1,114 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.865010 # Number of seconds simulated -sim_ticks 1865009748000 # Number of ticks simulated -final_tick 1865009748000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.865014 # Number of seconds simulated +sim_ticks 1865014104500 # Number of ticks simulated +final_tick 1865014104500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 235871 # Simulator instruction rate (inst/s) -host_op_rate 235870 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8303287371 # Simulator tick rate (ticks/s) -host_mem_usage 337912 # Number of bytes of host memory used -host_seconds 224.61 # Real time elapsed on the host -sim_insts 52979108 # Number of instructions simulated -sim_ops 52979108 # Number of ops (including micro ops) simulated +host_inst_rate 231832 # Simulator instruction rate (inst/s) +host_op_rate 231832 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8163594872 # Simulator tick rate (ticks/s) +host_mem_usage 339292 # Number of bytes of host memory used +host_seconds 228.46 # Real time elapsed on the host +sim_insts 52963270 # Number of instructions simulated +sim_ops 52963270 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 962240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24880192 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 962304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24880000 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25843392 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 962240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 962240 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7516224 # Number of bytes written to this memory -system.physmem.bytes_written::total 7516224 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15035 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388753 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25843264 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 962304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 962304 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7514304 # Number of bytes written to this memory +system.physmem.bytes_written::total 7514304 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15036 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388750 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403803 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117441 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117441 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 515944 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13340516 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403801 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117411 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117411 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 515977 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13340382 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13856974 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 515944 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 515944 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4030126 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4030126 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4030126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 515944 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13340516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13856873 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 515977 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 515977 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4029087 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4029087 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4029087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 515977 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13340382 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17887100 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403803 # Number of read requests accepted -system.physmem.writeReqs 117441 # Number of write requests accepted -system.physmem.readBursts 403803 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117441 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25835712 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue -system.physmem.bytesWritten 7515136 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25843392 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7516224 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17885960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403801 # Number of read requests accepted +system.physmem.writeReqs 117411 # Number of write requests accepted +system.physmem.readBursts 403801 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117411 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25836480 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue +system.physmem.bytesWritten 7512704 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25843264 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7514304 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25444 # Per bank write bursts -system.physmem.perBankRdBursts::1 25611 # Per bank write bursts -system.physmem.perBankRdBursts::2 25628 # Per bank write bursts -system.physmem.perBankRdBursts::3 25719 # Per bank write bursts -system.physmem.perBankRdBursts::4 25100 # Per bank write bursts -system.physmem.perBankRdBursts::5 25088 # Per bank write bursts -system.physmem.perBankRdBursts::6 24758 # Per bank write bursts -system.physmem.perBankRdBursts::7 24649 # Per bank write bursts -system.physmem.perBankRdBursts::8 24903 # Per bank write bursts -system.physmem.perBankRdBursts::9 25188 # Per bank write bursts -system.physmem.perBankRdBursts::10 25284 # Per bank write bursts -system.physmem.perBankRdBursts::11 25005 # Per bank write bursts -system.physmem.perBankRdBursts::12 24375 # Per bank write bursts -system.physmem.perBankRdBursts::13 25430 # Per bank write bursts +system.physmem.perBankRdBursts::0 25442 # Per bank write bursts +system.physmem.perBankRdBursts::1 25616 # Per bank write bursts +system.physmem.perBankRdBursts::2 25500 # Per bank write bursts +system.physmem.perBankRdBursts::3 25612 # Per bank write bursts +system.physmem.perBankRdBursts::4 25113 # Per bank write bursts +system.physmem.perBankRdBursts::5 25182 # Per bank write bursts +system.physmem.perBankRdBursts::6 24743 # Per bank write bursts +system.physmem.perBankRdBursts::7 24567 # Per bank write bursts +system.physmem.perBankRdBursts::8 25026 # Per bank write bursts +system.physmem.perBankRdBursts::9 25298 # Per bank write bursts +system.physmem.perBankRdBursts::10 25283 # Per bank write bursts +system.physmem.perBankRdBursts::11 25011 # Per bank write bursts +system.physmem.perBankRdBursts::12 24384 # Per bank write bursts +system.physmem.perBankRdBursts::13 25424 # Per bank write bursts system.physmem.perBankRdBursts::14 25804 # Per bank write bursts -system.physmem.perBankRdBursts::15 25697 # Per bank write bursts -system.physmem.perBankWrBursts::0 7804 # Per bank write bursts -system.physmem.perBankWrBursts::1 7583 # Per bank write bursts -system.physmem.perBankWrBursts::2 7900 # Per bank write bursts -system.physmem.perBankWrBursts::3 7698 # Per bank write bursts -system.physmem.perBankWrBursts::4 7224 # Per bank write bursts -system.physmem.perBankWrBursts::5 7092 # Per bank write bursts -system.physmem.perBankWrBursts::6 6759 # Per bank write bursts -system.physmem.perBankWrBursts::7 6515 # Per bank write bursts -system.physmem.perBankWrBursts::8 7053 # Per bank write bursts -system.physmem.perBankWrBursts::9 6824 # Per bank write bursts +system.physmem.perBankRdBursts::15 25690 # Per bank write bursts +system.physmem.perBankWrBursts::0 7803 # Per bank write bursts +system.physmem.perBankWrBursts::1 7588 # Per bank write bursts +system.physmem.perBankWrBursts::2 7778 # Per bank write bursts +system.physmem.perBankWrBursts::3 7603 # Per bank write bursts +system.physmem.perBankWrBursts::4 7231 # Per bank write bursts +system.physmem.perBankWrBursts::5 7190 # Per bank write bursts +system.physmem.perBankWrBursts::6 6745 # Per bank write bursts +system.physmem.perBankWrBursts::7 6418 # Per bank write bursts +system.physmem.perBankWrBursts::8 7146 # Per bank write bursts +system.physmem.perBankWrBursts::9 6920 # Per bank write bursts system.physmem.perBankWrBursts::10 7197 # Per bank write bursts system.physmem.perBankWrBursts::11 7005 # Per bank write bursts -system.physmem.perBankWrBursts::12 6955 # Per bank write bursts -system.physmem.perBankWrBursts::13 7882 # Per bank write bursts +system.physmem.perBankWrBursts::12 6963 # Per bank write bursts +system.physmem.perBankWrBursts::13 7878 # Per bank write bursts system.physmem.perBankWrBursts::14 8018 # Per bank write bursts -system.physmem.perBankWrBursts::15 7915 # Per bank write bursts +system.physmem.perBankWrBursts::15 7903 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 65 # Number of times write queue was full causing retry -system.physmem.totGap 1865004470500 # Total gap between requests +system.physmem.numWrRetry 61 # Number of times write queue was full causing retry +system.physmem.totGap 1865008869500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403803 # Read request sizes (log2) +system.physmem.readPktSize::6 403801 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117441 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 314056 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 36501 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28766 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117411 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 314099 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 36538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28723 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24204 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -149,115 +149,116 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 159 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61362 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 543.503536 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 333.365701 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.323842 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13476 21.96% 21.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10707 17.45% 39.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4479 7.30% 46.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2678 4.36% 51.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2195 3.58% 54.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1843 3.00% 57.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1874 3.05% 60.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1552 2.53% 63.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22558 36.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61362 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5160 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.231977 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2938.731055 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5157 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 418 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 139 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61269 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 544.301360 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 334.095290 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.294475 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13441 21.94% 21.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10649 17.38% 39.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4420 7.21% 46.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2704 4.41% 50.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2252 3.68% 54.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1833 2.99% 57.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1848 3.02% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1534 2.50% 63.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22588 36.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61269 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5165 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.156438 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2937.375866 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5162 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5160 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5160 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.756589 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.921420 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.589297 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4641 89.94% 89.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 34 0.66% 90.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 173 3.35% 93.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 9 0.17% 94.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 2 0.04% 94.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 16 0.31% 94.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 8 0.16% 94.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 3 0.06% 94.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 29 0.56% 95.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 4 0.08% 95.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 150 2.91% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 19 0.37% 98.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 6 0.12% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 5 0.10% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 7 0.14% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 2 0.04% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 3 0.06% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 7 0.14% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 5 0.10% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 10 0.19% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 13 0.25% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 4 0.08% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.08% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 3 0.06% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5160 # Writes before turning the bus around for reads -system.physmem.totQLat 7817102750 # Total ticks spent queuing -system.physmem.totMemAccLat 15386159000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2018415000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19364.46 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5165 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5165 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.727202 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.973066 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.761118 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4630 89.64% 89.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 34 0.66% 90.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 183 3.54% 93.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 6 0.12% 93.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 3 0.06% 94.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 17 0.33% 94.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 10 0.19% 94.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 3 0.06% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 30 0.58% 95.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 4 0.08% 95.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 158 3.06% 98.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 16 0.31% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 13 0.25% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 4 0.08% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 6 0.12% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 2 0.04% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 2 0.04% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 3 0.06% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 6 0.12% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 6 0.12% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 9 0.17% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 8 0.15% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 2 0.04% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 5 0.10% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5165 # Writes before turning the bus around for reads +system.physmem.totQLat 7762770500 # Total ticks spent queuing +system.physmem.totMemAccLat 15332051750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2018475000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19229.30 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38114.46 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 37979.30 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.85 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.03 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.86 # Average system read bandwidth in MiByte/s @@ -266,88 +267,88 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.99 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.83 # Average write queue length when enqueuing -system.physmem.readRowHits 364427 # Number of row buffer hits during reads -system.physmem.writeRowHits 95317 # Number of row buffer hits during writes +system.physmem.avgRdQLen 1.79 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.83 # Average write queue length when enqueuing +system.physmem.readRowHits 364450 # Number of row buffer hits during reads +system.physmem.writeRowHits 95361 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.28 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.16 # Row buffer hit rate for writes -system.physmem.avgGap 3577987.41 # Average gap between requests -system.physmem.pageHitRate 88.22 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 216106380 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 114863265 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1442258580 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 305761500 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3620229600.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4158564390 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 232346880 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 8004158310 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 4220231520 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 438996708360 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 461312299845 # Total energy per rank (pJ) -system.physmem_0.averagePower 247.351146 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1855244620250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 361602000 # Time in different power states -system.physmem_0.memoryStateTime::REF 1537874000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1826739481250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 10990187750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7827619250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 17552983750 # Time in different power states -system.physmem_1.actEnergy 222025440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 118005525 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1440038040 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 307191780 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3620229600.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4104344850 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 228211680 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 8096599200 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 4247999520 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 438951182175 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 461336536560 # Total energy per rank (pJ) -system.physmem_1.averagePower 247.364142 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1855407985250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 350582750 # Time in different power states -system.physmem_1.memoryStateTime::REF 1537736000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1826594899250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 11062498750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7708202750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 17755828500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 19556212 # Number of BP lookups -system.cpu.branchPred.condPredicted 16618547 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 593854 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12802975 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5420040 # Number of BTB hits +system.physmem.writeRowHitRate 81.22 # Row buffer hit rate for writes +system.physmem.avgGap 3578215.52 # Average gap between requests +system.physmem.pageHitRate 88.24 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 215406660 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 114491355 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1440673500 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 304618320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3636824880.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4141323030 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 240547200 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 8014976340 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 4268063520 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 438971983965 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 461349368400 # Total energy per rank (pJ) +system.physmem_0.averagePower 247.370445 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1855266278000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 380549250 # Time in different power states +system.physmem_0.memoryStateTime::REF 1544966000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1826613361750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 11114845500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7783583250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 17576798750 # Time in different power states +system.physmem_1.actEnergy 222061140 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 118024500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1441708800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 308136600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3631907760.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4166934840 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 235115520 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 8062896810 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 4253243040 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 438933503490 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 461375149740 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.384267 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1855254817500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 370314000 # Time in different power states +system.physmem_1.memoryStateTime::REF 1542730000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1826502260750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 11076094000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7841044250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 17681661500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 19565204 # Number of BP lookups +system.cpu.branchPred.condPredicted 16626727 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 606351 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12911299 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5422453 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 42.334223 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1126473 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 42524 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6261380 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 563797 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5697583 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 265016 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 41.997734 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1125914 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 42947 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 6343232 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 564019 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5779213 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 264491 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 11131129 # DTB read hits -system.cpu.dtb.read_misses 49734 # DTB read misses -system.cpu.dtb.read_acv 613 # DTB read access violations -system.cpu.dtb.read_accesses 995788 # DTB read accesses -system.cpu.dtb.write_hits 6783534 # DTB write hits -system.cpu.dtb.write_misses 12230 # DTB write misses -system.cpu.dtb.write_acv 435 # DTB write access violations -system.cpu.dtb.write_accesses 345368 # DTB write accesses -system.cpu.dtb.data_hits 17914663 # DTB hits -system.cpu.dtb.data_misses 61964 # DTB misses -system.cpu.dtb.data_acv 1048 # DTB access violations -system.cpu.dtb.data_accesses 1341156 # DTB accesses -system.cpu.itb.fetch_hits 1815343 # ITB hits -system.cpu.itb.fetch_misses 10369 # ITB misses -system.cpu.itb.fetch_acv 759 # ITB acv -system.cpu.itb.fetch_accesses 1825712 # ITB accesses +system.cpu.dtb.read_hits 11109232 # DTB read hits +system.cpu.dtb.read_misses 50748 # DTB read misses +system.cpu.dtb.read_acv 615 # DTB read access violations +system.cpu.dtb.read_accesses 993788 # DTB read accesses +system.cpu.dtb.write_hits 6757496 # DTB write hits +system.cpu.dtb.write_misses 12693 # DTB write misses +system.cpu.dtb.write_acv 420 # DTB write access violations +system.cpu.dtb.write_accesses 345501 # DTB write accesses +system.cpu.dtb.data_hits 17866728 # DTB hits +system.cpu.dtb.data_misses 63441 # DTB misses +system.cpu.dtb.data_acv 1035 # DTB access violations +system.cpu.dtb.data_accesses 1339289 # DTB accesses +system.cpu.itb.fetch_hits 1817930 # ITB hits +system.cpu.itb.fetch_misses 10423 # ITB misses +system.cpu.itb.fetch_acv 754 # ITB acv +system.cpu.itb.fetch_accesses 1828353 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -360,270 +361,269 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numPwrStateTransitions 12878 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 6439 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 279575452.943004 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 438968142.754116 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 6439 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 71000 # Distribution of time spent in the clock gated state +system.cpu.numPwrStateTransitions 12882 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 6441 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 279499621.875485 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 438940062.434372 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 6441 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 80500 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 6439 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 64823406500 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1800186341500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 129653253 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::total 6441 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 64757040000 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1800257064500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 129520522 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30226306 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85761758 # Number of instructions fetch has processed -system.cpu.fetch.Branches 19556212 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7110310 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 91828962 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1682802 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 214 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 31116 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 206972 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 428466 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 497 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9929941 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 408418 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 123563934 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.694068 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.023639 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30117726 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85842784 # Number of instructions fetch has processed +system.cpu.fetch.Branches 19565204 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7112386 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 91831627 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1707334 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 94 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 30324 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 206515 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 432806 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 499 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9953050 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 416768 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 123473258 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.695234 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.025215 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 107716203 87.17% 87.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1033964 0.84% 88.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2108086 1.71% 89.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 968916 0.78% 90.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2910075 2.36% 92.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 665807 0.54% 93.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 808204 0.65% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1035117 0.84% 94.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6317562 5.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 107617936 87.16% 87.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1029887 0.83% 87.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2106014 1.71% 89.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 969195 0.78% 90.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2907839 2.36% 92.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 668408 0.54% 93.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 818971 0.66% 94.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1034002 0.84% 94.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6321006 5.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 123563934 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.150835 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.661470 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24256271 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 86199481 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 10262767 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2038754 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 806660 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 739137 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 35567 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 74091152 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 113387 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 806660 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25262123 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 56608165 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20046193 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11227977 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9612814 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 71075345 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 200089 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2115758 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 264182 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5312560 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 47887128 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 85631010 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 85450068 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168489 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38179018 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9708102 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1730208 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 277739 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13892500 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 11673351 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 7232744 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1724750 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1099672 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 62753291 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2208700 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 60568136 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 94532 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11982878 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5316307 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1547451 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 123563934 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.490176 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.236204 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 123473258 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.151059 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.662774 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24152038 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 86201336 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 10258063 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2042752 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 819068 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 5235547 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 36008 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 74118733 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 112337 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 819068 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25161583 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 56623083 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20020475 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11228852 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9620195 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 71027053 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 203339 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2122213 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 263594 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5326402 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 47839712 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 85552570 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 85371726 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168391 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38166163 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 9673541 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1731851 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 279206 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13863805 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 11669742 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7218714 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1729922 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1107908 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 62661067 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2212545 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 60426230 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 90696 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11910337 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5399466 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1551308 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 123473258 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.489387 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.234720 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 99014105 80.13% 80.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10422330 8.43% 88.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4419921 3.58% 92.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3179961 2.57% 94.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3252538 2.63% 97.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1603803 1.30% 98.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1099991 0.89% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 433312 0.35% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 137973 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 98959132 80.15% 80.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10414953 8.43% 88.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4418122 3.58% 92.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3174360 2.57% 94.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3248671 2.63% 97.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1596633 1.29% 98.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1092968 0.89% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 431056 0.35% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 137363 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 123563934 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 123473258 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 206621 16.55% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 610635 48.92% 65.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 372589 29.85% 95.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 31948 2.56% 97.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 26502 2.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 204093 16.54% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 604376 48.98% 65.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 366984 29.74% 95.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 31970 2.59% 97.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 26536 2.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7279 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 40937281 67.59% 67.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 62136 0.10% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38562 0.06% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 11522525 19.02% 86.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6750152 11.14% 97.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 156092 0.26% 98.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 141347 0.23% 98.43% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949126 1.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 40835249 67.58% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 62139 0.10% 67.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38557 0.06% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 11506324 19.04% 86.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6726484 11.13% 97.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 156184 0.26% 98.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 141292 0.23% 98.43% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949086 1.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 60568136 # Type of FU issued -system.cpu.iq.rate 0.467155 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1248295 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020610 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 245303428 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 76606948 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 58345447 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 739604 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 359470 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 336798 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 61411065 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 398087 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 692317 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 60426230 # Type of FU issued +system.cpu.iq.rate 0.466538 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1233959 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.020421 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 244910582 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 76445733 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 58177679 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 739790 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 359586 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 336759 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 61254735 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 398175 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 690768 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2580830 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3930 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 22198 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 854795 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2579745 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4605 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 21941 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 842112 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17998 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 456632 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18009 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 459546 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 806660 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 52694504 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1340713 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 68945664 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 202125 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 11673351 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 7232744 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1959731 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 45749 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1091638 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 22198 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 229988 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 630611 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 860599 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 59710531 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 11213503 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 857604 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 819068 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 52732826 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1310921 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 68860028 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 210874 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 11669742 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 7218714 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1962223 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 46667 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1061185 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 21941 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 239076 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 633747 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 872823 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 59548676 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 11192398 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 877553 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3983673 # number of nop insts executed -system.cpu.iew.exec_refs 18029484 # number of memory reference insts executed -system.cpu.iew.exec_branches 9387402 # Number of branches executed -system.cpu.iew.exec_stores 6815981 # Number of stores executed -system.cpu.iew.exec_rate 0.460540 # Inst execution rate -system.cpu.iew.wb_sent 58927059 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 58682245 # cumulative count of insts written-back -system.cpu.iew.wb_producers 29779151 # num instructions producing a value -system.cpu.iew.wb_consumers 41279871 # num instructions consuming a value -system.cpu.iew.wb_rate 0.452609 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.721396 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 12584544 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661249 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 770143 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 121389515 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.462724 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.395132 # Number of insts commited each cycle +system.cpu.iew.exec_nop 3986416 # number of nop insts executed +system.cpu.iew.exec_refs 17982691 # number of memory reference insts executed +system.cpu.iew.exec_branches 9367788 # Number of branches executed +system.cpu.iew.exec_stores 6790293 # Number of stores executed +system.cpu.iew.exec_rate 0.459762 # Inst execution rate +system.cpu.iew.wb_sent 58762094 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 58514438 # cumulative count of insts written-back +system.cpu.iew.wb_producers 29700638 # num instructions producing a value +system.cpu.iew.wb_consumers 41179298 # num instructions consuming a value +system.cpu.iew.wb_rate 0.451777 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.721252 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 12514858 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661237 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 782772 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 121281996 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.462997 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.395862 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 101523124 83.63% 83.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7984339 6.58% 90.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4194668 3.46% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2261790 1.86% 95.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1754136 1.45% 96.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 633873 0.52% 97.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 481376 0.40% 97.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 513083 0.42% 98.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2043126 1.68% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 101434078 83.63% 83.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7974018 6.57% 90.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4186796 3.45% 93.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2256770 1.86% 95.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1754187 1.45% 96.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 639315 0.53% 97.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 479528 0.40% 97.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 513600 0.42% 98.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2043704 1.69% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 121389515 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56169799 # Number of instructions committed -system.cpu.commit.committedOps 56169799 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 121281996 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56153243 # Number of instructions committed +system.cpu.commit.committedOps 56153243 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15470470 # Number of memory references committed -system.cpu.commit.loads 9092521 # Number of loads committed -system.cpu.commit.membars 226360 # Number of memory barriers committed -system.cpu.commit.branches 8440690 # Number of branches committed +system.cpu.commit.refs 15466599 # Number of memory references committed +system.cpu.commit.loads 9089997 # Number of loads committed +system.cpu.commit.membars 226363 # Number of memory barriers committed +system.cpu.commit.branches 8438860 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52019202 # Number of committed integer instructions. -system.cpu.commit.function_calls 740566 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3197964 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36217526 64.48% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60675 0.11% 70.28% # Class of committed instruction +system.cpu.commit.int_insts 52003390 # Number of committed integer instructions. +system.cpu.commit.function_calls 740372 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3197246 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36205593 64.48% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60678 0.11% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction @@ -653,39 +653,39 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9174285 16.33% 86.69% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6245839 11.12% 97.81% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9171764 16.33% 86.69% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6244492 11.12% 97.81% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemRead 144596 0.26% 98.06% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemWrite 138067 0.25% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 949126 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 949086 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56169799 # Class of committed instruction -system.cpu.commit.bw_lim_events 2043126 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 187851195 # The number of ROB reads -system.cpu.rob.rob_writes 139687376 # The number of ROB writes -system.cpu.timesIdled 556781 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6089319 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3600366244 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52979108 # Number of Instructions Simulated -system.cpu.committedOps 52979108 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.447252 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.447252 # CPI: Total CPI of All Threads -system.cpu.ipc 0.408622 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.408622 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 77910051 # number of integer regfile reads -system.cpu.int_regfile_writes 42617580 # number of integer regfile writes -system.cpu.fp_regfile_reads 166665 # number of floating regfile reads -system.cpu.fp_regfile_writes 175716 # number of floating regfile writes -system.cpu.misc_regfile_reads 2001313 # number of misc regfile reads -system.cpu.misc_regfile_writes 939513 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1405851 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994060 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 12629128 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1406363 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.979992 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 28232500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994060 # Average occupied blocks per requestor +system.cpu.commit.op_class_0::total 56153243 # Class of committed instruction +system.cpu.commit.bw_lim_events 2043704 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 187656858 # The number of ROB reads +system.cpu.rob.rob_writes 139533948 # The number of ROB writes +system.cpu.timesIdled 550447 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6047264 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3600507688 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52963270 # Number of Instructions Simulated +system.cpu.committedOps 52963270 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.445478 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.445478 # CPI: Total CPI of All Threads +system.cpu.ipc 0.408918 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.408918 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 77682847 # number of integer regfile reads +system.cpu.int_regfile_writes 42491451 # number of integer regfile writes +system.cpu.fp_regfile_reads 166573 # number of floating regfile reads +system.cpu.fp_regfile_writes 175777 # number of floating regfile writes +system.cpu.misc_regfile_reads 2001872 # number of misc regfile reads +system.cpu.misc_regfile_writes 939479 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1405824 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994108 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 12609719 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1406336 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.966363 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 28054500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994108 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999988 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999988 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -693,507 +693,501 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 414 system.cpu.dcache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 67152661 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 67152661 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 8020035 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 8020035 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4180765 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4180765 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 212398 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 212398 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215680 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215680 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 12200800 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 12200800 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 12200800 # number of overall hits -system.cpu.dcache.overall_hits::total 12200800 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1817327 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1817327 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1966706 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1966706 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23570 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23570 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 93 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 93 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3784033 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3784033 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3784033 # number of overall misses -system.cpu.dcache.overall_misses::total 3784033 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 45159601500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 45159601500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 92703832258 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 92703832258 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 420302500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 420302500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 1299500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 1299500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 137863433758 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 137863433758 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 137863433758 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 137863433758 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9837362 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9837362 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6147471 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6147471 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235968 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 235968 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215773 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215773 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15984833 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15984833 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15984833 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15984833 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184737 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.184737 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319921 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.319921 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.099886 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.099886 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000431 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000431 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.236726 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.236726 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.236726 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.236726 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24849.463800 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24849.463800 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47136.599094 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47136.599094 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17832.095885 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17832.095885 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13973.118280 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13973.118280 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36432.936435 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36432.936435 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36432.936435 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36432.936435 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4933871 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2725 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 132268 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 28 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.302076 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 97.321429 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 844182 # number of writebacks -system.cpu.dcache.writebacks::total 844182 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717105 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 717105 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1677249 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1677249 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6763 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 6763 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2394354 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2394354 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2394354 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2394354 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1100222 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1100222 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289457 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 289457 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16807 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 16807 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 93 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 93 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1389679 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1389679 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1389679 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1389679 # number of overall MSHR misses +system.cpu.dcache.tags.tag_accesses 67057386 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 67057386 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 8001397 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 8001397 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4179263 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4179263 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 213150 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 213150 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215702 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215702 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 12180660 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 12180660 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 12180660 # number of overall hits +system.cpu.dcache.overall_hits::total 12180660 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1813374 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1813374 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1966870 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1966870 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22944 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22944 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 62 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 62 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3780244 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3780244 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3780244 # number of overall misses +system.cpu.dcache.overall_misses::total 3780244 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 45111482000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 45111482000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 92228872060 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 92228872060 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 421566000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 421566000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 865000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 865000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 137340354060 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 137340354060 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 137340354060 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 137340354060 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9814771 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9814771 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6146133 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6146133 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 236094 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 236094 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215764 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215764 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15960904 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15960904 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15960904 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15960904 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184760 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.184760 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.320017 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.320017 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.097182 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.097182 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000287 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000287 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.236844 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.236844 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.236844 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.236844 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24877.097609 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24877.097609 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46891.188569 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46891.188569 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18373.692469 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18373.692469 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13951.612903 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13951.612903 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36331.081819 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36331.081819 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36331.081819 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36331.081819 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4936405 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4609 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 132646 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 30 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.214880 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 153.633333 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 843338 # number of writebacks +system.cpu.dcache.writebacks::total 843338 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 712674 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 712674 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1677487 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1677487 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6576 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 6576 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2390161 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2390161 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2390161 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2390161 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1100700 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1100700 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289383 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 289383 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16368 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 16368 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 62 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 62 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1390083 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1390083 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1390083 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1390083 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33013560500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33013560500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14384695133 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14384695133 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 210983000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 210983000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 1206500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 1206500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47398255633 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 47398255633 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47398255633 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 47398255633 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1535352000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1535352000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1535352000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 1535352000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.111841 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.111841 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047086 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047086 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.071226 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.071226 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000431 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000431 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.086937 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.086937 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086937 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.086937 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30006.271916 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30006.271916 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49695.447452 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49695.447452 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12553.281371 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12553.281371 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12973.118280 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12973.118280 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34107.341072 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34107.341072 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34107.341072 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34107.341072 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221551.515152 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221551.515152 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92888.378002 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92888.378002 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1077480 # number of replacements -system.cpu.icache.tags.tagsinuse 509.004193 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 8783075 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1077988 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.147656 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 30284131500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.004193 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994149 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994149 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33019179500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33019179500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14332081529 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14332081529 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205108500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205108500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 803000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 803000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47351261029 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 47351261029 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47351261029 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 47351261029 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1535277500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1535277500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1535277500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 1535277500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.112147 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.112147 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047084 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047084 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.069328 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.069328 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000287 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000287 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087093 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.087093 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087093 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.087093 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29998.346053 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29998.346053 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49526.342353 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49526.342353 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12531.066716 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12531.066716 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12951.612903 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12951.612903 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34063.621402 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34063.621402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34063.621402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34063.621402 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221540.764791 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221540.764791 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92883.870773 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92883.870773 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1070370 # number of replacements +system.cpu.icache.tags.tagsinuse 509.026702 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 8813001 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1070878 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.229697 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 30284278500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.026702 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994193 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994193 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 11008225 # Number of tag accesses -system.cpu.icache.tags.data_accesses 11008225 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 8783075 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8783075 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8783075 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8783075 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8783075 # number of overall hits -system.cpu.icache.overall_hits::total 8783075 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1146854 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1146854 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1146854 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1146854 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1146854 # number of overall misses -system.cpu.icache.overall_misses::total 1146854 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16347552990 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16347552990 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16347552990 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16347552990 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16347552990 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16347552990 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9929929 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9929929 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9929929 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9929929 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9929929 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9929929 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115495 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.115495 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.115495 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.115495 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.115495 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.115495 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14254.258162 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14254.258162 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14254.258162 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14254.258162 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14254.258162 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14254.258162 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8615 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 11024191 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11024191 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 8813002 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8813002 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8813002 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8813002 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8813002 # number of overall hits +system.cpu.icache.overall_hits::total 8813002 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1140039 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1140039 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1140039 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1140039 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1140039 # number of overall misses +system.cpu.icache.overall_misses::total 1140039 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16263731493 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16263731493 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16263731493 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16263731493 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16263731493 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16263731493 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9953041 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9953041 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9953041 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9953041 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9953041 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9953041 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.114542 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.114542 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.114542 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.114542 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.114542 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.114542 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14265.943089 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14265.943089 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14265.943089 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14265.943089 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14265.943089 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14265.943089 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8433 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 335 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 292 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 25.716418 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.880137 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1077480 # number of writebacks -system.cpu.icache.writebacks::total 1077480 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68558 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 68558 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 68558 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 68558 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 68558 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 68558 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1078296 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1078296 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1078296 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1078296 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1078296 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1078296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14436755994 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14436755994 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14436755994 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14436755994 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14436755994 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14436755994 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108591 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108591 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108591 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.108591 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108591 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.108591 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13388.490724 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13388.490724 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13388.490724 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13388.490724 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13388.490724 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13388.490724 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 338614 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65420.361718 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4561143 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 404136 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 11.286159 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6414386000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 255.267028 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5315.608032 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 59849.486658 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.003895 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081110 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.913231 # Average percentage of cache occupancy +system.cpu.icache.writebacks::writebacks 1070370 # number of writebacks +system.cpu.icache.writebacks::total 1070370 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68889 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 68889 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 68889 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 68889 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 68889 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 68889 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1071150 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1071150 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1071150 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1071150 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1071150 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1071150 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14349436996 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14349436996 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14349436996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14349436996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14349436996 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14349436996 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.107620 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.107620 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.107620 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.107620 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.107620 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.107620 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13396.290899 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13396.290899 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13396.290899 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13396.290899 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13396.290899 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13396.290899 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 338611 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65420.352754 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4547118 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 404133 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 11.251538 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 6414124000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 256.173828 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5307.615094 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 59856.563832 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.003909 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.080988 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.913339 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.998235 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 896 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 446 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5595 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 58579 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 439 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5606 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 58575 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40130556 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40130556 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 844182 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 844182 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1076791 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1076791 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 68 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 68 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 93 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 93 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 185239 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 185239 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1062874 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1062874 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 831967 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 831967 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1062874 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1017206 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2080080 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1062874 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1017206 # number of overall hits -system.cpu.l2cache.overall_hits::total 2080080 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 7 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 7 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 114698 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 114698 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15038 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 15038 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 274508 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 274508 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 15038 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 389206 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404244 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 15038 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 389206 # number of overall misses -system.cpu.l2cache.overall_misses::total 404244 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 357500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 357500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12064669000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12064669000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1519815000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1519815000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22385224000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 22385224000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1519815000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 34449893000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35969708000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1519815000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 34449893000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35969708000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 844182 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 844182 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1076791 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1076791 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 75 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 75 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 93 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 93 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 299937 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 299937 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1077912 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1077912 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1106475 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1106475 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1077912 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1406412 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2484324 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1077912 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1406412 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2484324 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.093333 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.093333 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382407 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.382407 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.013951 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.013951 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248092 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248092 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.013951 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.276737 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.162718 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.013951 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.276737 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.162718 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 51071.428571 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 51071.428571 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 105186.393834 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 105186.393834 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 101064.968746 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 101064.968746 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81546.709021 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81546.709021 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 101064.968746 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88513.262899 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 88980.190182 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 101064.968746 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88513.262899 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 88980.190182 # average overall miss latency +system.cpu.l2cache.tags.tag_accesses 40018321 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40018321 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 843338 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 843338 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1069837 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1069837 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 60 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 60 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 62 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 62 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 185066 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 185066 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1055887 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1055887 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 832119 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 832119 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1055887 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1017185 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2073072 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1055887 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1017185 # number of overall hits +system.cpu.l2cache.overall_hits::total 2073072 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 10 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 10 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 114704 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 114704 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15037 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 15037 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 274496 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 274496 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 15037 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 389200 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 404237 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 15037 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 389200 # number of overall misses +system.cpu.l2cache.overall_misses::total 404237 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 448000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 448000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12012512000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12012512000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1519237500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1519237500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22383517000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 22383517000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1519237500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 34396029000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 35915266500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1519237500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 34396029000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 35915266500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 843338 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 843338 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1069837 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1069837 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 70 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 70 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 62 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 62 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 299770 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 299770 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1070924 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1070924 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1106615 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1106615 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1070924 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1406385 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2477309 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1070924 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1406385 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2477309 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.142857 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.142857 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382640 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.382640 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014041 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014041 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248050 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248050 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014041 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.276738 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.163176 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014041 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.276738 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.163176 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 44800 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 44800 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104726.182173 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104726.182173 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 101033.284565 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 101033.284565 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81544.055287 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81544.055287 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 101033.284565 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88376.230730 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 88847.053832 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 101033.284565 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88376.230730 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 88847.053832 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 75929 # number of writebacks -system.cpu.l2cache.writebacks::total 75929 # number of writebacks -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 7 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 7 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 114698 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 114698 # number of ReadExReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 75899 # number of writebacks +system.cpu.l2cache.writebacks::total 75899 # number of writebacks +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 114704 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 114704 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15037 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15037 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 274508 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 274508 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 274496 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 274496 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 15037 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389206 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404243 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389200 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404237 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 15037 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389206 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404243 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389200 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404237 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 287500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 287500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10917688501 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10917688501 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1369353500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1369353500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19646288000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19646288000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1369353500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 30563976501 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 31933330001 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1369353500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 30563976501 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 31933330001 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1448711500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1448711500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1448711500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1448711500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.093333 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.093333 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382407 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382407 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013950 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013950 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248092 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248092 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013950 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276737 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.162718 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013950 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276737 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.162718 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 41071.428571 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 41071.428571 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95186.389484 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95186.389484 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 91065.604841 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 91065.604841 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71569.090883 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71569.090883 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 91065.604841 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78529.047602 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78995.381493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 91065.604841 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78529.047602 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78995.381493 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209049.278499 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209049.278499 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87646.651340 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87646.651340 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4968207 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2483449 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 5093 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 951 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 951 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 348000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 348000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10865472000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10865472000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1368867500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1368867500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19644703500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19644703500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1368867500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 30510175500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 31879043000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1368867500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 30510175500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31879043000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1448637000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1448637000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1448637000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1448637000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.142857 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.142857 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382640 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382640 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014041 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014041 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248050 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248050 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014041 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276738 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.163176 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014041 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276738 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.163176 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 34800 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 34800 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94726.182173 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94726.182173 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 91033.284565 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 91033.284565 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71566.447234 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71566.447234 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 91033.284565 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78392.023381 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78862.259021 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 91033.284565 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78392.023381 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78862.259021 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209038.528139 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209038.528139 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87642.144110 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87642.144110 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4953861 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2476312 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4344 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 953 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 953 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2191810 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2184804 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9599 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9599 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 920111 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1077480 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 824354 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 75 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 93 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 168 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 299937 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 299937 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1078296 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106636 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 919237 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1070370 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 825198 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 70 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 62 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 132 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 299770 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 299770 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1071150 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106776 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 47 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateResp 2 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3233688 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4252227 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7485915 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137945088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144089148 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 282034236 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 339553 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4894016 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2840416 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002130 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.046099 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3212444 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4252074 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7464518 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137042816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144033404 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 281076220 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 339392 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4881984 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2833204 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001872 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.043223 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2834367 99.79% 99.79% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 6049 0.21% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2827901 99.81% 99.81% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5303 0.19% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2840416 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4418829500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2833204 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4403702500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 292883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1618554275 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1607637172 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2121571625 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2121526099 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1207,7 +1201,7 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51151 # Transaction distribution @@ -1238,46 +1232,46 @@ system.iobus.pkt_size_system.bridge.master::total 44156 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2705764 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5364500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 5360000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 813500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 815500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 178500 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 180500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14114000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14072500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2179500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2178500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6040500 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6063000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 88500 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 93500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216207792 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216225034 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23459000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.265392 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.265440 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1714257470000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.265392 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.079087 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.079087 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1714255689000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.265440 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.079090 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.079090 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1286,14 +1280,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21940383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21940383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4930799409 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4930799409 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4952739792 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4952739792 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4952739792 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4952739792 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21944883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21944883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4931807151 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4931807151 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4953752034 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4953752034 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4953752034 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4953752034 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1310,19 +1304,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126823.023121 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126823.023121 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118665.753971 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118665.753971 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 118699.575602 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118699.575602 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 118699.575602 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118699.575602 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 1416 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126849.034682 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126849.034682 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118690.006522 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118690.006522 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 118723.835446 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118723.835446 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 118723.835446 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118723.835446 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 1219 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 13 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 12 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 108.923077 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 101.583333 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks @@ -1334,14 +1328,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13290383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13290383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2850780302 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2850780302 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2864070685 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2864070685 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2864070685 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2864070685 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13294883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13294883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2851781783 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2851781783 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2865076666 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2865076666 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2865076666 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2865076666 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1350,76 +1344,76 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76823.023121 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76823.023121 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68607.535185 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68607.535185 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68641.598203 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68641.598203 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68641.598203 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68641.598203 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 825546 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 380389 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 528 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76849.034682 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76849.034682 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68631.637057 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68631.637057 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68665.707993 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68665.707993 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68665.707993 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68665.707993 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 825536 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 380380 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 527 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 296601 # Transaction distribution +system.membus.trans_dist::ReadResp 296589 # Transaction distribution system.membus.trans_dist::WriteReq 9599 # Transaction distribution system.membus.trans_dist::WriteResp 9599 # Transaction distribution -system.membus.trans_dist::WritebackDirty 117441 # Transaction distribution -system.membus.trans_dist::CleanEvict 262065 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117411 # Transaction distribution +system.membus.trans_dist::CleanEvict 262092 # Transaction distribution system.membus.trans_dist::UpgradeReq 137 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 114568 # Transaction distribution -system.membus.trans_dist::ReadExResp 114568 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289718 # Transaction distribution +system.membus.trans_dist::ReadExReq 114577 # Transaction distribution +system.membus.trans_dist::ReadExResp 114577 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289706 # Transaction distribution system.membus.trans_dist::BadAddressError 47 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 124 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33058 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145812 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145804 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 94 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1178964 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1178956 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1262389 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1262381 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44156 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30701888 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30746044 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30699840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30743996 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33403772 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 563 # Total snoops (count) -system.membus.snoopTraffic 27904 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 462504 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001466 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.038259 # Request fanout histogram +system.membus.pkt_size::total 33401724 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 562 # Total snoops (count) +system.membus.snoopTraffic 27840 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 462501 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001464 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.038231 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 461826 99.85% 99.85% # Request fanout histogram -system.membus.snoop_fanout::1 678 0.15% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 461824 99.85% 99.85% # Request fanout histogram +system.membus.snoop_fanout::1 677 0.15% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 462504 # Request fanout histogram -system.membus.reqLayer0.occupancy 28800500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 462501 # Request fanout histogram +system.membus.reqLayer0.occupancy 28785000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1313542061 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1313532070 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 57500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 60000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2137882250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2137876500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1056521 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1057021 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1451,52 +1445,52 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211030 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74670 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211020 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74665 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1881 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105578 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182260 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73303 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105573 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182250 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73298 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1881 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73303 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1819124828000 97.54% 97.54% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 67368000 0.00% 97.54% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 565513500 0.03% 97.57% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 45251211500 2.43% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1865008921000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73298 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148608 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1819143935000 97.54% 97.54% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 67422000 0.00% 97.54% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 565966500 0.03% 97.57% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 45235960500 2.43% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1865013284000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694302 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815418 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694287 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815407 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed @@ -1504,7 +1498,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175141 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175131 91.22% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -1513,7 +1507,7 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5106 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191988 # number of callpals executed +system.cpu.kern.callpal::total 191978 # number of callpals executed system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches system.cpu.kern.mode_switch::user 1738 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches @@ -1524,9 +1518,9 @@ system.cpu.kern.mode_switch_good::kernel 0.326098 # fr system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.393971 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29666586000 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2759246500 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1832583080500 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 29665976500 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2757716000 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1832589583500 98.26% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 37e31e615..b789abbb5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,163 +1,163 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.848913 # Number of seconds simulated -sim_ticks 2848912955000 # Number of ticks simulated -final_tick 2848912955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.848599 # Number of seconds simulated +sim_ticks 2848598682500 # Number of ticks simulated +final_tick 2848598682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 258856 # Simulator instruction rate (inst/s) -host_op_rate 313468 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5762698171 # Simulator tick rate (ticks/s) -host_mem_usage 627144 # Number of bytes of host memory used -host_seconds 494.37 # Real time elapsed on the host -sim_insts 127970828 # Number of instructions simulated -sim_ops 154969713 # Number of ops (including micro ops) simulated +host_inst_rate 262669 # Simulator instruction rate (inst/s) +host_op_rate 318064 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5881753499 # Simulator tick rate (ticks/s) +host_mem_usage 626168 # Number of bytes of host memory used +host_seconds 484.31 # Real time elapsed on the host +sim_insts 127213455 # Number of instructions simulated +sim_ops 154041729 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 9408 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 9280 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1675840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1349948 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8501504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 229824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 661012 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 405952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1663936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1359352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8597824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 234560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 659412 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 325376 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12835728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1675840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 229824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1905664 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9061888 # Number of bytes written to this memory +system.physmem.bytes_read::total 12852044 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1663936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 234560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1898496 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8978368 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 9079452 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 147 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8995932 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 145 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26185 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21618 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 132836 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3591 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10349 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6343 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25999 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21764 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 134341 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 20 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3665 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10324 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5084 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 201104 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 141592 # Number of write requests responded to by this memory +system.physmem.num_reads::total 201358 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 140287 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 145983 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3302 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 144678 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3258 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 588238 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 473847 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2984122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 427 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 80671 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 232023 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 142494 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 584124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 477200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3018264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 449 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 82342 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 231486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 114223 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4505483 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 588238 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 80671 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 668909 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3180823 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6151 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4511707 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 584124 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 82342 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 666467 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3151854 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6152 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3186988 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3180823 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3302 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3158020 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3151854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3258 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 588238 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 479998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2984122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 427 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 80671 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 232037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 142494 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 584124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 483352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3018264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 82342 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 231500 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 114223 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7692471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 201104 # Number of read requests accepted -system.physmem.writeReqs 145983 # Number of write requests accepted -system.physmem.readBursts 201104 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 145983 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12861056 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue -system.physmem.bytesWritten 9091968 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12835728 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9079452 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::total 7669728 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 201358 # Number of read requests accepted +system.physmem.writeReqs 144678 # Number of write requests accepted +system.physmem.readBursts 201358 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 144678 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12877760 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9152 # Total number of bytes read from write queue +system.physmem.bytesWritten 9008896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12852044 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8995932 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 143 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12429 # Per bank write bursts -system.physmem.perBankRdBursts::1 12794 # Per bank write bursts -system.physmem.perBankRdBursts::2 13696 # Per bank write bursts -system.physmem.perBankRdBursts::3 13190 # Per bank write bursts -system.physmem.perBankRdBursts::4 15337 # Per bank write bursts -system.physmem.perBankRdBursts::5 12894 # Per bank write bursts -system.physmem.perBankRdBursts::6 12741 # Per bank write bursts -system.physmem.perBankRdBursts::7 13088 # Per bank write bursts -system.physmem.perBankRdBursts::8 12333 # Per bank write bursts -system.physmem.perBankRdBursts::9 12486 # Per bank write bursts -system.physmem.perBankRdBursts::10 11357 # Per bank write bursts -system.physmem.perBankRdBursts::11 10671 # Per bank write bursts -system.physmem.perBankRdBursts::12 11888 # Per bank write bursts -system.physmem.perBankRdBursts::13 12773 # Per bank write bursts -system.physmem.perBankRdBursts::14 11762 # Per bank write bursts -system.physmem.perBankRdBursts::15 11515 # Per bank write bursts -system.physmem.perBankWrBursts::0 8987 # Per bank write bursts -system.physmem.perBankWrBursts::1 9459 # Per bank write bursts -system.physmem.perBankWrBursts::2 10102 # Per bank write bursts -system.physmem.perBankWrBursts::3 9553 # Per bank write bursts -system.physmem.perBankWrBursts::4 8641 # Per bank write bursts -system.physmem.perBankWrBursts::5 9022 # Per bank write bursts -system.physmem.perBankWrBursts::6 9160 # Per bank write bursts -system.physmem.perBankWrBursts::7 9289 # Per bank write bursts -system.physmem.perBankWrBursts::8 8726 # Per bank write bursts -system.physmem.perBankWrBursts::9 8906 # Per bank write bursts -system.physmem.perBankWrBursts::10 8219 # Per bank write bursts -system.physmem.perBankWrBursts::11 7897 # Per bank write bursts -system.physmem.perBankWrBursts::12 8731 # Per bank write bursts -system.physmem.perBankWrBursts::13 8920 # Per bank write bursts -system.physmem.perBankWrBursts::14 8491 # Per bank write bursts -system.physmem.perBankWrBursts::15 7959 # Per bank write bursts +system.physmem.perBankRdBursts::0 12337 # Per bank write bursts +system.physmem.perBankRdBursts::1 12726 # Per bank write bursts +system.physmem.perBankRdBursts::2 13547 # Per bank write bursts +system.physmem.perBankRdBursts::3 13037 # Per bank write bursts +system.physmem.perBankRdBursts::4 15119 # Per bank write bursts +system.physmem.perBankRdBursts::5 12845 # Per bank write bursts +system.physmem.perBankRdBursts::6 12657 # Per bank write bursts +system.physmem.perBankRdBursts::7 13022 # Per bank write bursts +system.physmem.perBankRdBursts::8 12280 # Per bank write bursts +system.physmem.perBankRdBursts::9 12341 # Per bank write bursts +system.physmem.perBankRdBursts::10 11583 # Per bank write bursts +system.physmem.perBankRdBursts::11 10739 # Per bank write bursts +system.physmem.perBankRdBursts::12 12026 # Per bank write bursts +system.physmem.perBankRdBursts::13 12946 # Per bank write bursts +system.physmem.perBankRdBursts::14 12179 # Per bank write bursts +system.physmem.perBankRdBursts::15 11831 # Per bank write bursts +system.physmem.perBankWrBursts::0 8873 # Per bank write bursts +system.physmem.perBankWrBursts::1 9291 # Per bank write bursts +system.physmem.perBankWrBursts::2 9856 # Per bank write bursts +system.physmem.perBankWrBursts::3 9274 # Per bank write bursts +system.physmem.perBankWrBursts::4 8405 # Per bank write bursts +system.physmem.perBankWrBursts::5 8988 # Per bank write bursts +system.physmem.perBankWrBursts::6 8961 # Per bank write bursts +system.physmem.perBankWrBursts::7 9107 # Per bank write bursts +system.physmem.perBankWrBursts::8 8695 # Per bank write bursts +system.physmem.perBankWrBursts::9 8769 # Per bank write bursts +system.physmem.perBankWrBursts::10 8272 # Per bank write bursts +system.physmem.perBankWrBursts::11 7845 # Per bank write bursts +system.physmem.perBankWrBursts::12 8751 # Per bank write bursts +system.physmem.perBankWrBursts::13 8985 # Per bank write bursts +system.physmem.perBankWrBursts::14 8630 # Per bank write bursts +system.physmem.perBankWrBursts::15 8062 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 98 # Number of times write queue was full causing retry -system.physmem.totGap 2848912399000 # Total gap between requests +system.physmem.numWrRetry 74 # Number of times write queue was full causing retry +system.physmem.totGap 2848598144000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 556 # Read request sizes (log2) +system.physmem.readPktSize::2 555 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 200520 # Read request sizes (log2) +system.physmem.readPktSize::6 200775 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 141592 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 84624 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 63240 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11856 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9787 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6722 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5707 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4943 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4044 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1053 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 240 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 140287 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 85113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 63389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9690 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6744 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5598 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4878 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4009 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 239 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -185,178 +185,178 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 10035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 296 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 89688 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 244.770315 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 140.172635 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 301.083170 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 45750 51.01% 51.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18787 20.95% 71.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6651 7.42% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3758 4.19% 83.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2958 3.30% 86.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1568 1.75% 88.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1004 1.12% 89.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1009 1.13% 90.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8203 9.15% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 89688 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7073 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.410010 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 554.388606 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7071 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8923 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 216 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 88566 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 247.121830 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 141.476955 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 302.598654 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 44693 50.46% 50.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18724 21.14% 71.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6637 7.49% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3795 4.28% 83.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2919 3.30% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1572 1.77% 88.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 960 1.08% 89.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1024 1.16% 90.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8242 9.31% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 88566 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6985 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.806586 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 558.021687 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6983 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7073 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7073 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.085112 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.515707 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.383837 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5944 84.04% 84.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 432 6.11% 90.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 82 1.16% 91.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 52 0.74% 92.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 255 3.61% 95.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 25 0.35% 96.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 15 0.21% 96.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.10% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 13 0.18% 96.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 9 0.13% 96.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.06% 96.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 7 0.10% 96.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 148 2.09% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 11 0.16% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.08% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.04% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 9 0.13% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.04% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 4 0.06% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 6 0.08% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.04% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.01% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 6 0.08% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.04% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 4 0.06% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.01% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.04% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 4 0.06% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 4 0.06% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7073 # Writes before turning the bus around for reads -system.physmem.totQLat 9366475580 # Total ticks spent queuing -system.physmem.totMemAccLat 13134363080 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1004770000 # Total ticks spent in databus transfers -system.physmem.avgQLat 46610.05 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6985 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6985 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.152326 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.495944 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.110349 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5869 84.02% 84.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 441 6.31% 90.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 79 1.13% 91.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 44 0.63% 92.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 241 3.45% 95.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 25 0.36% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 15 0.21% 96.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 10 0.14% 96.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 17 0.24% 96.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.11% 96.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.04% 96.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.10% 96.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 146 2.09% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.06% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 6 0.09% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 7 0.10% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.04% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.04% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 11 0.16% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.03% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 10 0.14% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.03% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.04% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 3 0.04% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.04% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.04% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 3 0.04% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-243 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6985 # Writes before turning the bus around for reads +system.physmem.totQLat 9483410947 # Total ticks spent queuing +system.physmem.totMemAccLat 13256192197 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1006075000 # Total ticks spent in databus transfers +system.physmem.avgQLat 47130.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 65360.05 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.51 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.19 # Average achieved write bandwidth in MiByte/s +system.physmem.avgMemAccLat 65880.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.52 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.16 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.51 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.19 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.16 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.20 # Average write queue length when enqueuing -system.physmem.readRowHits 166422 # Number of row buffer hits during reads -system.physmem.writeRowHits 86905 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 61.16 # Row buffer hit rate for writes -system.physmem.avgGap 8208064.26 # Average gap between requests -system.physmem.pageHitRate 73.85 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 341813220 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 181678035 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 758046660 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 387391860 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5805889440.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5444775090 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 308095680 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 11642068740 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 8562690720 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 670190772435 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 703626055650 # Total energy per rank (pJ) -system.physmem_0.averagePower 246.980538 # Core power per rank (mW) -system.physmem_0.totalIdleTime 2836051939093 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 546109733 # Time in different power states -system.physmem_0.memoryStateTime::REF 2466940000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 2788334468750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 22298648785 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9735828674 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 25530959058 # Time in different power states -system.physmem_1.actEnergy 298566240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 158687925 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 676764900 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 354171780 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5707547040.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5348415450 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 325299360 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 10595992200 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 8817735360 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 670663868775 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 702949735620 # Total energy per rank (pJ) -system.physmem_1.averagePower 246.743143 # Core power per rank (mW) -system.physmem_1.totalIdleTime 2836330915238 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 596946927 # Time in different power states -system.physmem_1.memoryStateTime::REF 2425844000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 2790131179750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 22962884806 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9559167335 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 23236932182 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.98 # Average write queue length when enqueuing +system.physmem.readRowHits 166670 # Number of row buffer hits during reads +system.physmem.writeRowHits 86742 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 61.61 # Row buffer hit rate for writes +system.physmem.avgGap 8232086.10 # Average gap between requests +system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 334044900 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 177549075 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 751770600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 379781100 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 5711234880.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5249821980 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 307614240 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 11585671230 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8434613280 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 670304268120 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 703238620035 # Total energy per rank (pJ) +system.physmem_0.averagePower 246.871777 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2836104738853 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 545953693 # Time in different power states +system.physmem_0.memoryStateTime::REF 2426690000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2788907518000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 21965166332 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9346009704 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 25407344771 # Time in different power states +system.physmem_1.actEnergy 298323480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 158558895 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 684904500 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 355006980 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 5713078800.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5198973990 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 317598720 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 10947475860 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 8696180160 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 670560217290 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 702932935245 # Total energy per rank (pJ) +system.physmem_1.averagePower 246.764467 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2836364452001 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 573854684 # Time in different power states +system.physmem_1.memoryStateTime::REF 2428124000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2789710596750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 22646269258 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9232187315 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 24007650493 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory @@ -375,30 +375,30 @@ system.realview.nvmem.bw_inst_read::total 472 # I system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 20830846 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13649526 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1014386 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 13197369 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 8753451 # Number of BTB hits +system.cpu0.branchPred.lookups 21387746 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14055793 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1067110 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 13655999 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 8982856 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 66.327243 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3414506 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 211257 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 762629 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 580306 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 182323 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 100148 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 65.779560 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3510572 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 218030 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 788067 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 592988 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 195079 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 105213 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -428,61 +428,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 66699 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 66699 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 45954 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 20745 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 66699 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 66699 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 66699 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6786 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12503.831418 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11414.396725 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6634.903581 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6272 92.43% 92.43% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 416 6.13% 98.56% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 85 1.25% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 5 0.07% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 5 0.07% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::114688-131071 2 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6786 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 69629 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 69629 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46094 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 23535 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 69629 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 69629 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 69629 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 7649 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12135.050333 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 10988.955041 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 11832.363963 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 7639 99.87% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 6 0.08% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 2 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 7649 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 338892000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 338892000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 338892000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5256 77.45% 77.45% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1530 22.55% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6786 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 66699 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5959 77.91% 77.91% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1690 22.09% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 7649 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 69629 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 66699 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6786 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 69629 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7649 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6786 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 73485 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7649 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 77278 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 17337178 # DTB read hits -system.cpu0.dtb.read_misses 60105 # DTB read misses -system.cpu0.dtb.write_hits 14536732 # DTB write hits -system.cpu0.dtb.write_misses 6594 # DTB write misses +system.cpu0.dtb.read_hits 17966885 # DTB read hits +system.cpu0.dtb.read_misses 63028 # DTB read misses +system.cpu0.dtb.write_hits 15039551 # DTB write hits +system.cpu0.dtb.write_misses 6601 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3451 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1375 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1930 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3754 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1491 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2059 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 524 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 17397283 # DTB read accesses -system.cpu0.dtb.write_accesses 14543326 # DTB write accesses +system.cpu0.dtb.perms_faults 586 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 18029913 # DTB read accesses +system.cpu0.dtb.write_accesses 15046152 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31873910 # DTB hits -system.cpu0.dtb.misses 66699 # DTB misses -system.cpu0.dtb.accesses 31940609 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 33006436 # DTB hits +system.cpu0.dtb.misses 69629 # DTB misses +system.cpu0.dtb.accesses 33076065 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -512,40 +509,40 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 4013 # Table walker walks requested -system.cpu0.itb.walker.walksShort 4013 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 305 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3708 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 4013 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 4013 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 4013 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2436 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12745.689655 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11895.862443 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5321.422543 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 433 17.78% 17.78% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1791 73.52% 91.30% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 138 5.67% 96.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 37 1.52% 98.48% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 36 1.48% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 4318 # Table walker walks requested +system.cpu0.itb.walker.walksShort 4318 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 325 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3993 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 4318 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 4318 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 4318 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2683 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12304.137160 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11560.884208 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 4695.711947 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 502 18.71% 18.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1984 73.95% 92.66% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 147 5.48% 98.14% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 31 1.16% 99.29% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 18 0.67% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2436 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2683 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 338263500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 338263500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 338263500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2136 87.68% 87.68% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 300 12.32% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2436 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2363 88.07% 88.07% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 320 11.93% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2683 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4013 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4013 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4318 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4318 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2436 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2436 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6449 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 38740955 # ITB inst hits -system.cpu0.itb.inst_misses 4013 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2683 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2683 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 7001 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 39752533 # ITB inst hits +system.cpu0.itb.inst_misses 4318 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -554,798 +551,796 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2172 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2396 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7050 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7865 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 38744968 # ITB inst accesses -system.cpu0.itb.hits 38740955 # DTB hits -system.cpu0.itb.misses 4013 # DTB misses -system.cpu0.itb.accesses 38744968 # DTB accesses -system.cpu0.numPwrStateTransitions 3702 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1851 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1492467740.212318 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23926618307.518574 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1069 57.75% 57.75% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 775 41.87% 99.62% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 2 0.11% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 39756851 # ITB inst accesses +system.cpu0.itb.hits 39752533 # DTB hits +system.cpu0.itb.misses 4318 # DTB misses +system.cpu0.itb.accesses 39756851 # DTB accesses +system.cpu0.numPwrStateTransitions 3708 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1854 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1488611861.955232 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23946276211.601498 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1085 58.52% 58.52% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 762 41.10% 99.62% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.68% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.05% 99.73% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499963002708 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1851 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 86355167867 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2762557787133 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 172712897 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 499963838164 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1854 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 88712290435 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2759886392065 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 177427128 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 79713377 # Number of instructions committed -system.cpu0.committedOps 95922535 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 5281292 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1851 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5525141996 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.166674 # CPI: cycles per instruction -system.cpu0.ipc 0.461537 # IPC: instructions per cycle -system.cpu0.op_class_0::No_OpClass 2273 0.00% 0.00% # Class of committed instruction -system.cpu0.op_class_0::IntAlu 63731011 66.44% 66.44% # Class of committed instruction -system.cpu0.op_class_0::IntMult 92142 0.10% 66.54% # Class of committed instruction -system.cpu0.op_class_0::IntDiv 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::FloatAdd 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::FloatCmp 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::FloatCvt 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::FloatMult 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::FloatMultAcc 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::FloatDiv 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::FloatMisc 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::FloatSqrt 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdAdd 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdAddAcc 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdAlu 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdCmp 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdCvt 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdMisc 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdMult 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdMultAcc 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdShift 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdSqrt 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMisc 8073 0.01% 66.55% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.55% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.55% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.55% # Class of committed instruction -system.cpu0.op_class_0::MemRead 16805807 17.52% 84.07% # Class of committed instruction -system.cpu0.op_class_0::MemWrite 15273589 15.92% 99.99% # Class of committed instruction -system.cpu0.op_class_0::FloatMemRead 2256 0.00% 99.99% # Class of committed instruction -system.cpu0.op_class_0::FloatMemWrite 7384 0.01% 100.00% # Class of committed instruction +system.cpu0.committedInsts 82154396 # Number of instructions committed +system.cpu0.committedOps 98918766 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 5358225 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1854 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5519798084 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.159679 # CPI: cycles per instruction +system.cpu0.ipc 0.463032 # IPC: instructions per cycle +system.cpu0.op_class_0::No_OpClass 2315 0.00% 0.00% # Class of committed instruction +system.cpu0.op_class_0::IntAlu 65610842 66.33% 66.33% # Class of committed instruction +system.cpu0.op_class_0::IntMult 94061 0.10% 66.43% # Class of committed instruction +system.cpu0.op_class_0::IntDiv 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::FloatAdd 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::FloatCmp 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::FloatCvt 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::FloatMult 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::FloatMultAcc 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::FloatDiv 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::FloatMisc 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::FloatSqrt 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdAdd 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdAddAcc 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdAlu 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdCmp 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdCvt 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdMisc 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdMult 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdMultAcc 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdShift 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdSqrt 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMisc 8175 0.01% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::MemRead 17407324 17.60% 84.03% # Class of committed instruction +system.cpu0.op_class_0::MemWrite 15784753 15.96% 99.99% # Class of committed instruction +system.cpu0.op_class_0::FloatMemRead 2708 0.00% 99.99% # Class of committed instruction +system.cpu0.op_class_0::FloatMemWrite 8588 0.01% 100.00% # Class of committed instruction system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.op_class_0::total 95922535 # Class of committed instruction +system.cpu0.op_class_0::total 98918766 # Class of committed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1851 # number of quiesce instructions executed -system.cpu0.tickCycles 120871852 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 51841045 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 716918 # number of replacements -system.cpu0.dcache.tags.tagsinuse 495.671066 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 30432435 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 717430 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 42.418682 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 1854 # number of quiesce instructions executed +system.cpu0.tickCycles 124478065 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 52949063 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 756000 # number of replacements +system.cpu0.dcache.tags.tagsinuse 495.989536 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 31503611 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 756512 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 41.643240 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 356904000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 495.671066 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.968108 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.968108 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 495.989536 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.968730 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.968730 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63807329 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63807329 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 15850504 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 15850504 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 13422208 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 13422208 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320804 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 320804 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365505 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 365505 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361161 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361161 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 29272712 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 29272712 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 29593516 # number of overall hits -system.cpu0.dcache.overall_hits::total 29593516 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 439135 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 439135 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 581157 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 581157 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 135756 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 135756 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20923 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20923 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20396 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20396 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1020292 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1020292 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1156048 # number of overall misses -system.cpu0.dcache.overall_misses::total 1156048 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6443435000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6443435000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 11283390500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 11283390500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 333090000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 333090000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 482408000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 482408000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 637500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 637500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 17726825500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 17726825500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 17726825500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 17726825500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 16289639 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 16289639 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 14003365 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 14003365 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456560 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 456560 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386428 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386428 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381557 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381557 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 30293004 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 30293004 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 30749564 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 30749564 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.026958 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.026958 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041501 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.041501 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.297345 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.297345 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054145 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054145 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053455 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053455 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033681 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.033681 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037596 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.037596 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14673.016271 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14673.016271 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19415.391194 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19415.391194 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15919.801176 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15919.801176 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23652.088645 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23652.088645 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 66089687 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 66089687 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 16428136 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 16428136 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 13890443 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 13890443 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 328324 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 328324 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374119 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 374119 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 370195 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 370195 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 30318579 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 30318579 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 30646903 # number of overall hits +system.cpu0.dcache.overall_hits::total 30646903 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 460755 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 460755 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 603639 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 603639 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141924 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 141924 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21489 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21489 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20512 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20512 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1064394 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1064394 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1206318 # number of overall misses +system.cpu0.dcache.overall_misses::total 1206318 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6676359500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6676359500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 11544866500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 11544866500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336675500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 336675500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 485473000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 485473000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 539500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 539500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 18221226000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 18221226000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 18221226000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 18221226000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16888891 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16888891 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 14494082 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 14494082 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 470248 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 470248 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 395608 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 395608 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 390707 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 390707 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 31382973 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 31382973 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 31853221 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 31853221 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027282 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.027282 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041647 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.041647 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.301807 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.301807 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054319 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054319 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052500 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052500 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033916 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.033916 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037871 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.037871 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14490.042430 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14490.042430 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19125.448323 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 19125.448323 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15667.341430 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15667.341430 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23667.755460 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23667.755460 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17374.266877 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 17374.266877 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15333.987430 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15333.987430 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17118.873274 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 17118.873274 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15104.828080 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15104.828080 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 716918 # number of writebacks -system.cpu0.dcache.writebacks::total 716918 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 44597 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 44597 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 255598 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 255598 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14548 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14548 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 300195 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 300195 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 300195 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 300195 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 394538 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 394538 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325559 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 325559 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102257 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 102257 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6375 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6375 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20396 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20396 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 720097 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 720097 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 822354 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 822354 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20581 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20581 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19270 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19270 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39851 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39851 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5273598500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5273598500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6168960000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6168960000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1704833000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1704833000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 102845500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102845500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 462030000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 462030000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 619500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 619500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11442558500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11442558500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13147391500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13147391500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4607502500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4607502500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4607502500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4607502500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024220 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024220 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023249 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023249 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.223973 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223973 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016497 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016497 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053455 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053455 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023771 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023771 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026744 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026744 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13366.516026 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13366.516026 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18948.823408 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18948.823408 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16672.042012 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16672.042012 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16132.627451 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16132.627451 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22652.971171 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22652.971171 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 756000 # number of writebacks +system.cpu0.dcache.writebacks::total 756000 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 45822 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 45822 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 266133 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 266133 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14947 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14947 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 311955 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 311955 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 311955 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 311955 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 414933 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 414933 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 337506 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 337506 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 108299 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 108299 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6542 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6542 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20512 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20512 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 752439 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 752439 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 860738 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 860738 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20603 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20603 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19302 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19302 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39905 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39905 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5470255000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5470255000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6299771000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6299771000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1751643500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1751643500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104376500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104376500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 464977000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 464977000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 523500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 523500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11770026000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11770026000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13521669500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13521669500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4611679000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4611679000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4611679000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4611679000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024568 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024568 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023286 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023286 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.230302 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.230302 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016537 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016537 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052500 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052500 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023976 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023976 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027022 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027022 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13183.465764 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13183.465764 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18665.656314 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18665.656314 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16174.142882 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16174.142882 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15954.830327 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15954.830327 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22668.535491 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22668.535491 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15890.301584 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15890.301584 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15987.508421 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15987.508421 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223871.653467 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223871.653467 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115618.240446 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115618.240446 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1966568 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.773009 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 36766553 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1967080 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 18.690929 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6697446000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.773009 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999557 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999557 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15642.498595 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15642.498595 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15709.390662 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15709.390662 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223835.315245 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223835.315245 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115566.445308 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115566.445308 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 2036864 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.774783 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 37707013 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 2037376 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 18.507636 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6575306000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774783 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999560 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999560 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 79434387 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 79434387 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 36766553 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 36766553 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 36766553 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 36766553 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 36766553 # number of overall hits -system.cpu0.icache.overall_hits::total 36766553 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1967094 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1967094 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1967094 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1967094 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1967094 # number of overall misses -system.cpu0.icache.overall_misses::total 1967094 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 19796906000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 19796906000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 19796906000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 19796906000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 19796906000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 19796906000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 38733647 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 38733647 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 38733647 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 38733647 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 38733647 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 38733647 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050785 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.050785 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050785 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.050785 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050785 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.050785 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10064.036594 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10064.036594 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10064.036594 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10064.036594 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10064.036594 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10064.036594 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 81526207 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 81526207 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 37707013 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 37707013 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 37707013 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 37707013 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 37707013 # number of overall hits +system.cpu0.icache.overall_hits::total 37707013 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 2037394 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 2037394 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 2037394 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 2037394 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 2037394 # number of overall misses +system.cpu0.icache.overall_misses::total 2037394 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20429568000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 20429568000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 20429568000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 20429568000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 20429568000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 20429568000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 39744407 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 39744407 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 39744407 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 39744407 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 39744407 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 39744407 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051262 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.051262 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051262 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.051262 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051262 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.051262 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10027.303506 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10027.303506 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10027.303506 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10027.303506 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10027.303506 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10027.303506 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1966568 # number of writebacks -system.cpu0.icache.writebacks::total 1966568 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1967094 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1967094 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1967094 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1967094 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1967094 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1967094 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 2036864 # number of writebacks +system.cpu0.icache.writebacks::total 2036864 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2037394 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 2037394 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 2037394 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 2037394 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 2037394 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 2037394 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3277 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 3277 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3277 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 3277 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 18813359500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 18813359500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 18813359500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 18813359500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 18813359500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 18813359500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19410871500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 19410871500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19410871500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 19410871500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19410871500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 19410871500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 323882000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 323882000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 323882000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 323882000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050785 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050785 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050785 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.050785 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050785 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.050785 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9564.036848 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9564.036848 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9564.036848 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9564.036848 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9564.036848 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9564.036848 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.051262 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.051262 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.051262 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.051262 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.051262 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.051262 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9527.303752 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9527.303752 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9527.303752 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9527.303752 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9527.303752 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9527.303752 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98834.909979 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98834.909979 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98834.909979 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98834.909979 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1845428 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1845508 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 70 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1927829 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1927948 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 103 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 235148 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 289262 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15626.234267 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2591525 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 304855 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 8.500845 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 243748 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 297127 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15638.814401 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2702273 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 312734 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 8.640803 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14514.282419 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 66.020594 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.070348 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1045.860906 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.885881 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004030 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063834 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.953750 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 230 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15349 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 21 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 121 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 83 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 14568.839087 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.655947 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.055478 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1008.263889 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.889211 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003763 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000003 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.061540 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.954517 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 252 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15345 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 32 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 142 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 72 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1192 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7258 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5558 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1085 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.014038 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.936829 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 91498325 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 91498325 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 78219 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5306 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 83525 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 481785 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 481785 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 2159151 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 2159151 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 222970 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 222970 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1875280 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1875280 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 389002 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 389002 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 78219 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5306 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1875280 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 611972 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 2570777 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 78219 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5306 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1875280 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 611972 # number of overall hits -system.cpu0.l2cache.overall_hits::total 2570777 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 1055 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 176 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1231 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 56519 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 56519 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20396 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 20396 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 46078 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 46078 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 91814 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 91814 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 114162 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 114162 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 1055 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 176 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 91814 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 160240 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 253285 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 1055 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 176 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 91814 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 160240 # number of overall misses -system.cpu0.l2cache.overall_misses::total 253285 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 45088000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4105500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 49193500 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 43638000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 43638000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 10254000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 10254000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 591500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 591500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2907293999 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2907293999 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 4520777000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 4520777000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3763870996 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3763870996 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 45088000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4105500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4520777000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 6671164995 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 11241135495 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 45088000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4105500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4520777000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 6671164995 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 11241135495 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 79274 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5482 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 84756 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 481785 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 481785 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 2159151 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 2159151 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56519 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 56519 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20396 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 20396 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269048 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 269048 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1967094 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 1967094 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 503164 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 503164 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 79274 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5482 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1967094 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 772212 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 2824062 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 79274 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5482 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1967094 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 772212 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 2824062 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.013308 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.032105 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.014524 # miss rate for ReadReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 251 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1191 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7256 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5870 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 777 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.015381 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.936584 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 95152070 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 95152070 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 82993 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5634 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 88627 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 506169 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 506169 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 2242578 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 2242578 # number of WritebackClean hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 235126 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 235126 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1941946 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 1941946 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 414577 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 414577 # number of ReadSharedReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 82993 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5634 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1941946 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 649703 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 2680276 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 82993 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5634 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1941946 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 649703 # number of overall hits +system.cpu0.l2cache.overall_hits::total 2680276 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 792 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 89 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 881 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 56686 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 56686 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20512 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 20512 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 45703 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 45703 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 95448 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 95448 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 115192 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 115192 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 792 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 89 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 95448 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 160895 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 257224 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 792 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 89 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 95448 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 160895 # number of overall misses +system.cpu0.l2cache.overall_misses::total 257224 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 39518000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2258000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 41776000 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 46480500 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 46480500 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 11233000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 11233000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 499500 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 499500 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2934504499 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 2934504499 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 4610090000 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 4610090000 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3801275499 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3801275499 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 39518000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2258000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4610090000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 6735779998 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 11387645998 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 39518000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2258000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4610090000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 6735779998 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 11387645998 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 83785 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5723 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 89508 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 506169 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 506169 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 2242578 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 2242578 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56686 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 56686 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20512 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 20512 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 280829 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 280829 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 2037394 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 2037394 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 529769 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 529769 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 83785 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5723 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 2037394 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 810598 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 2937500 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 83785 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5723 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 2037394 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 810598 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 2937500 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009453 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.015551 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.009843 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.171263 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.171263 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.046675 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.046675 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.226888 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.226888 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.013308 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.032105 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.046675 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.207508 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.089688 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.013308 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.032105 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.046675 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.207508 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.089688 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 42737.440758 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23326.704545 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 39962.225833 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 772.094340 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 772.094340 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 502.745636 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 502.745636 # average SCUpgradeReq miss latency +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.162743 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.162743 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.046848 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.046848 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.217438 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.217438 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009453 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.015551 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.046848 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.198489 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.087566 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009453 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.015551 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.046848 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.198489 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.087566 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 49896.464646 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 25370.786517 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 47418.842225 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 819.964365 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 819.964365 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 547.630655 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 547.630655 # average SCUpgradeReq miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63095.056187 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63095.056187 # average ReadExReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 49238.427691 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 49238.427691 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32969.560765 # average ReadSharedReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32969.560765 # average ReadSharedReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 42737.440758 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23326.704545 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49238.427691 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41632.332720 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 44381.370768 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 42737.440758 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23326.704545 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49238.427691 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41632.332720 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 44381.370768 # average overall miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 64208.137300 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 64208.137300 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 48299.492918 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 48299.492918 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32999.474781 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32999.474781 # average ReadSharedReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 49896.464646 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 25370.786517 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 48299.492918 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41864.445744 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 44271.319931 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 49896.464646 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 25370.786517 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 48299.492918 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41864.445744 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 44271.319931 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 32 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.unused_prefetches 10931 # number of HardPF blocks evicted w/o reference -system.cpu0.l2cache.writebacks::writebacks 232720 # number of writebacks -system.cpu0.l2cache.writebacks::total 232720 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 4 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 4 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3236 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 3236 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 62 # number of ReadCleanReq MSHR hits -system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 62 # number of ReadCleanReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 399 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 399 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 4 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 4 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 62 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3635 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 3705 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 4 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 4 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 62 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3635 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 3705 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 1051 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 172 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 1223 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 265014 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 265014 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 56519 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 56519 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20396 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20396 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42842 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 42842 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 91752 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 91752 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 113763 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 113763 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 1051 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 172 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 91752 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 156605 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 249580 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 1051 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 172 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 91752 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 156605 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 265014 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 514594 # number of overall MSHR misses +system.cpu0.l2cache.unused_prefetches 10950 # number of HardPF blocks evicted w/o reference +system.cpu0.l2cache.writebacks::writebacks 237127 # number of writebacks +system.cpu0.l2cache.writebacks::total 237127 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3260 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 3260 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 60 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 60 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 437 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 437 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 60 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3697 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 3758 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 60 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3697 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 3758 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 791 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 89 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 880 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 267610 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 267610 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 56686 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 56686 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20512 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20512 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42443 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 42443 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 95388 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 95388 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 114755 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 114755 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 791 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 89 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 95388 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 157198 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 253466 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 791 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 89 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 95388 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 157198 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 267610 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 521076 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3277 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20581 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 23858 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19270 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19270 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20603 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 23880 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19302 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19302 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3277 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39851 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 43128 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 38674000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3003500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 41677500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16721781964 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 16721781964 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 978283000 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 978283000 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 308154500 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 308154500 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 483500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 483500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2153848999 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2153848999 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3967827500 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3967827500 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 3058327496 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 3058327496 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 38674000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3003500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3967827500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5212176495 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 9221681495 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 38674000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3003500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3967827500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5212176495 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16721781964 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 25943463459 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39905 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 43182 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 34749000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1724000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 36473000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17027732697 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17027732697 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 983576499 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 983576499 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 310242000 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 310242000 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 403500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 403500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2182275999 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2182275999 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 4035832000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 4035832000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 3088712499 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 3088712499 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 34749000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1724000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 4035832000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5270988498 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 9343293498 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 34749000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1724000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 4035832000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5270988498 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17027732697 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 26371026195 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 297666000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4442744500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4740410500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4446739000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4744405000 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 297666000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4442744500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4740410500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.013258 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031375 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.014430 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4446739000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4744405000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009441 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.015551 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009832 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159236 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159236 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.046643 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.046643 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.226095 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.226095 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.013258 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031375 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.046643 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.202801 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.088376 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.013258 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031375 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.046643 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.202801 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.151135 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.151135 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.046819 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.046819 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.216613 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.216613 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009441 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.015551 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.046819 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.193928 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.086286 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009441 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.015551 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.046819 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.193928 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.182218 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36797.335871 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17462.209302 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 34078.086672 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63097.730550 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63097.730550 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17308.922663 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17308.922663 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15108.575211 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15108.575211 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.177388 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 43930.467762 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 19370.786517 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 41446.590909 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63628.910343 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63628.910343 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17351.312476 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17351.312476 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15124.902496 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15124.902496 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 50274.240208 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 50274.240208 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43245.133621 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43245.133621 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26883.323189 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26883.323189 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36797.335871 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17462.209302 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43245.133621 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33282.312155 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36948.799964 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36797.335871 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17462.209302 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43245.133621 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33282.312155 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63097.730550 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50415.402160 # average overall mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 51416.629338 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 51416.629338 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42309.640626 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42309.640626 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26915.711725 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26915.711725 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 43930.467762 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 19370.786517 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42309.640626 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33530.887785 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36862.117594 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 43930.467762 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 19370.786517 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42309.640626 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33530.887785 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63628.910343 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50608.790647 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215866.308731 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198692.702657 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215829.684997 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198676.926298 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111483.889990 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109914.916064 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 5521359 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2782090 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 42565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 221607 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 217384 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4223 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 119065 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2638335 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 19270 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19270 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 714834 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 2201699 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 105895 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 314040 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 88690 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43009 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 113952 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 288266 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284716 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1967094 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 603225 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3100 # Transaction distribution +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111433.128681 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109869.968969 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 5741859 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2893899 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 44137 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 221175 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 217002 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4173 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 125397 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2741625 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 19302 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19302 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 743607 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 2286693 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 110010 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 316910 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 86864 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42906 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 113874 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 31 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 299874 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 296474 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 2037394 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 616815 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3112 # Transaction distribution system.cpu0.toL2Bus.trans_dist::InvalidateResp 13 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5907309 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2596679 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13203 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 166718 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 8683909 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 251964032 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99557768 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 21928 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 317096 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 351860824 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 942421 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 19099824 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 3784720 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.076642 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.270185 # Request fanout histogram +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 6118205 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2712873 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14034 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 176949 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 9022061 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 260962176 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 104517534 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 22892 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 335140 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 365837742 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 939630 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 19388808 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 3896038 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.075284 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.267877 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 3498873 92.45% 92.45% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 281624 7.44% 99.89% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 4223 0.11% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 3606903 92.58% 92.58% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 284962 7.31% 99.89% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4173 0.11% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3784720 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 5512121494 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3896038 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 5733869996 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115701354 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115563972 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2955829450 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 3061282943 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1228012492 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1285797933 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7726489 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 8314992 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 87463960 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 93182962 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 19376501 # Number of BP lookups -system.cpu1.branchPred.condPredicted 6203106 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 800498 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 9925818 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3621861 # Number of BTB hits +system.cpu1.branchPred.lookups 18647514 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5782822 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 870887 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 9511803 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3428026 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 36.489295 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 8664248 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 596452 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 3651980 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 3587973 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 64007 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 23614 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 36.039708 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 8548256 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 712976 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 3551521 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 3498978 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 52543 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 17984 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1375,63 +1370,57 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 26236 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 26236 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19848 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6388 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 26236 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 26236 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 26236 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2697 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12386.911383 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11389.033391 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6251.379906 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 628 23.29% 23.29% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1805 66.93% 90.21% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 172 6.38% 96.59% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.08% 98.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 26 0.96% 99.63% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 2 0.07% 99.70% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 3 0.11% 99.81% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.07% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-106495 3 0.11% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2697 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1855739032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1855739032 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1855739032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 2013 74.64% 74.64% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 684 25.36% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2697 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26236 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 22971 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 22971 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19558 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3413 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 22971 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 22971 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 22971 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1848 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12803.300866 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11525.814953 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 15800.491207 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 1844 99.78% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 3 0.16% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.05% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1848 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1978443032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1978443032 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1978443032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1308 70.78% 70.78% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 540 29.22% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1848 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 22971 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26236 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2697 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 22971 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1848 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2697 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 28933 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1848 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 24819 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 11335471 # DTB read hits -system.cpu1.dtb.read_misses 23997 # DTB read misses -system.cpu1.dtb.write_hits 7067505 # DTB write hits -system.cpu1.dtb.write_misses 2239 # DTB write misses +system.cpu1.dtb.read_hits 10530339 # DTB read hits +system.cpu1.dtb.read_misses 20830 # DTB read misses +system.cpu1.dtb.write_hits 6472980 # DTB write hits +system.cpu1.dtb.write_misses 2141 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1990 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 147 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 359 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1623 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 116 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 297 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 265 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 11359468 # DTB read accesses -system.cpu1.dtb.write_accesses 7069744 # DTB write accesses +system.cpu1.dtb.perms_faults 184 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10551169 # DTB read accesses +system.cpu1.dtb.write_accesses 6475121 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 18402976 # DTB hits -system.cpu1.dtb.misses 26236 # DTB misses -system.cpu1.dtb.accesses 18429212 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 17003319 # DTB hits +system.cpu1.dtb.misses 22971 # DTB misses +system.cpu1.dtb.accesses 17026290 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1461,45 +1450,43 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 2445 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2445 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 180 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2265 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2445 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2445 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2445 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1122 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12500.891266 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11818.240424 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 4741.770571 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 175 15.60% 15.60% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 626 55.79% 71.39% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 208 18.54% 89.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 49 4.37% 94.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 21 1.87% 96.17% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 29 2.58% 98.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 9 0.80% 99.55% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.18% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1122 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1856356532 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1856356532 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1856356532 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 957 85.29% 85.29% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 165 14.71% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1122 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 2051 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2051 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 145 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1906 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2051 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2051 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2051 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 830 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12046.987952 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11480.071390 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 4509.628818 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 126 15.18% 15.18% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 555 66.87% 82.05% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 85 10.24% 92.29% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 14 1.69% 93.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 22 2.65% 96.63% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 18 2.17% 98.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 6 0.72% 99.52% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 99.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.36% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 830 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1979056532 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1979056532 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1979056532 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 695 83.73% 83.73% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 135 16.27% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 830 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2445 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2445 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2051 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2051 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1122 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1122 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 3567 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 39707544 # ITB inst hits -system.cpu1.itb.inst_misses 2445 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 830 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 830 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2881 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 38623354 # ITB inst hits +system.cpu1.itb.inst_misses 2051 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1508,790 +1495,785 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1094 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 830 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1860 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1040 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 39709989 # ITB inst accesses -system.cpu1.itb.hits 39707544 # DTB hits -system.cpu1.itb.misses 2445 # DTB misses -system.cpu1.itb.accesses 39709989 # DTB accesses -system.cpu1.numPwrStateTransitions 5531 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2766 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1008751457.310195 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25700289930.408852 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1968 71.15% 71.15% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 794 28.71% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 38625405 # ITB inst accesses +system.cpu1.itb.hits 38623354 # DTB hits +system.cpu1.itb.misses 2051 # DTB misses +system.cpu1.itb.accesses 38625405 # DTB accesses +system.cpu1.numPwrStateTransitions 5477 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2739 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1019571073.706097 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25827442882.959442 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1941 70.87% 70.87% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 794 28.99% 99.85% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 949980202104 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2766 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 58706424080 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2790206530920 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 117416330 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 949980394548 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2739 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 55993511619 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2792605170881 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 111990488 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 48257451 # Number of instructions committed -system.cpu1.committedOps 59047178 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 5145755 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2766 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5579767080 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.433123 # CPI: cycles per instruction -system.cpu1.ipc 0.410994 # IPC: instructions per cycle -system.cpu1.op_class_0::No_OpClass 66 0.00% 0.00% # Class of committed instruction -system.cpu1.op_class_0::IntAlu 40655660 68.85% 68.85% # Class of committed instruction -system.cpu1.op_class_0::IntMult 45723 0.08% 68.93% # Class of committed instruction -system.cpu1.op_class_0::IntDiv 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::FloatAdd 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::FloatCmp 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::FloatCvt 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::FloatMult 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::FloatMultAcc 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::FloatDiv 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::FloatMisc 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::FloatSqrt 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdAdd 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdAddAcc 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdAlu 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdCmp 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdCvt 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdMisc 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdMult 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdMultAcc 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdShift 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdSqrt 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMisc 3341 0.01% 68.94% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMult 0 0.00% 68.94% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 68.94% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 68.94% # Class of committed instruction -system.cpu1.op_class_0::MemRead 11158922 18.90% 87.83% # Class of committed instruction -system.cpu1.op_class_0::MemWrite 7181682 12.16% 100.00% # Class of committed instruction -system.cpu1.op_class_0::FloatMemRead 516 0.00% 100.00% # Class of committed instruction -system.cpu1.op_class_0::FloatMemWrite 1268 0.00% 100.00% # Class of committed instruction +system.cpu1.committedInsts 45059059 # Number of instructions committed +system.cpu1.committedOps 55122963 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 4849343 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2739 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5584538446 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.485416 # CPI: cycles per instruction +system.cpu1.ipc 0.402347 # IPC: instructions per cycle +system.cpu1.op_class_0::No_OpClass 24 0.00% 0.00% # Class of committed instruction +system.cpu1.op_class_0::IntAlu 38107074 69.13% 69.13% # Class of committed instruction +system.cpu1.op_class_0::IntMult 43629 0.08% 69.21% # Class of committed instruction +system.cpu1.op_class_0::IntDiv 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::FloatAdd 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::FloatCmp 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::FloatCvt 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::FloatMult 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::FloatMultAcc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::FloatDiv 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::FloatMisc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdAdd 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdAlu 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdCmp 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdCvt 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdMisc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdMult 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdShift 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMisc 3226 0.01% 69.22% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.22% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.22% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.22% # Class of committed instruction +system.cpu1.op_class_0::MemRead 10387367 18.84% 88.06% # Class of committed instruction +system.cpu1.op_class_0::MemWrite 6581643 11.94% 100.00% # Class of committed instruction +system.cpu1.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu1.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.op_class_0::total 59047178 # Class of committed instruction +system.cpu1.op_class_0::total 55122963 # Class of committed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2766 # number of quiesce instructions executed -system.cpu1.tickCycles 94212752 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 23203578 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 197406 # number of replacements -system.cpu1.dcache.tags.tagsinuse 475.838335 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 17978253 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 197762 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 90.908531 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 91321339500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 475.838335 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.929372 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.929372 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 356 # Occupied blocks per task id +system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed +system.cpu1.tickCycles 90184958 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 21805530 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 157661 # number of replacements +system.cpu1.dcache.tags.tagsinuse 475.726390 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 16648746 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 158020 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 105.358474 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 91198641000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 475.726390 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.929153 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.929153 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 284 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 72 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.695312 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 36857417 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 36857417 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 10958654 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 10958654 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6778912 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6778912 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50538 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 50538 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80236 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 80236 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71701 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71701 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 17737566 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 17737566 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 17788104 # number of overall hits -system.cpu1.dcache.overall_hits::total 17788104 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 149954 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 149954 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 146295 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 146295 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30728 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30728 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16950 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16950 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23669 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23669 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 296249 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 296249 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 326977 # number of overall misses -system.cpu1.dcache.overall_misses::total 326977 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2480923500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2480923500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4141245000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 4141245000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 326364000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 326364000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 557050500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 557050500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 662000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 662000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6622168500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6622168500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6622168500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6622168500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 11108608 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 11108608 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6925207 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6925207 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 81266 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 81266 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97186 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 97186 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95370 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 95370 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 18033815 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 18033815 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 18115081 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 18115081 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.013499 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.013499 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021125 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.021125 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.378116 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.378116 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174408 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174408 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248181 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248181 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.016427 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.016427 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.018050 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.018050 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16544.563666 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16544.563666 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28307.495130 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 28307.495130 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19254.513274 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19254.513274 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23535.024716 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23535.024716 # average StoreCondReq miss latency +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 34039754 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 34039754 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 10204486 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 10204486 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6223411 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6223411 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 43300 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 43300 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 71256 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 71256 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 62645 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 62645 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 16427897 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 16427897 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 16471197 # number of overall hits +system.cpu1.dcache.overall_hits::total 16471197 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 127390 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 127390 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 122263 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 122263 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24165 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 24165 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16525 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 16525 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23356 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23356 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 249653 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 249653 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 273818 # number of overall misses +system.cpu1.dcache.overall_misses::total 273818 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2191208500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2191208500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3801376500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3801376500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 322530000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 322530000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 548226000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 548226000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 650000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 650000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 5992585000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 5992585000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 5992585000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 5992585000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 10331876 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 10331876 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6345674 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6345674 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 67465 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 67465 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87781 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 87781 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 86001 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 86001 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 16677550 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 16677550 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 16745015 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 16745015 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.012330 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.012330 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.019267 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.019267 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.358186 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.358186 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.188253 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.188253 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.271578 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.271578 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.014969 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.014969 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.016352 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.016352 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17200.788916 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 17200.788916 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31091.798009 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 31091.798009 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19517.700454 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19517.700454 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23472.598048 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23472.598048 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22353.386847 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 22353.386847 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20252.704319 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20252.704319 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24003.657076 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 24003.657076 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21885.285116 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 21885.285116 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 197406 # number of writebacks -system.cpu1.dcache.writebacks::total 197406 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 5638 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 5638 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 53221 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 53221 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12059 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12059 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 58859 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 58859 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 58859 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 58859 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 144316 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 144316 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 93074 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 93074 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29900 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29900 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4891 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4891 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23669 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23669 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 237390 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 237390 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 267290 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 267290 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14424 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14424 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11757 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11757 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26181 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26181 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2239010000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2239010000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2480218000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2480218000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 521766000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 521766000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86789500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86789500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 533397500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 533397500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 646000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 646000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4719228000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4719228000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5240994000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5240994000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2492996500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2492996500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2492996500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2492996500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.012991 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.012991 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013440 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013440 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.367928 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.367928 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050326 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050326 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248181 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248181 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013164 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.013164 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014755 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.014755 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15514.634552 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15514.634552 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26647.807121 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26647.807121 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17450.367893 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17450.367893 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17744.735228 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17744.735228 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22535.700706 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22535.700706 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 157661 # number of writebacks +system.cpu1.dcache.writebacks::total 157661 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 4447 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 4447 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 42267 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 42267 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11747 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11747 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 46714 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 46714 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 46714 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 46714 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 122943 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 122943 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 79996 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 79996 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23657 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 23657 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4778 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4778 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23356 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23356 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 202939 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 202939 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 226596 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 226596 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14406 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14406 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11728 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11728 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26134 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26134 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1987288500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1987288500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2305734500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2305734500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 418963500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 418963500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86008500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86008500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 524885000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 524885000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 635000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 635000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4293023000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4293023000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4711986500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4711986500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2490253500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2490253500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2490253500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2490253500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.011899 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.011899 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012606 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.012606 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.350656 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.350656 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054431 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054431 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.271578 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.271578 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.012168 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.012168 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.013532 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.013532 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16164.307850 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16164.307850 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28823.122406 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28823.122406 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17709.916727 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17709.916727 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18000.941817 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18000.941817 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22473.240281 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22473.240281 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19879.641097 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19879.641097 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19607.894048 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19607.894048 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172836.695785 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172836.695785 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95221.591994 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95221.591994 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 951563 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.187738 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 38753540 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 952075 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.704293 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 73017738000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.187738 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974976 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974976 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21154.253249 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21154.253249 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20794.658776 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20794.658776 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172862.244898 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172862.244898 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95287.881687 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95287.881687 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 872875 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.208474 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 37748872 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 873387 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 43.221243 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 72896771000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.208474 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975017 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975017 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 466 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 463 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 48 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 80363305 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 80363305 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 38753540 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 38753540 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 38753540 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 38753540 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 38753540 # number of overall hits -system.cpu1.icache.overall_hits::total 38753540 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 952075 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 952075 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 952075 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 952075 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 952075 # number of overall misses -system.cpu1.icache.overall_misses::total 952075 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8812564500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8812564500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8812564500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8812564500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8812564500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8812564500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 39705615 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 39705615 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 39705615 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 39705615 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 39705615 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 39705615 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023978 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.023978 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023978 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.023978 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023978 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.023978 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9256.166268 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9256.166268 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9256.166268 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9256.166268 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9256.166268 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9256.166268 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 78117905 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 78117905 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 37748872 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 37748872 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 37748872 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 37748872 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 37748872 # number of overall hits +system.cpu1.icache.overall_hits::total 37748872 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 873387 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 873387 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 873387 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 873387 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 873387 # number of overall misses +system.cpu1.icache.overall_misses::total 873387 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8011666500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8011666500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8011666500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8011666500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8011666500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8011666500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 38622259 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 38622259 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 38622259 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 38622259 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 38622259 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 38622259 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022614 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.022614 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022614 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.022614 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022614 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.022614 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9173.100241 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9173.100241 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9173.100241 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9173.100241 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9173.100241 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9173.100241 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 951563 # number of writebacks -system.cpu1.icache.writebacks::total 951563 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 952075 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 952075 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 952075 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 952075 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 952075 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 952075 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 872875 # number of writebacks +system.cpu1.icache.writebacks::total 872875 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 873387 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 873387 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 873387 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 873387 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 873387 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 873387 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8336527000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8336527000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8336527000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8336527000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8336527000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8336527000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10996500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10996500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10996500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 10996500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023978 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023978 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023978 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.023978 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023978 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.023978 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8756.166268 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8756.166268 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8756.166268 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8756.166268 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8756.166268 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8756.166268 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 98183.035714 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 98183.035714 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 98183.035714 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 98183.035714 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 202046 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 202062 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7574973000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7574973000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7574973000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7574973000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7574973000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7574973000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11042500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 11042500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 11042500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 11042500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022614 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022614 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022614 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.022614 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022614 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.022614 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8673.100241 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8673.100241 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8673.100241 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8673.100241 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8673.100241 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8673.100241 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 98593.750000 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 98593.750000 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 98593.750000 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 98593.750000 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 118852 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 118852 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 58314 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 53261 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14759.472479 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1060224 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 67460 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 15.716336 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 49172 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 37377 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14753.834184 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 946442 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 52088 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 18.170058 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14399.124814 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 38.202581 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.100138 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 322.044945 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.878853 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002332 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.019656 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.900847 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 251 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 42 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13906 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 79 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 172 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1287 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7824 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4795 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.015320 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002563 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.848755 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 39696628 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 39696628 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 28743 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 3180 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 31923 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 117832 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 117832 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 1010940 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 1010940 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28052 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 28052 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 916446 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 916446 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 103629 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 103629 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 28743 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 3180 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 916446 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 131681 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 1080050 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 28743 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 3180 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 916446 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 131681 # number of overall hits -system.cpu1.l2cache.overall_hits::total 1080050 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 682 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 266 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 948 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 30054 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 30054 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23668 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23668 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34968 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 34968 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 35629 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 35629 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 75478 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 75478 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 682 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 266 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 35629 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 110446 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 147023 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 682 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 266 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 35629 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 110446 # number of overall misses -system.cpu1.l2cache.overall_misses::total 147023 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 15962500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5289000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 21251500 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 13859000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 13859000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 17603500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 17603500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 622000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 622000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1509066000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1509066000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1359934000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1359934000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1890312995 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1890312995 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 15962500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5289000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1359934000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 3399378995 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 4780564495 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 15962500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5289000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1359934000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3399378995 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 4780564495 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29425 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 3446 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 32871 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 117832 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 117832 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 1010940 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 1010940 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30054 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 30054 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23668 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23668 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63020 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 63020 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 952075 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 952075 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 179107 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 179107 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29425 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 3446 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 952075 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 242127 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 1227073 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29425 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 3446 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 952075 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 242127 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 1227073 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023178 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.077191 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.028840 # miss rate for ReadReq accesses +system.cpu1.l2cache.tags.occ_blocks::writebacks 14422.597482 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 42.225036 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.137350 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 287.874316 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.880285 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002577 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000069 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.017570 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.900503 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 261 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 78 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14372 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 24 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 234 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 53 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1285 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2929 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10158 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.015930 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004761 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.877197 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 35693220 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 35693220 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 23446 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2580 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 26026 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 95283 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 95283 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 916386 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 916386 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 18220 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 18220 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 844850 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 844850 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 81639 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 81639 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 23446 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2580 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 844850 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 99859 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 970735 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 23446 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2580 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 844850 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 99859 # number of overall hits +system.cpu1.l2cache.overall_hits::total 970735 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 823 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 297 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 1120 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29230 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 29230 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23356 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 23356 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32546 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 32546 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 28537 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 28537 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69739 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 69739 # number of ReadSharedReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 823 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 297 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 28537 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 102285 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 131942 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 823 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 297 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 28537 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 102285 # number of overall misses +system.cpu1.l2cache.overall_misses::total 131942 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 21253500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5882500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 27136000 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 7496000 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 7496000 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 16835000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 16835000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 611000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 611000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1439672500 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1439672500 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1146878000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1146878000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1720708495 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1720708495 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 21253500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5882500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1146878000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 3160380995 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 4334394995 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 21253500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5882500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1146878000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 3160380995 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 4334394995 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 24269 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2877 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 27146 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 95283 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 95283 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 916386 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 916386 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29230 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 29230 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23356 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23356 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 50766 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 50766 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 873387 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 873387 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 151378 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 151378 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 24269 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2877 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 873387 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 202144 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 1102677 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 24269 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2877 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 873387 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 202144 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 1102677 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.033912 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.103233 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.041258 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.554871 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.554871 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.037422 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.037422 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.421413 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.421413 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023178 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.077191 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.037422 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.456149 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.119816 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023178 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.077191 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.037422 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.456149 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.119816 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23405.425220 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19883.458647 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22417.194093 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 461.136621 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 461.136621 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 743.767957 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 743.767957 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 622000 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 622000 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43155.628003 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43155.628003 # average ReadExReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38169.300289 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38169.300289 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 25044.555963 # average ReadSharedReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 25044.555963 # average ReadSharedReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23405.425220 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19883.458647 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38169.300289 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 30778.651966 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 32515.759405 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23405.425220 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19883.458647 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38169.300289 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 30778.651966 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 32515.759405 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 24 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.641098 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.641098 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.032674 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.032674 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.460694 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.460694 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.033912 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.103233 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.032674 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.506001 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.119656 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.033912 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.103233 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.032674 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.506001 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.119656 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 25824.422843 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19806.397306 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24228.571429 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 256.448854 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 256.448854 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 720.799794 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 720.799794 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44235.005838 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44235.005838 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 40189.157935 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 40189.157935 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 24673.547011 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 24673.547011 # average ReadSharedReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 25824.422843 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19806.397306 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40189.157935 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 30897.795327 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 32850.760145 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 25824.422843 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19806.397306 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40189.157935 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 30897.795327 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 32850.760145 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 24 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.unused_prefetches 862 # number of HardPF blocks evicted w/o reference -system.cpu1.l2cache.writebacks::writebacks 36438 # number of writebacks -system.cpu1.l2cache.writebacks::total 36438 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 196 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 196 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 18 # number of ReadCleanReq MSHR hits -system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 87 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 87 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 18 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 283 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 302 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 18 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 283 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 302 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 681 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 266 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 947 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 26287 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 26287 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 30054 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 30054 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23668 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23668 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34772 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 34772 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 35611 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 35611 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 75391 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 75391 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 681 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 266 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 35611 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 110163 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 146721 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 681 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 266 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 35611 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 110163 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 26287 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 173008 # number of overall MSHR misses +system.cpu1.l2cache.unused_prefetches 596 # number of HardPF blocks evicted w/o reference +system.cpu1.l2cache.writebacks::writebacks 29159 # number of writebacks +system.cpu1.l2cache.writebacks::total 29159 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 3 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 3 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 174 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 174 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 5 # number of ReadCleanReq MSHR hits +system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 44 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 44 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 3 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 3 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 218 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 229 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 3 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 3 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 218 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 229 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 820 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 294 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 1114 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 19637 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 19637 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29230 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29230 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23356 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23356 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 32372 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 32372 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 28532 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 28532 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69695 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69695 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 820 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 294 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 28532 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 102067 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 131713 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 820 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 294 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 28532 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 102067 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 19637 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 151350 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14424 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14536 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11757 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11757 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14406 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14518 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11728 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11728 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26181 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26293 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 11857500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3693000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 15550500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 965321170 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 965321170 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 461957500 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 461957500 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 354728500 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 354728500 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 526000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 526000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1277222000 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1277222000 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 1145765500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 1145765500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1434909495 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1434909495 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 11857500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3693000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1145765500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2712131495 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 3873447495 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 11857500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3693000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1145765500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2712131495 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 965321170 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 4838768665 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10100500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2377583500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2387684000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 10100500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2377583500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2387684000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023144 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.077191 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.028810 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26134 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26246 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 16302000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4074000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 20376000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 732946008 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 732946008 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 445433500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 445433500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 348598000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 348598000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 521000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 521000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1224744500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1224744500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 975419000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 975419000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1300674995 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1300674995 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 16302000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4074000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 975419000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2525419495 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 3521214495 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 16302000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4074000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 975419000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2525419495 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 732946008 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4254160503 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10146500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2374983500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2385130000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 10146500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2374983500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2385130000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.033788 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.102190 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.041037 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.551761 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.551761 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.037404 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.037404 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.420927 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.420927 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023144 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.077191 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.037404 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.454980 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.119570 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023144 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.077191 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.037404 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.454980 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.637671 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.637671 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.032668 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.032668 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.460404 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.460404 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.033788 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.102190 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.032668 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.504922 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.119448 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.033788 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.102190 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.032668 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.504922 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.140992 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17411.894273 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13883.458647 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16420.802534 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36722.378742 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36722.378742 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15370.915685 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15370.915685 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14987.683792 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14987.683792 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 526000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 526000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36731.335557 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36731.335557 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32174.482604 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32174.482604 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 19032.901739 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 19032.901739 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17411.894273 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13883.458647 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32174.482604 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24619.259597 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26400.089251 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17411.894273 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13883.458647 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32174.482604 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24619.259597 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36722.378742 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27968.467730 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90183.035714 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164835.239878 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164260.044029 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90183.035714 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90813.318819 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90810.634009 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 2407036 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1212847 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 20197 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 118681 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 110741 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 7940 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 51870 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1220498 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 11757 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11757 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 156434 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 1031137 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 35507 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 31472 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 73789 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42123 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86153 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 70267 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 67627 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 952075 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 295896 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 106 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2855937 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 915985 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8156 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62049 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 3842127 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 121840000 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 30925576 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13784 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 117700 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 152897060 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 370911 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 5180924 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 1603484 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.097889 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.313386 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.137257 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19880.487805 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13857.142857 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18290.843806 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37324.744513 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 37324.744513 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15238.915498 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15238.915498 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14925.415311 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14925.415311 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37833.451748 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37833.451748 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34186.842843 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34186.842843 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 18662.386039 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 18662.386039 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19880.487805 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13857.142857 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34186.842843 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24742.762058 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26733.993569 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19880.487805 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13857.142857 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34186.842843 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24742.762058 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37324.744513 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28108.097146 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90593.750000 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164860.717756 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164287.780686 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90593.750000 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90877.152369 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90875.943001 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 2165902 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1090398 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18866 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 115909 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 108045 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 7864 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 44859 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1106447 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11728 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11728 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 126621 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 935252 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 26571 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 23763 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 71775 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41777 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 84685 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 31 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 58060 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 55427 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 873387 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 263309 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 71 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2619873 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 793002 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6834 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50653 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3470362 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 111767936 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25786238 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11508 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 97076 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 137662758 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 338759 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 4674348 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1446654 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.103615 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.322104 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1454460 90.71% 90.71% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 141084 8.80% 99.50% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 7940 0.50% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1304623 90.18% 90.18% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 134167 9.27% 99.46% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 7864 0.54% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1603484 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 2385111494 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1446654 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 2144021494 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79363429 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 78336814 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1428355849 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 412276680 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1310300396 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 351676729 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4711996 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 3959994 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 32634978 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 26397473 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 31015 # Transaction distribution -system.iobus.trans_dist::ReadResp 31015 # Transaction distribution -system.iobus.trans_dist::WriteReq 59422 # Transaction distribution -system.iobus.trans_dist::WriteResp 59422 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 31009 # Transaction distribution +system.iobus.trans_dist::ReadResp 31009 # Transaction distribution +system.iobus.trans_dist::WriteReq 59424 # Transaction distribution +system.iobus.trans_dist::WriteResp 59424 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56618 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -2310,11 +2292,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107932 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71562 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -2333,94 +2315,94 @@ system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48355001 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 162812 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2483988 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 48425501 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 110500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 333000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 324500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 29500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 12500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 92500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 88500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 611500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 621000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 19500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6349500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6370500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38550000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 39055001 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187836280 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187730317 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84732000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 36461 # number of replacements -system.iocache.tags.tagsinuse 14.472129 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 36449 # number of replacements +system.iocache.tags.tagsinuse 14.472713 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36477 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 272035829000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.472129 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.904508 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.904508 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 271902155000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.472713 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.904545 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.904545 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328311 # Number of tag accesses -system.iocache.tags.data_accesses 328311 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses -system.iocache.ReadReq_misses::total 255 # number of ReadReq misses +system.iocache.tags.tag_accesses 328203 # Number of tag accesses +system.iocache.tags.data_accesses 328203 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses +system.iocache.ReadReq_misses::total 243 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses -system.iocache.demand_misses::total 36479 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36479 # number of overall misses -system.iocache.overall_misses::total 36479 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 33894626 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 33894626 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4361652654 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4361652654 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4395547280 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4395547280 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4395547280 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4395547280 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 36467 # number of demand (read+write) misses +system.iocache.demand_misses::total 36467 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36467 # number of overall misses +system.iocache.overall_misses::total 36467 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 32482877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32482877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4347292440 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4347292440 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4379775317 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4379775317 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4379775317 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4379775317 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36479 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36479 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36479 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36479 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36467 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36467 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36467 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36467 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -2429,38 +2411,38 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 132920.101961 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 132920.101961 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120407.813991 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120407.813991 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120495.278928 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120495.278928 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120495.278928 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120495.278928 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 133674.390947 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 133674.390947 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120011.385822 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120011.385822 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120102.430060 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120102.430060 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120102.430060 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120102.430060 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 5 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.600000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 3.500000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 36479 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 21144626 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 21144626 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2548533560 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2548533560 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2569678186 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2569678186 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2569678186 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2569678186 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 36467 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 36467 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 36467 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 36467 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 20332877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 20332877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2534226880 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2534226880 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2554559757 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2554559757 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2554559757 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2554559757 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2469,587 +2451,591 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 82920.101961 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 82920.101961 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70354.835468 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70354.835468 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 70442.670742 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70442.670742 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 70442.670742 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70442.670742 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 144965 # number of replacements -system.l2c.tags.tagsinuse 65152.937424 # Cycle average of tags in use -system.l2c.tags.total_refs 609190 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 210433 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.894936 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 94596333000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 6623.641464 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 83.873340 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030778 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8717.297780 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6753.906827 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34978.887881 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 14.032858 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2236.963584 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3439.697056 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2304.605856 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.101069 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001280 # Average percentage of cache occupancy +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 83674.390947 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 83674.390947 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69959.885159 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69959.885159 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70051.272575 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70051.272575 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70051.272575 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70051.272575 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 143599 # number of replacements +system.l2c.tags.tagsinuse 65154.346859 # Cycle average of tags in use +system.l2c.tags.total_refs 605481 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 209069 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.896082 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 94462980000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 6720.710891 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 87.363500 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.029896 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8711.779777 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6725.180439 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34970.113845 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 14.660518 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2224.966255 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3446.409233 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2253.132505 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.102550 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001333 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.133015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.103056 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.533735 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000214 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.034133 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.052486 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.035165 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994155 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 31624 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 33792 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 150 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4711 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 26763 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 52 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.132931 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.102618 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.533602 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000224 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.033950 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.052588 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.034380 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994176 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 32778 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 59 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 32633 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 137 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5072 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 27569 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 59 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 93 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1870 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 31828 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.482544 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.515625 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6850011 # Number of tag accesses -system.l2c.tags.data_accesses 6850011 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 269158 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 269158 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 42928 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 5622 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 48550 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2743 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 2305 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 5048 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4279 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1522 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5801 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 596 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 96 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 68829 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 63546 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47286 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 133 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 12 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 32119 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 13663 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5831 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 232111 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 596 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 96 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 68829 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 67825 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 47286 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 133 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 12 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 32119 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 15185 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 5831 # number of demand (read+write) hits -system.l2c.demand_hits::total 237912 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 596 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 96 # number of overall hits -system.l2c.overall_hits::cpu0.inst 68829 # number of overall hits -system.l2c.overall_hits::cpu0.data 67825 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 47286 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 133 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 12 # number of overall hits -system.l2c.overall_hits::cpu1.inst 32119 # number of overall hits -system.l2c.overall_hits::cpu1.data 15185 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 5831 # number of overall hits -system.l2c.overall_hits::total 237912 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 404 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 229 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 633 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 106 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 82 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 188 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11300 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8634 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19934 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 147 # number of ReadSharedReq misses +system.l2c.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 123 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 1691 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 30817 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.500153 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000900 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.497940 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6803015 # Number of tag accesses +system.l2c.tags.data_accesses 6803015 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 266286 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 266286 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 43645 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 4461 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 48106 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 3017 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 2129 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 5146 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4448 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1231 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5679 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 477 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 86 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 72650 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 65777 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 48761 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 80 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 9 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 24965 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 8445 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3652 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 224902 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 477 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 86 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 72650 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 70225 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 48761 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 80 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 9 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 24965 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 9676 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 3652 # number of demand (read+write) hits +system.l2c.demand_hits::total 230581 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 477 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 86 # number of overall hits +system.l2c.overall_hits::cpu0.inst 72650 # number of overall hits +system.l2c.overall_hits::cpu0.data 70225 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 48761 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 80 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 9 # number of overall hits +system.l2c.overall_hits::cpu1.inst 24965 # number of overall hits +system.l2c.overall_hits::cpu1.data 9676 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 3652 # number of overall hits +system.l2c.overall_hits::total 230581 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 459 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 178 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 637 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 57 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 62 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 119 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 11423 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 8564 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 19987 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 145 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 22922 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 9947 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 132993 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 19 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 3492 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 1704 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6343 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 177568 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 147 # number of demand (read+write) misses +system.l2c.ReadSharedReq_misses::cpu0.inst 22738 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 9967 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134498 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 20 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 3567 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 1751 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5084 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 177771 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 145 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 22922 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 21247 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 132993 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 19 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 3492 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 10338 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 6343 # number of demand (read+write) misses -system.l2c.demand_misses::total 197502 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 147 # number of overall misses +system.l2c.demand_misses::cpu0.inst 22738 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 21390 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 134498 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 20 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 3567 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 10315 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 5084 # number of demand (read+write) misses +system.l2c.demand_misses::total 197758 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 145 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 22922 # number of overall misses -system.l2c.overall_misses::cpu0.data 21247 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 132993 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 19 # number of overall misses -system.l2c.overall_misses::cpu1.inst 3492 # number of overall misses -system.l2c.overall_misses::cpu1.data 10338 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 6343 # number of overall misses -system.l2c.overall_misses::total 197502 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 7730000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 962500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 8692500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 689500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 165500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 855000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 1562017000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 830214000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2392231000 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 21395500 # number of ReadSharedReq miss cycles +system.l2c.overall_misses::cpu0.inst 22738 # number of overall misses +system.l2c.overall_misses::cpu0.data 21390 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 134498 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 20 # number of overall misses +system.l2c.overall_misses::cpu1.inst 3567 # number of overall misses +system.l2c.overall_misses::cpu1.data 10315 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 5084 # number of overall misses +system.l2c.overall_misses::total 197758 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 8555500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 760000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 9315500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 567000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 122000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 689000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 1593574000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 815318500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2408892500 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 22107500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 90000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2310573000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 1198855000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 15885174851 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 1721000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 383378500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 272430000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 845052256 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 20918670107 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 21395500 # number of demand (read+write) miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2317227000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 1217018500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 16177990963 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 4552500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 377306500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 262293500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 655902831 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 21034489294 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 22107500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 90000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 2310573000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 2760872000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15885174851 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1721000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 383378500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1102644000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 845052256 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 23310901107 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 21395500 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu0.inst 2317227000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 2810592500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 16177990963 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 4552500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 377306500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1077612000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 655902831 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 23443381794 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 22107500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 90000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 2310573000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 2760872000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15885174851 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1721000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 383378500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1102644000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 845052256 # number of overall miss cycles -system.l2c.overall_miss_latency::total 23310901107 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 269158 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 269158 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 43332 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 5851 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 49183 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 2849 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 2387 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 5236 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 15579 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 10156 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 25735 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 743 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 97 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 91751 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 73493 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 180279 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 152 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 12 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 35611 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 15367 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 12174 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 409679 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 743 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 97 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 91751 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 89072 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 180279 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 152 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 12 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 35611 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 25523 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 12174 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 435414 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 743 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 97 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 91751 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 89072 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 180279 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 152 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 12 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 35611 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 25523 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 12174 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 435414 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.009323 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.039139 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.012870 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.037206 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.034353 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.035905 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.725335 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.850138 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.774587 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.197847 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.010309 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.249828 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.135346 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.737707 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.098060 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.110887 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.521028 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.433432 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.197847 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.010309 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.249828 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.238537 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.737707 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.098060 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.405046 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.521028 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.453596 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.197847 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.010309 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.249828 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.238537 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.737707 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.098060 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.405046 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.521028 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.453596 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 19133.663366 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4203.056769 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 13732.227488 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6504.716981 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2018.292683 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 4547.872340 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 138231.592920 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 96156.358582 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 120007.574997 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 145547.619048 # average ReadSharedReq miss latency +system.l2c.overall_miss_latency::cpu0.inst 2317227000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 2810592500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 16177990963 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 4552500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 377306500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1077612000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 655902831 # number of overall miss cycles +system.l2c.overall_miss_latency::total 23443381794 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 266286 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 266286 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 44104 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4639 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 48743 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 3074 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 2191 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 5265 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 15871 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 9795 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 25666 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 622 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 87 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 95388 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 75744 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 183259 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 100 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 9 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 28532 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 10196 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 8736 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 402673 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 622 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 87 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 95388 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 91615 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 183259 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 100 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 9 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 28532 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 19991 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 8736 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 428339 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 622 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 87 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 95388 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 91615 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 183259 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 100 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 9 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 28532 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 19991 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 8736 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 428339 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.010407 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.038370 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.013069 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.018543 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.028298 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.022602 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.719740 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.874324 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.778735 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.233119 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.011494 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.238374 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.131588 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.733923 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.200000 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.125018 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.171734 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.581960 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.441477 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.233119 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.011494 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.238374 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.233477 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.733923 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.200000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.125018 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.515982 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.581960 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.461686 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.233119 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.011494 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.238374 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.233477 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.733923 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.200000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.125018 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.515982 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.581960 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.461686 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 18639.433551 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4269.662921 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 14624.018838 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 9947.368421 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1967.741935 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 5789.915966 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139505.734045 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 95203.000934 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 120522.964927 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 152465.517241 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90000 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 100801.544368 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 120524.278677 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119443.691405 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 90578.947368 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 109787.657503 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 159876.760563 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 133225.958695 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 117806.531059 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 145547.619048 # average overall miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 101909.886534 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 122104.795826 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 120284.249305 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 227625 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 105776.983459 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 149796.402056 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 129013.145358 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 118323.513363 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 152465.517241 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 100801.544368 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 129941.732951 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119443.691405 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90578.947368 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 109787.657503 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 106659.315148 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 133225.958695 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 118028.683796 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 145547.619048 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 101909.886534 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 131397.498831 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 120284.249305 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 227625 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 105776.983459 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 104470.382937 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 129013.145358 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 118545.807472 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 152465.517241 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 100801.544368 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 129941.732951 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119443.691405 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90578.947368 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 109787.657503 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 106659.315148 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 133225.958695 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 118028.683796 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 151 # number of cycles access was blocked +system.l2c.overall_avg_miss_latency::cpu0.inst 101909.886534 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 131397.498831 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 120284.249305 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 227625 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 105776.983459 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 104470.382937 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 129013.145358 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 118545.807472 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 4 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 37.750000 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 105386 # number of writebacks -system.l2c.writebacks::total 105386 # number of writebacks -system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 3 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 3 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 3 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 4794 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 4794 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 404 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 229 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 633 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 106 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 82 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 188 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 11300 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 8634 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 19934 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 147 # number of ReadSharedReq MSHR misses +system.l2c.writebacks::writebacks 104081 # number of writebacks +system.l2c.writebacks::total 104081 # number of writebacks +system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 1 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 6 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 4309 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 4309 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 459 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 178 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 637 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 57 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 62 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 119 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 11423 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 8564 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 19987 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 145 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 22919 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9947 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 132993 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 19 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 3492 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1704 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6343 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 177565 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 147 # number of demand (read+write) MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 22733 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9967 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 134498 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 20 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 3566 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1751 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5084 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 177765 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 145 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 22919 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 21247 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 132993 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 19 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 3492 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 10338 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6343 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 197499 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 147 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 22733 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 21390 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134498 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 20 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 3566 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 10315 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5084 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 197752 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 145 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 22919 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 21247 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 132993 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 19 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 3492 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 10338 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6343 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 197499 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 22733 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 21390 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134498 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 20 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 3566 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 10315 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5084 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 197752 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3277 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20581 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20603 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14421 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 38391 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19270 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11757 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 31027 # number of WriteReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14403 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 38395 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19302 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11728 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 31030 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3277 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39851 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39905 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 26178 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 69418 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 8946500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5034000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 13980500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 2786000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1998500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 4784500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1449017000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 743874000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 2192891000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 19925500 # number of ReadSharedReq MSHR miss cycles +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 26131 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 69425 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 10236500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3909500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 14146000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1509500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1453000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 2962500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1479344000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 729678500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 2209022500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 20657500 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 80000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2081229000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1099385000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14555242855 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 1531000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 348458500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 255390000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 781621757 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 19142863612 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 19925500 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2089156001 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1117348500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14833007471 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 4352500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 341582500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 244783001 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 605061833 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 19256029306 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 20657500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 80000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 2081229000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2548402000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 14555242855 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1531000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 348458500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 999264000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 781621757 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 21335754612 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 19925500 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 2089156001 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2596692500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 14833007471 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 4352500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 341582500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 974461501 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 605061833 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 21465051806 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 20657500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 80000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 2081229000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2548402000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14555242855 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1531000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 348458500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 999264000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 781621757 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 21335754612 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 2089156001 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2596692500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14833007471 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 4352500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 341582500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 974461501 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 605061833 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 21465051806 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 228848500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4072237500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7748500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2117933000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6426767500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4075847000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7794500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2115657500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6428147500 # number of ReadReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 228848500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4072237500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7748500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2117933000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 6426767500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4075847000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7794500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2115657500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 6428147500 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.009323 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.039139 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.012870 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.037206 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.034353 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.035905 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.725335 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.850138 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.774587 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.197847 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.010309 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.249796 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.135346 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737707 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.098060 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.110887 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521028 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.433425 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.197847 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.010309 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.249796 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.238537 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737707 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.098060 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.405046 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521028 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.453589 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.197847 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.010309 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.249796 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.238537 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737707 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.098060 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.405046 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521028 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.453589 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22144.801980 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21982.532751 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22086.097946 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26283.018868 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24371.951220 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25449.468085 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 128231.592920 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 86156.358582 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 110007.574997 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 135547.619048 # average ReadSharedReq mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.010407 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.038370 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.013069 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.018543 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.028298 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.022602 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.719740 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.874324 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.778735 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.233119 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.011494 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.238321 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.131588 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.733923 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.200000 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.124982 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.171734 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581960 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.441462 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.233119 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.011494 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.238321 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.233477 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.733923 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.200000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.124982 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.515982 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581960 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.461672 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.233119 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011494 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.238321 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.233477 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.733923 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.200000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.124982 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.515982 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581960 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.461672 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22301.742919 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21963.483146 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22207.221350 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26482.456140 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23435.483871 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24894.957983 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129505.734045 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 85203.000934 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 110522.964927 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 142465.517241 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 90808.019547 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 110524.278677 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109443.676397 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 80578.947368 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 99787.657503 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 149876.760563 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 123225.880025 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 107807.640087 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 135547.619048 # average overall mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 91899.705318 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 112104.795826 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110284.223342 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 217625 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 95788.698822 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 139796.117076 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119012.949056 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108322.950558 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 142465.517241 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90808.019547 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 119941.732951 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109443.676397 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80578.947368 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 99787.657503 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 96659.315148 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 123225.880025 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 108029.684262 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 135547.619048 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 91899.705318 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 121397.498831 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110284.223342 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 217625 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 95788.698822 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94470.334561 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119012.949056 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 108545.308295 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 142465.517241 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90808.019547 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 119941.732951 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109443.676397 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80578.947368 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 99787.657503 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 96659.315148 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 123225.880025 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 108029.684262 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 91899.705318 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 121397.498831 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110284.223342 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 217625 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 95788.698822 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94470.334561 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119012.949056 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 108545.308295 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197863.927895 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69183.035714 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146864.503155 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167402.972051 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197827.840606 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69593.750000 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146890.057627 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167421.474150 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102186.582520 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69183.035714 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80905.072962 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 92580.706733 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 519148 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 291431 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 639 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102138.754542 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69593.750000 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80963.510773 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 92591.249550 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 513996 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 285885 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 629 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 38391 # Transaction distribution -system.membus.trans_dist::ReadResp 216211 # Transaction distribution -system.membus.trans_dist::WriteReq 31027 # Transaction distribution -system.membus.trans_dist::WriteResp 31027 # Transaction distribution -system.membus.trans_dist::WritebackDirty 141592 # Transaction distribution -system.membus.trans_dist::CleanEvict 19995 # Transaction distribution -system.membus.trans_dist::UpgradeReq 63966 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 38983 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 38395 # Transaction distribution +system.membus.trans_dist::ReadResp 216403 # Transaction distribution +system.membus.trans_dist::WriteReq 31030 # Transaction distribution +system.membus.trans_dist::WriteResp 31030 # Transaction distribution +system.membus.trans_dist::WritebackDirty 140287 # Transaction distribution +system.membus.trans_dist::CleanEvict 19048 # Transaction distribution +system.membus.trans_dist::UpgradeReq 61128 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 38691 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 40431 # Transaction distribution -system.membus.trans_dist::ReadExResp 19912 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 177820 # Transaction distribution +system.membus.trans_dist::ReadExReq 40497 # Transaction distribution +system.membus.trans_dist::ReadExResp 19965 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 178008 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 4302 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::InvalidateResp 4238 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107932 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14192 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 659894 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 782044 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72955 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72955 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 854999 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 655043 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 777209 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72931 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72931 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 850140 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162812 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28384 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19597036 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19789560 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19529832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19722372 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22107704 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 127509 # Total snoops (count) -system.membus.snoopTraffic 37120 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 426843 # Request fanout histogram -system.membus.snoop_fanout::mean 0.011580 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.106987 # Request fanout histogram +system.membus.pkt_size::total 22040516 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 124379 # Total snoops (count) +system.membus.snoopTraffic 36224 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 423974 # Request fanout histogram +system.membus.snoop_fanout::mean 0.011487 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.106558 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 421900 98.84% 98.84% # Request fanout histogram -system.membus.snoop_fanout::1 4943 1.16% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 419104 98.85% 98.85% # Request fanout histogram +system.membus.snoop_fanout::1 4870 1.15% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 426843 # Request fanout histogram -system.membus.reqLayer0.occupancy 94581999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 423974 # Request fanout histogram +system.membus.reqLayer0.occupancy 95170998 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12496000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12519499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1014639485 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1006886251 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1151195264 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1152568025 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 6864902 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 6725047 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3081,78 +3067,78 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 1123711 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 579018 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 224775 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 30515 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 29083 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 1432 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 38394 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 569470 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31027 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31027 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 374544 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 155002 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 112494 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 44031 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 156525 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 34 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51717 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51717 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 531080 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4357 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 3099 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1346867 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 408809 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1755676 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 38391932 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7144124 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45536056 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 402215 # Total snoops (count) -system.toL2Bus.snoopTraffic 16179148 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 958128 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.409221 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.494721 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 1101165 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 567136 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 209084 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 30878 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 29463 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1415 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 38398 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 558656 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31030 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31030 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 370367 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 149733 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 109212 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 43837 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 153049 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 31 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 31 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51538 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51538 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 520262 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4298 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 3081 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1372035 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 353597 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1725632 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 39251474 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5647218 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 44898692 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 393768 # Total snoops (count) +system.toL2Bus.snoopTraffic 15844428 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 942231 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.393753 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.491645 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 567474 59.23% 59.23% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 389222 40.62% 99.85% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1432 0.15% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 572640 60.77% 60.77% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 368176 39.07% 99.85% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1415 0.15% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 958128 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 954442443 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 942231 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 939495440 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1977326 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1962409 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 723838248 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 733983819 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 286417681 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 257943151 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index a1ac44f79..9ef8eea73 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.854886 # Number of seconds simulated -sim_ticks 2854886132500 # Number of ticks simulated -final_tick 2854886132500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.854944 # Number of seconds simulated +sim_ticks 2854944380500 # Number of ticks simulated +final_tick 2854944380500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 259825 # Simulator instruction rate (inst/s) -host_op_rate 314145 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6635713455 # Simulator tick rate (ticks/s) -host_mem_usage 588360 # Number of bytes of host memory used -host_seconds 430.23 # Real time elapsed on the host -sim_insts 111784531 # Number of instructions simulated -sim_ops 135154718 # Number of ops (including micro ops) simulated +host_inst_rate 264512 # Simulator instruction rate (inst/s) +host_op_rate 319813 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6754449586 # Simulator tick rate (ticks/s) +host_mem_usage 588784 # Number of bytes of host memory used +host_seconds 422.68 # Real time elapsed on the host +sim_insts 111803105 # Number of instructions simulated +sim_ops 135177203 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 7232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1667840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9176172 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 6784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1665024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9168492 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10852268 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1667840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1667840 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7959296 # Number of bytes written to this memory +system.physmem.bytes_read::total 10841388 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1665024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1665024 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7956736 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7976820 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 113 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26060 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143899 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7974260 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 106 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26016 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143779 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170088 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124364 # Number of write requests responded to by this memory +system.physmem.num_reads::total 169918 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124324 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 128745 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2533 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 584205 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3214199 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 128705 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 583207 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3211443 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3801296 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 584205 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 584205 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2787956 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3797408 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 583207 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 583207 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2787002 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6138 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2794094 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2787956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2533 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 584205 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3220337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2793140 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2787002 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 583207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3217581 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6595390 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170088 # Number of read requests accepted -system.physmem.writeReqs 128745 # Number of write requests accepted -system.physmem.readBursts 170088 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 128745 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10876160 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue -system.physmem.bytesWritten 7989120 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10852268 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7976820 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6590548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 169918 # Number of read requests accepted +system.physmem.writeReqs 128705 # Number of write requests accepted +system.physmem.readBursts 169918 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 128705 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10866560 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue +system.physmem.bytesWritten 7986688 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10841388 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7974260 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10602 # Per bank write bursts -system.physmem.perBankRdBursts::1 10348 # Per bank write bursts -system.physmem.perBankRdBursts::2 10682 # Per bank write bursts -system.physmem.perBankRdBursts::3 10189 # Per bank write bursts -system.physmem.perBankRdBursts::4 13369 # Per bank write bursts -system.physmem.perBankRdBursts::5 10294 # Per bank write bursts -system.physmem.perBankRdBursts::6 10368 # Per bank write bursts -system.physmem.perBankRdBursts::7 10838 # Per bank write bursts -system.physmem.perBankRdBursts::8 10130 # Per bank write bursts -system.physmem.perBankRdBursts::9 10489 # Per bank write bursts -system.physmem.perBankRdBursts::10 10055 # Per bank write bursts -system.physmem.perBankRdBursts::11 9592 # Per bank write bursts -system.physmem.perBankRdBursts::12 10755 # Per bank write bursts -system.physmem.perBankRdBursts::13 11804 # Per bank write bursts -system.physmem.perBankRdBursts::14 10513 # Per bank write bursts -system.physmem.perBankRdBursts::15 9912 # Per bank write bursts -system.physmem.perBankWrBursts::0 7846 # Per bank write bursts -system.physmem.perBankWrBursts::1 7741 # Per bank write bursts -system.physmem.perBankWrBursts::2 8334 # Per bank write bursts -system.physmem.perBankWrBursts::3 7790 # Per bank write bursts -system.physmem.perBankWrBursts::4 7606 # Per bank write bursts -system.physmem.perBankWrBursts::5 7522 # Per bank write bursts -system.physmem.perBankWrBursts::6 7517 # Per bank write bursts -system.physmem.perBankWrBursts::7 7997 # Per bank write bursts -system.physmem.perBankWrBursts::8 7756 # Per bank write bursts -system.physmem.perBankWrBursts::9 7896 # Per bank write bursts -system.physmem.perBankWrBursts::10 7435 # Per bank write bursts -system.physmem.perBankWrBursts::11 7391 # Per bank write bursts -system.physmem.perBankWrBursts::12 8149 # Per bank write bursts -system.physmem.perBankWrBursts::13 8812 # Per bank write bursts -system.physmem.perBankWrBursts::14 7798 # Per bank write bursts -system.physmem.perBankWrBursts::15 7240 # Per bank write bursts +system.physmem.perBankRdBursts::0 10675 # Per bank write bursts +system.physmem.perBankRdBursts::1 10444 # Per bank write bursts +system.physmem.perBankRdBursts::2 10743 # Per bank write bursts +system.physmem.perBankRdBursts::3 10387 # Per bank write bursts +system.physmem.perBankRdBursts::4 13022 # Per bank write bursts +system.physmem.perBankRdBursts::5 10182 # Per bank write bursts +system.physmem.perBankRdBursts::6 10267 # Per bank write bursts +system.physmem.perBankRdBursts::7 10712 # Per bank write bursts +system.physmem.perBankRdBursts::8 10430 # Per bank write bursts +system.physmem.perBankRdBursts::9 10642 # Per bank write bursts +system.physmem.perBankRdBursts::10 10231 # Per bank write bursts +system.physmem.perBankRdBursts::11 9545 # Per bank write bursts +system.physmem.perBankRdBursts::12 10746 # Per bank write bursts +system.physmem.perBankRdBursts::13 11530 # Per bank write bursts +system.physmem.perBankRdBursts::14 10184 # Per bank write bursts +system.physmem.perBankRdBursts::15 10050 # Per bank write bursts +system.physmem.perBankWrBursts::0 7937 # Per bank write bursts +system.physmem.perBankWrBursts::1 7870 # Per bank write bursts +system.physmem.perBankWrBursts::2 8420 # Per bank write bursts +system.physmem.perBankWrBursts::3 7905 # Per bank write bursts +system.physmem.perBankWrBursts::4 7296 # Per bank write bursts +system.physmem.perBankWrBursts::5 7361 # Per bank write bursts +system.physmem.perBankWrBursts::6 7425 # Per bank write bursts +system.physmem.perBankWrBursts::7 7903 # Per bank write bursts +system.physmem.perBankWrBursts::8 7956 # Per bank write bursts +system.physmem.perBankWrBursts::9 8136 # Per bank write bursts +system.physmem.perBankWrBursts::10 7613 # Per bank write bursts +system.physmem.perBankWrBursts::11 7341 # Per bank write bursts +system.physmem.perBankWrBursts::12 8127 # Per bank write bursts +system.physmem.perBankWrBursts::13 8673 # Per bank write bursts +system.physmem.perBankWrBursts::14 7491 # Per bank write bursts +system.physmem.perBankWrBursts::15 7338 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 69 # Number of times write queue was full causing retry -system.physmem.totGap 2854885682000 # Total gap between requests +system.physmem.numWrRetry 64 # Number of times write queue was full causing retry +system.physmem.totGap 2854943930000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 543 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 169531 # Read request sizes (log2) +system.physmem.readPktSize::6 169361 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 124364 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 160094 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 124324 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 159846 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9630 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -160,121 +160,123 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7446 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 159 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 60347 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 312.612325 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 185.506399 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.136235 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21716 35.99% 35.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14599 24.19% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6802 11.27% 71.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3528 5.85% 77.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2551 4.23% 81.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1581 2.62% 84.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1111 1.84% 85.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1010 1.67% 87.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7449 12.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 60347 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6172 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.532242 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 583.546907 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6171 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 166 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 60346 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 312.418122 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 185.510807 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 328.995418 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21664 35.90% 35.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14701 24.36% 60.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6745 11.18% 71.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3562 5.90% 77.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2510 4.16% 81.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1679 2.78% 84.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1014 1.68% 85.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1006 1.67% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7465 12.37% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60346 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6177 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.486158 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 583.334644 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6176 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6172 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6172 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.225211 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.326492 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 15.268498 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5463 88.51% 88.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 63 1.02% 89.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 33 0.53% 90.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 41 0.66% 90.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 274 4.44% 95.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 26 0.42% 95.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 14 0.23% 95.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 8 0.13% 95.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 10 0.16% 96.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 4 0.06% 96.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.08% 96.26% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6177 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6177 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.202687 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.306581 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 15.265718 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5466 88.49% 88.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 67 1.08% 89.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 30 0.49% 90.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 47 0.76% 90.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 264 4.27% 95.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 28 0.45% 95.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 18 0.29% 95.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.10% 95.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 9 0.15% 96.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 7 0.11% 96.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.06% 96.26% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::60-63 7 0.11% 96.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 140 2.27% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.08% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.06% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 6 0.10% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 3 0.05% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.03% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.05% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 11 0.18% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.05% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.23% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 6 0.10% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 4 0.06% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 6 0.10% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.03% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 143 2.32% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.06% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 1 0.02% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 7 0.11% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 5 0.08% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 11 0.18% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 3 0.05% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.05% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.23% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 3 0.05% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 4 0.06% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.06% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 5 0.08% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.02% 99.89% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::188-191 2 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 3 0.05% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6172 # Writes before turning the bus around for reads -system.physmem.totQLat 4562123250 # Total ticks spent queuing -system.physmem.totMemAccLat 7748498250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 849700000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26845.49 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::192-195 4 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6177 # Writes before turning the bus around for reads +system.physmem.totQLat 4574555750 # Total ticks spent queuing +system.physmem.totMemAccLat 7758118250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 848950000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26942.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45595.49 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 45692.43 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.80 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s @@ -284,52 +286,52 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.21 # Average write queue length when enqueuing -system.physmem.readRowHits 140395 # Number of row buffer hits during reads -system.physmem.writeRowHits 94027 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.31 # Row buffer hit rate for writes -system.physmem.avgGap 9553448.52 # Average gap between requests -system.physmem.pageHitRate 79.52 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 217784280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 115755090 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 618966600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 325482660 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 6028389120.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4546972650 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 380659200 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 12537712590 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 8446773120 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 671876398965 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 705097688865 # Total energy per rank (pJ) -system.physmem_0.averagePower 246.979269 # Core power per rank (mW) -system.physmem_0.totalIdleTime 2843583812750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 720868250 # Time in different power states -system.physmem_0.memoryStateTime::REF 2563490000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 2794425375000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 21996678750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7684667500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 27495053000 # Time in different power states -system.physmem_1.actEnergy 213100440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 113261775 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 594405000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 326129940 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 6103375200.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4480349340 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 365416320 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 12364122510 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 8637319200 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 671971041390 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 705171178185 # Total energy per rank (pJ) -system.physmem_1.averagePower 247.005010 # Core power per rank (mW) -system.physmem_1.totalIdleTime 2844103138750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 682770250 # Time in different power states -system.physmem_1.memoryStateTime::REF 2596086000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 2794495958000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 22493040000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7504072000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 27114206250 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 25.37 # Average write queue length when enqueuing +system.physmem.readRowHits 140247 # Number of row buffer hits during reads +system.physmem.writeRowHits 93988 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.30 # Row buffer hit rate for writes +system.physmem.avgGap 9560361.83 # Average gap between requests +system.physmem.pageHitRate 79.51 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 217834260 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 115781655 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 617124480 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 324250740 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 6010564560.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4580096490 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 375795840 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 12507827490 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8401113600 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 671912403285 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 705065679060 # Total energy per rank (pJ) +system.physmem_0.averagePower 246.963017 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2843582682250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 706056250 # Time in different power states +system.physmem_0.memoryStateTime::REF 2555890000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2794607920750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 21877952250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7767045000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 27429516250 # Time in different power states +system.physmem_1.actEnergy 213043320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 113231415 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 595176120 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 327163500 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 6093540960.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4507043580 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 367350240 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 12209497470 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 8677272480 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 672029778480 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 705136507095 # Total energy per rank (pJ) +system.physmem_1.averagePower 246.987826 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2844096160000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 691055750 # Time in different power states +system.physmem_1.memoryStateTime::REF 2591938000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2794723975250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 22596980000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7565161250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 26775270250 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory @@ -342,30 +344,30 @@ system.realview.nvmem.bw_inst_read::cpu.inst 179 system.realview.nvmem.bw_inst_read::total 179 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 179 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 179 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 31050902 # Number of BP lookups -system.cpu.branchPred.condPredicted 16823011 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2467385 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18598277 # Number of BTB lookups -system.cpu.branchPred.BTBHits 10398347 # Number of BTB hits +system.cpu.branchPred.lookups 31068063 # Number of BP lookups +system.cpu.branchPred.condPredicted 16834819 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2474290 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18684214 # Number of BTB lookups +system.cpu.branchPred.BTBHits 10413110 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 55.910271 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7909634 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1502216 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3035557 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2846976 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 188581 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 109207 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 55.732128 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7904720 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1504932 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3038151 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2849063 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 189088 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 109706 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -395,57 +397,59 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 67916 # Table walker walks requested -system.cpu.dtb.walker.walksShort 67916 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 44853 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23063 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 67916 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 67916 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 67916 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7871 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 10132.638801 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 8470.700593 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 9365.136659 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 7864 99.91% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 6 0.08% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7871 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 67808 # Table walker walks requested +system.cpu.dtb.walker.walksShort 67808 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 44545 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23263 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 67808 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 67808 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 67808 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7897 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 10074.838546 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 8443.809763 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7240.808120 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 7014 88.82% 88.82% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 876 11.09% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::81920-98303 5 0.06% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::245760-262143 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7897 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples 276581000 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 276581000 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 276581000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6482 82.35% 82.35% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1389 17.65% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7871 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 67916 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 6507 82.40% 82.40% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1390 17.60% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7897 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 67808 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 67916 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7871 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 67808 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7897 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7871 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 75787 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7897 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 75705 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24685993 # DTB read hits -system.cpu.dtb.read_misses 61030 # DTB read misses -system.cpu.dtb.write_hits 19409907 # DTB write hits -system.cpu.dtb.write_misses 6886 # DTB write misses +system.cpu.dtb.read_hits 24693754 # DTB read hits +system.cpu.dtb.read_misses 60831 # DTB read misses +system.cpu.dtb.write_hits 19411318 # DTB write hits +system.cpu.dtb.write_misses 6977 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4276 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1444 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1826 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4277 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1491 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1775 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 755 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24747023 # DTB read accesses -system.cpu.dtb.write_accesses 19416793 # DTB write accesses +system.cpu.dtb.perms_faults 779 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24754585 # DTB read accesses +system.cpu.dtb.write_accesses 19418295 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44095900 # DTB hits -system.cpu.dtb.misses 67916 # DTB misses -system.cpu.dtb.accesses 44163816 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 44105072 # DTB hits +system.cpu.dtb.misses 67808 # DTB misses +system.cpu.dtb.accesses 44172880 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -475,39 +479,39 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 5836 # Table walker walks requested -system.cpu.itb.walker.walksShort 5836 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 323 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 5513 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 5836 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 5836 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 5836 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3199 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 10502.500781 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 8663.235820 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 6980.719897 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1845 57.67% 57.67% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 784 24.51% 82.18% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 564 17.63% 99.81% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::24576-32767 5 0.16% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 5860 # Table walker walks requested +system.cpu.itb.walker.walksShort 5860 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 319 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 5541 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 5860 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 5860 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 5860 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3216 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 10484.452736 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 8664.992606 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 6927.635793 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1845 57.37% 57.37% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 815 25.34% 82.71% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 549 17.07% 99.78% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::24576-32767 6 0.19% 99.97% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3199 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3216 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples 276141500 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 276141500 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total 276141500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2889 90.31% 90.31% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 310 9.69% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3199 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 2906 90.36% 90.36% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 310 9.64% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3216 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5836 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 5836 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5860 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 5860 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3199 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3199 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 9035 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 57468050 # ITB inst hits -system.cpu.itb.inst_misses 5836 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3216 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3216 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 9076 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 57505769 # ITB inst hits +system.cpu.itb.inst_misses 5860 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -516,45 +520,45 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2922 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2934 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8340 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8328 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57473886 # ITB inst accesses -system.cpu.itb.hits 57468050 # DTB hits -system.cpu.itb.misses 5836 # DTB misses -system.cpu.itb.accesses 57473886 # DTB accesses +system.cpu.itb.inst_accesses 57511629 # ITB inst accesses +system.cpu.itb.hits 57505769 # DTB hits +system.cpu.itb.misses 5860 # DTB misses +system.cpu.itb.accesses 57511629 # DTB accesses system.cpu.numPwrStateTransitions 6066 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 887944293.276624 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17437791477.805088 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 2968 97.86% 97.86% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 59 1.95% 99.80% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 887942089.664688 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17437807884.014717 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 2969 97.89% 97.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 58 1.91% 99.80% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 499966835544 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 499966671100 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 161751090992 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2693135041508 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 323505132 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 161816022547 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2693128357953 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 323634999 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 111784531 # Number of instructions committed -system.cpu.committedOps 135154718 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7776689 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 111803105 # Number of instructions committed +system.cpu.committedOps 135177203 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7783284 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 3033 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5386331427 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.894006 # CPI: cycles per instruction -system.cpu.ipc 0.345542 # IPC: instructions per cycle +system.cpu.quiesceCycles 5386318328 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.894687 # CPI: cycles per instruction +system.cpu.ipc 0.345460 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 2337 0.00% 0.00% # Class of committed instruction -system.cpu.op_class_0::IntAlu 90595549 67.03% 67.03% # Class of committed instruction -system.cpu.op_class_0::IntMult 113150 0.08% 67.12% # Class of committed instruction +system.cpu.op_class_0::IntAlu 90612203 67.03% 67.03% # Class of committed instruction +system.cpu.op_class_0::IntMult 113141 0.08% 67.12% # Class of committed instruction system.cpu.op_class_0::IntDiv 0 0.00% 67.12% # Class of committed instruction system.cpu.op_class_0::FloatAdd 0 0.00% 67.12% # Class of committed instruction system.cpu.op_class_0::FloatCmp 0 0.00% 67.12% # Class of committed instruction @@ -580,519 +584,519 @@ system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.12% # Cl system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.12% # Class of committed instruction system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.12% # Class of committed instruction system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 8471 0.01% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 8473 0.01% 67.12% # Class of committed instruction system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.12% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.12% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.12% # Class of committed instruction -system.cpu.op_class_0::MemRead 24195627 17.90% 85.02% # Class of committed instruction -system.cpu.op_class_0::MemWrite 20228352 14.97% 99.99% # Class of committed instruction +system.cpu.op_class_0::MemRead 24199534 17.90% 85.03% # Class of committed instruction +system.cpu.op_class_0::MemWrite 20230283 14.97% 99.99% # Class of committed instruction system.cpu.op_class_0::FloatMemRead 2708 0.00% 99.99% # Class of committed instruction system.cpu.op_class_0::FloatMemWrite 8524 0.01% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 135154718 # Class of committed instruction +system.cpu.op_class_0::total 135177203 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed -system.cpu.tickCycles 217865051 # Number of cycles that the object actually ticked -system.cpu.idleCycles 105640081 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 843791 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.945118 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42554576 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 844303 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.402019 # Average number of references to valid blocks. +system.cpu.tickCycles 217984467 # Number of cycles that the object actually ticked +system.cpu.idleCycles 105650532 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 844606 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.945154 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42562338 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 845118 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.362598 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 330588500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.945118 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.945154 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999893 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999893 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 364 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 175868835 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 175868835 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 23043762 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23043762 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18247268 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18247268 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 357174 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 357174 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443432 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443432 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460038 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460038 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41291030 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41291030 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41648204 # number of overall hits -system.cpu.dcache.overall_hits::total 41648204 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 465012 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 465012 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 548381 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 548381 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 168658 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 168658 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22398 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22398 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 175904316 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 175904316 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 23049763 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23049763 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18249075 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18249075 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 357182 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 357182 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443419 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443419 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460030 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460030 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41298838 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41298838 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41656020 # number of overall hits +system.cpu.dcache.overall_hits::total 41656020 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 464983 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 464983 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 548530 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 548530 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 169407 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 169407 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22402 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22402 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 1013393 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1013393 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1182051 # number of overall misses -system.cpu.dcache.overall_misses::total 1182051 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7327923000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7327923000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26756956980 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26756956980 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306920500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 306920500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 171000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 171000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34084879980 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34084879980 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34084879980 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34084879980 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23508774 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23508774 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 18795649 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18795649 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 525832 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 525832 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465830 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 465830 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460040 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460040 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42304423 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42304423 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42830255 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42830255 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.019780 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.019780 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029176 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029176 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.320745 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.320745 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048082 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048082 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 1013513 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1013513 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1182920 # number of overall misses +system.cpu.dcache.overall_misses::total 1182920 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7335235000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7335235000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26749219979 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26749219979 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 303724500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 303724500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 169000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 169000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34084454979 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34084454979 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34084454979 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34084454979 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23514746 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23514746 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 18797605 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18797605 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 526589 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 526589 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465821 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 465821 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460032 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460032 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42312351 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42312351 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42838940 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42838940 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.019774 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.019774 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029181 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029181 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.321706 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.321706 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048091 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048091 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023955 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023955 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.027599 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.027599 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15758.567521 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15758.567521 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48792.640482 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48792.640482 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13703.031521 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13703.031521 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 85500 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 85500 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33634.414270 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33634.414270 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28835.371723 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28835.371723 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.023953 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023953 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.027613 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.027613 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15775.275655 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15775.275655 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48765.281715 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48765.281715 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13557.918936 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13557.918936 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 84500 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 84500 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33630.012618 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33630.012618 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28813.829320 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28813.829320 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 813 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 21 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.571429 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.954545 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 701301 # number of writebacks -system.cpu.dcache.writebacks::total 701301 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45802 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 45802 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249489 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 249489 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14157 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14157 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 295291 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 295291 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 295291 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 295291 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 419210 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 419210 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298892 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 298892 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 120813 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 120813 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8241 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8241 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 701993 # number of writebacks +system.cpu.dcache.writebacks::total 701993 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45638 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 45638 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249404 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 249404 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14200 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14200 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 295042 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 295042 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 295042 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 295042 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 419345 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 419345 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299126 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 299126 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121262 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 121262 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8202 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8202 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 718102 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 718102 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 838915 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 838915 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 718471 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 718471 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 839733 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 839733 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31130 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 31130 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6438741500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6438741500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14235579000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14235579000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1652909500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1652909500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 122323000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 122323000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20674320500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 20674320500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22327230000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22327230000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6305432000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6305432000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6305432000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6305432000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017832 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017832 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015902 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015902 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.229756 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.229756 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017691 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017691 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6449852500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6449852500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14240256000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14240256000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1658671000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1658671000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 118600500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 118600500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 167000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 167000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20690108500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 20690108500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22348779500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22348779500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6305317500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6305317500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6305317500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6305317500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017833 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017833 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015913 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015913 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230278 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230278 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017608 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017608 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016975 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016975 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019587 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019587 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15359.226879 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15359.226879 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47627.835472 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47627.835472 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13681.553310 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13681.553310 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14843.222910 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14843.222910 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 84500 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 84500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28790.228268 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28790.228268 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26614.412664 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26614.412664 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202551.622229 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202551.622229 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107392.308478 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107392.308478 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 2889413 # number of replacements -system.cpu.icache.tags.tagsinuse 511.370681 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 54569461 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 2889925 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.882656 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 16116553500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.370681 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998771 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998771 # Average percentage of cache occupancy +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016980 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016980 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019602 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019602 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15380.778357 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15380.778357 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47606.212767 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47606.212767 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13678.407085 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13678.407085 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14459.948793 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14459.948793 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 83500 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 83500 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28797.416319 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28797.416319 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26614.149378 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26614.149378 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202547.944105 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202547.944105 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107390.358347 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107390.358347 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 2890432 # number of replacements +system.cpu.icache.tags.tagsinuse 511.371135 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 54606166 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2890944 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.888697 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 16096310500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.371135 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998772 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998772 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 193 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60349332 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60349332 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 54569461 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 54569461 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 54569461 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 54569461 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 54569461 # number of overall hits -system.cpu.icache.overall_hits::total 54569461 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 2889936 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 2889936 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 2889936 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 2889936 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 2889936 # number of overall misses -system.cpu.icache.overall_misses::total 2889936 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39799359500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39799359500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39799359500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39799359500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39799359500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39799359500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 57459397 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 57459397 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 57459397 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 57459397 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 57459397 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 57459397 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050295 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.050295 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.050295 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.050295 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.050295 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.050295 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13771.709650 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13771.709650 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13771.709650 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13771.709650 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13771.709650 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13771.709650 # average overall miss latency +system.cpu.icache.tags.tag_accesses 60388077 # Number of tag accesses +system.cpu.icache.tags.data_accesses 60388077 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 54606166 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 54606166 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 54606166 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 54606166 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 54606166 # number of overall hits +system.cpu.icache.overall_hits::total 54606166 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 2890956 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 2890956 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 2890956 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 2890956 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 2890956 # number of overall misses +system.cpu.icache.overall_misses::total 2890956 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 39801907000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 39801907000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 39801907000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 39801907000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 39801907000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 39801907000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 57497122 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 57497122 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 57497122 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 57497122 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 57497122 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 57497122 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050280 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.050280 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.050280 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.050280 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.050280 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.050280 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13767.731851 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13767.731851 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13767.731851 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13767.731851 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13767.731851 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13767.731851 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 2889413 # number of writebacks -system.cpu.icache.writebacks::total 2889413 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2889936 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 2889936 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 2889936 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 2889936 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 2889936 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 2889936 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 2890432 # number of writebacks +system.cpu.icache.writebacks::total 2890432 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2890956 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 2890956 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 2890956 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 2890956 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 2890956 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 2890956 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3119 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 3119 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3119 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 3119 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36909424500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36909424500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36909424500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36909424500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36909424500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36909424500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36910952000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 36910952000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36910952000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 36910952000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36910952000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 36910952000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 265216500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 265216500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 265216500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 265216500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050295 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050295 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050295 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.050295 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050295 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.050295 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12771.709996 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12771.709996 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12771.709996 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12771.709996 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12771.709996 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12771.709996 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050280 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050280 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050280 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.050280 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050280 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.050280 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12767.732197 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12767.732197 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12767.732197 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12767.732197 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12767.732197 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12767.732197 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 85032.542482 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 85032.542482 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 85032.542482 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 85032.542482 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 96873 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65145.709178 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 7314750 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 162275 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 45.076259 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 99924187000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 73.512854 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.023684 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 12110.922280 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 52961.250360 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001122 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.184798 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.808125 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994045 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 58 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65344 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 57 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4564 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60694 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000885 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 60034528 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 60034528 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 67803 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3361 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 71164 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 701301 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 701301 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 2838672 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 2838672 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 2815 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 2815 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 166503 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 166503 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2866935 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 2866935 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 533944 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 533944 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 67803 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3361 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 2866935 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 700447 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3638546 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 67803 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3361 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 2866935 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 700447 # number of overall hits -system.cpu.l2cache.overall_hits::total 3638546 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 113 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 114 # number of ReadReq misses +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 96713 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65145.108369 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 7318914 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 162108 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 45.148383 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 100163301000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 70.225039 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.032952 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 12109.105789 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 52965.744589 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001072 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.184770 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.808193 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994035 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 46 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65349 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 45 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4579 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60686 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000702 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997147 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 60066606 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 60066606 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 68164 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3376 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 71540 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 701993 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 701993 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 2839731 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 2839731 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 2785 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 2785 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 167030 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 167030 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2867992 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 2867992 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 534347 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 534347 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 68164 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 3376 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 2867992 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 701377 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 3640909 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 68164 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 3376 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 2867992 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 701377 # number of overall hits +system.cpu.l2cache.overall_hits::total 3640909 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 106 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 108 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 129573 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 129573 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 22965 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 22965 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14315 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 14315 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 113 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 22965 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143888 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 166967 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 113 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 22965 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143888 # number of overall misses -system.cpu.l2cache.overall_misses::total 166967 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 38662500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 89500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 38752000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 174000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 174000 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 166000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 166000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12000990500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12000990500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2404531500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 2404531500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1744805500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1744805500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 38662500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 89500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 2404531500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13745796000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16189079500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 38662500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 89500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2404531500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13745796000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16189079500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 67916 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3362 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 71278 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 701301 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 701301 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 2838672 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 2838672 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2821 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2821 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 129309 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 129309 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 22923 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 22923 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14458 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 14458 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 106 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 22923 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143767 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 166798 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 106 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 22923 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143767 # number of overall misses +system.cpu.l2cache.overall_misses::total 166798 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 35537000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 193500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 35730500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 172000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 172000 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 164000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 164000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12000174000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12000174000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2393515000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 2393515000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1752753500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1752753500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 35537000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 193500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 2393515000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13752927500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16182173000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 35537000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 193500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 2393515000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13752927500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16182173000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 68270 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3378 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 71648 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 701993 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 701993 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 2839731 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 2839731 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2791 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2791 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 296076 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 296076 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2889900 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 2889900 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 548259 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 548259 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 67916 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3362 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 2889900 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 844335 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 3805513 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 67916 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3362 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 2889900 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 844335 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 3805513 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001664 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000297 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001599 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.002127 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.002127 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 296339 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 296339 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2890915 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 2890915 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 548805 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 548805 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 68270 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 3378 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 2890915 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 845144 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 3807707 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 68270 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 3378 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 2890915 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 845144 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 3807707 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001553 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000592 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001507 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.002150 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.002150 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.437634 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.437634 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.007947 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.007947 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026110 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026110 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001664 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000297 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007947 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.170416 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.043875 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001664 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000297 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007947 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.170416 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.043875 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 342146.017699 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 339929.824561 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29000 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 83000 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 83000 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92619.531075 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92619.531075 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 104704.180274 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 104704.180274 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 121886.517639 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 121886.517639 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 342146.017699 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 104704.180274 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95531.218726 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 96959.755521 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 342146.017699 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 104704.180274 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95531.218726 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 96959.755521 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436355 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.436355 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.007929 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.007929 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026345 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026345 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001553 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000592 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007929 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.170109 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.043805 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001553 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000592 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007929 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.170109 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.043805 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 335254.716981 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 96750 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 330837.962963 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 28666.666667 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 28666.666667 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82000 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82000 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92802.310744 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92802.310744 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 104415.434280 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 104415.434280 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 121230.702725 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 121230.702725 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 335254.716981 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 96750 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 104415.434280 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95661.226151 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 97016.588928 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 335254.716981 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 96750 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 104415.434280 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95661.226151 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 97016.588928 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 88174 # number of writebacks -system.cpu.l2cache.writebacks::total 88174 # number of writebacks -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 144 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 144 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 144 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 157 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 144 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 157 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 113 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 114 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 88134 # number of writebacks +system.cpu.l2cache.writebacks::total 88134 # number of writebacks +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 15 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 15 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 143 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 143 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 143 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 158 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 143 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 158 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 106 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 108 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 129573 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 129573 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 22952 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 22952 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14171 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14171 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 113 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 22952 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143744 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 166810 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 113 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 22952 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143744 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 166810 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 129309 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 129309 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 22908 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 22908 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14315 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14315 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 106 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 22908 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143624 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166640 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 106 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 22908 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143624 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 166640 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3119 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31130 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34249 # number of ReadReq MSHR uncacheable @@ -1101,146 +1105,146 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3119 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61833 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 37532500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 79500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 37612000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 114000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 114000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 146000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 146000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10705260500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10705260500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2173786500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2173786500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1590255500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1590255500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 37532500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 79500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2173786500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12295516000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14506914500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 37532500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 79500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2173786500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12295516000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14506914500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 34477000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 173500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 34650500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 112000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 112000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 144000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 144000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10707084000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10707084000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2162492500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2162492500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1597831000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1597831000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 34477000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 173500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2162492500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12304915000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14502058000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 34477000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 173500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2162492500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12304915000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14502058000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 216819500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5916233500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6133053000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5916117000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6132936500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 216819500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5916233500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6133053000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001664 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000297 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001599 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.002127 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.002127 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5916117000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6132936500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001553 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000592 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001507 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.002150 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.002150 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437634 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437634 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007942 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007942 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025847 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.025847 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001664 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000297 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007942 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170245 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.043834 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001664 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000297 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007942 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170245 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.043834 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 332146.017699 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 329929.824561 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 73000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 73000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82619.531075 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82619.531075 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 94710.112409 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 94710.112409 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 112219.003599 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 112219.003599 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 332146.017699 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 94710.112409 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85537.594613 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86966.695642 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 332146.017699 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 94710.112409 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85537.594613 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86966.695642 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436355 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436355 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007924 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007924 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026084 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.026084 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001553 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000592 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007924 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.169940 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.043764 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001553 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000592 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007924 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.169940 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.043764 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 325254.716981 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 86750 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 320837.962963 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18666.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18666.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 72000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 72000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82802.310744 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82802.310744 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 94399.009080 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 94399.009080 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 111619.350332 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 111619.350332 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 325254.716981 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 86750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 94399.009080 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85674.504261 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87026.272204 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 325254.716981 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 86750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 94399.009080 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85674.504261 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87026.272204 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69515.710164 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190049.261163 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 179072.469269 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190045.518792 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 179069.067710 # average ReadReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69515.710164 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100763.591307 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 99187.375673 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 7501348 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3767098 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58079 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 189 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 189 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100761.607112 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 99185.491566 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 7504755 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3768676 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58052 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 184 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 184 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 136577 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3574918 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 136721 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3576628 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 789475 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2889413 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 151189 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2821 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 790127 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2890432 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 151192 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2791 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2823 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296076 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296076 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 2889936 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 548482 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 4413 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 16 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8675486 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2655698 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14711 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 158895 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11504790 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370075584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99113193 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 271664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 469473889 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 132758 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5779048 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 4002764 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.022319 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.147720 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2793 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 2890956 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 549028 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 4410 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 13 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8678540 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2658068 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14779 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 159341 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11510728 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370205760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99209257 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 273080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 469701609 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 132371 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5775904 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 4004544 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.022245 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.147479 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3913425 97.77% 97.77% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 89339 2.23% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3915463 97.78% 97.78% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 89081 2.22% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4002764 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7421735500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4004544 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7425335000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 289875 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 287877 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4340119421 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4341709800 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1313068534 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1314266535 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 11352493 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 11403994 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 91007942 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 91100441 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1291,29 +1295,29 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 46393500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46325500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 333000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 322500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 91000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 91500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 613000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 623000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 21500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 52000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 51500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) @@ -1323,34 +1327,34 @@ system.iobus.reqLayer19.occupancy 2500 # La system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6090000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6084500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 39095500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 39097500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187683346 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187729822 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.033754 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.033985 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 272028370000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.033754 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064610 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064610 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 272037045000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.033985 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064624 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064624 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328122 # Number of tag accesses system.iocache.tags.data_accesses 328122 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses system.iocache.ReadReq_misses::total 234 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -1359,14 +1363,14 @@ system.iocache.demand_misses::realview.ide 36458 # system.iocache.demand_misses::total 36458 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36458 # number of overall misses system.iocache.overall_misses::total 36458 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29456377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29456377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4371874969 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4371874969 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4401331346 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4401331346 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4401331346 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4401331346 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 37405377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 37405377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4361655445 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4361655445 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4399060822 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4399060822 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4399060822 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4399060822 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1383,14 +1387,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 125881.952991 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125881.952991 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120690.011291 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120690.011291 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120723.334961 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120723.334961 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120723.334961 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120723.334961 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 159852.038462 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 159852.038462 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120407.891039 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120407.891039 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120661.057162 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120661.057162 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120661.057162 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120661.057162 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1407,14 +1411,14 @@ system.iocache.demand_mshr_misses::realview.ide 36458 system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17756377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17756377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2558822831 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2558822831 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2576579208 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2576579208 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2576579208 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2576579208 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 25705377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 25705377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2548589823 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2548589823 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2574295200 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2574295200 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2574295200 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2574295200 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1423,91 +1427,91 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75881.952991 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75881.952991 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70638.881156 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70638.881156 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 70672.532997 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70672.532997 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 70672.532997 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70672.532997 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 336642 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 137901 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 539 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 109852.038462 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 109852.038462 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70356.388665 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70356.388665 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70609.885348 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70609.885348 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70609.885348 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70609.885348 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 336307 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 137733 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 538 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 34249 # Transaction distribution -system.membus.trans_dist::ReadResp 71720 # Transaction distribution +system.membus.trans_dist::ReadResp 71814 # Transaction distribution system.membus.trans_dist::WriteReq 27584 # Transaction distribution system.membus.trans_dist::WriteResp 27584 # Transaction distribution -system.membus.trans_dist::WritebackDirty 124364 # Transaction distribution -system.membus.trans_dist::CleanEvict 8933 # Transaction distribution +system.membus.trans_dist::WritebackDirty 124324 # Transaction distribution +system.membus.trans_dist::CleanEvict 8813 # Transaction distribution system.membus.trans_dist::UpgradeReq 128 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 129451 # Transaction distribution -system.membus.trans_dist::ReadExResp 129451 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 37471 # Transaction distribution +system.membus.trans_dist::ReadExReq 129187 # Transaction distribution +system.membus.trans_dist::ReadExResp 129187 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 37565 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 4363 # Transaction distribution +system.membus.trans_dist::InvalidateResp 4361 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446194 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 445694 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553262 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 626659 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 626159 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4148 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16511968 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16675753 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16498528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16662313 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18992873 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 4867 # Total snoops (count) +system.membus.pkt_size::total 18979433 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 4865 # Total snoops (count) system.membus.snoopTraffic 32128 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 265109 # Request fanout histogram -system.membus.snoop_fanout::mean 0.018562 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.134973 # Request fanout histogram +system.membus.snoop_fanout::samples 264939 # Request fanout histogram +system.membus.snoop_fanout::mean 0.018563 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.134975 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 260188 98.14% 98.14% # Request fanout histogram -system.membus.snoop_fanout::1 4921 1.86% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 260021 98.14% 98.14% # Request fanout histogram +system.membus.snoop_fanout::1 4918 1.86% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 265109 # Request fanout histogram -system.membus.reqLayer0.occupancy 92913500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 264939 # Request fanout histogram +system.membus.reqLayer0.occupancy 92843000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 8000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1698000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1694500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 904283412 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 903707925 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 988660500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 987836250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 5813415 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 5807414 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1539,28 +1543,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2854886132500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2854944380500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 2fb8c4409..27961363f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,167 +1,167 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.826654 # Number of seconds simulated -sim_ticks 2826653666000 # Number of ticks simulated -final_tick 2826653666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.826673 # Number of seconds simulated +sim_ticks 2826672558500 # Number of ticks simulated +final_tick 2826672558500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 170078 # Simulator instruction rate (inst/s) -host_op_rate 206349 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4004321035 # Simulator tick rate (ticks/s) -host_mem_usage 626896 # Number of bytes of host memory used -host_seconds 705.90 # Real time elapsed on the host -sim_insts 120058397 # Number of instructions simulated -sim_ops 145661611 # Number of ops (including micro ops) simulated +host_inst_rate 170041 # Simulator instruction rate (inst/s) +host_op_rate 206302 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4002646805 # Simulator tick rate (ticks/s) +host_mem_usage 627056 # Number of bytes of host memory used +host_seconds 706.20 # Real time elapsed on the host +sim_insts 120082757 # Number of instructions simulated +sim_ops 145690782 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 1664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1325840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1300840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8393920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 384 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1308688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1308456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8387648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 176672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 586900 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 432960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 193312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 594324 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 432320 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12220460 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1325840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 176672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1502512 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8774720 # Number of bytes written to this memory +system.physmem.bytes_read::total 12228268 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1308688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 193312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1502000 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8790464 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8792284 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 26 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 22967 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20846 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 131155 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 6 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8808028 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 22699 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20965 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 131057 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2828 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9191 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6765 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3088 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9307 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6755 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 193804 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 137105 # Number of write requests responded to by this memory +system.physmem.num_reads::total 193926 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 137351 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 141496 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 589 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 91 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 469049 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 460205 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2969561 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 136 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 141742 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 657 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 462978 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 462896 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2967322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 158 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 62502 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 207631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 153171 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 68389 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 210256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 152943 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4323296 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 469049 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 62502 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 531552 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3104278 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4326029 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 462978 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 68389 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 531367 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3109827 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6200 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3110492 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3104278 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 589 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 91 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 469049 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 466405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2969561 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3116041 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3109827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 462978 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 469096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2967322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 158 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 62502 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 207645 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 153171 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 68389 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 210270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 152943 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7433788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 193805 # Number of read requests accepted -system.physmem.writeReqs 141496 # Number of write requests accepted -system.physmem.readBursts 193805 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 141496 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12392576 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10880 # Total number of bytes read from write queue -system.physmem.bytesWritten 8805056 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12220524 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8792284 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 170 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 7442070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 193927 # Number of read requests accepted +system.physmem.writeReqs 141742 # Number of write requests accepted +system.physmem.readBursts 193927 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 141742 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12400768 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10496 # Total number of bytes read from write queue +system.physmem.bytesWritten 8820224 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12228332 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8808028 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 164 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11925 # Per bank write bursts -system.physmem.perBankRdBursts::1 11855 # Per bank write bursts -system.physmem.perBankRdBursts::2 12297 # Per bank write bursts -system.physmem.perBankRdBursts::3 12187 # Per bank write bursts -system.physmem.perBankRdBursts::4 14909 # Per bank write bursts -system.physmem.perBankRdBursts::5 12660 # Per bank write bursts -system.physmem.perBankRdBursts::6 12587 # Per bank write bursts -system.physmem.perBankRdBursts::7 12794 # Per bank write bursts -system.physmem.perBankRdBursts::8 12033 # Per bank write bursts -system.physmem.perBankRdBursts::9 12070 # Per bank write bursts -system.physmem.perBankRdBursts::10 11247 # Per bank write bursts -system.physmem.perBankRdBursts::11 10141 # Per bank write bursts -system.physmem.perBankRdBursts::12 11323 # Per bank write bursts -system.physmem.perBankRdBursts::13 11835 # Per bank write bursts -system.physmem.perBankRdBursts::14 11954 # Per bank write bursts -system.physmem.perBankRdBursts::15 11817 # Per bank write bursts -system.physmem.perBankWrBursts::0 8684 # Per bank write bursts -system.physmem.perBankWrBursts::1 8734 # Per bank write bursts -system.physmem.perBankWrBursts::2 9001 # Per bank write bursts -system.physmem.perBankWrBursts::3 8790 # Per bank write bursts -system.physmem.perBankWrBursts::4 8747 # Per bank write bursts -system.physmem.perBankWrBursts::5 9254 # Per bank write bursts -system.physmem.perBankWrBursts::6 9144 # Per bank write bursts -system.physmem.perBankWrBursts::7 9206 # Per bank write bursts -system.physmem.perBankWrBursts::8 8582 # Per bank write bursts -system.physmem.perBankWrBursts::9 8592 # Per bank write bursts -system.physmem.perBankWrBursts::10 8144 # Per bank write bursts -system.physmem.perBankWrBursts::11 7450 # Per bank write bursts -system.physmem.perBankWrBursts::12 8375 # Per bank write bursts -system.physmem.perBankWrBursts::13 8211 # Per bank write bursts -system.physmem.perBankWrBursts::14 8456 # Per bank write bursts -system.physmem.perBankWrBursts::15 8209 # Per bank write bursts +system.physmem.perBankRdBursts::0 11912 # Per bank write bursts +system.physmem.perBankRdBursts::1 11892 # Per bank write bursts +system.physmem.perBankRdBursts::2 12330 # Per bank write bursts +system.physmem.perBankRdBursts::3 12174 # Per bank write bursts +system.physmem.perBankRdBursts::4 14942 # Per bank write bursts +system.physmem.perBankRdBursts::5 12676 # Per bank write bursts +system.physmem.perBankRdBursts::6 12556 # Per bank write bursts +system.physmem.perBankRdBursts::7 12785 # Per bank write bursts +system.physmem.perBankRdBursts::8 12022 # Per bank write bursts +system.physmem.perBankRdBursts::9 12081 # Per bank write bursts +system.physmem.perBankRdBursts::10 11226 # Per bank write bursts +system.physmem.perBankRdBursts::11 10162 # Per bank write bursts +system.physmem.perBankRdBursts::12 11365 # Per bank write bursts +system.physmem.perBankRdBursts::13 11848 # Per bank write bursts +system.physmem.perBankRdBursts::14 11951 # Per bank write bursts +system.physmem.perBankRdBursts::15 11840 # Per bank write bursts +system.physmem.perBankWrBursts::0 8683 # Per bank write bursts +system.physmem.perBankWrBursts::1 8758 # Per bank write bursts +system.physmem.perBankWrBursts::2 9038 # Per bank write bursts +system.physmem.perBankWrBursts::3 8776 # Per bank write bursts +system.physmem.perBankWrBursts::4 8736 # Per bank write bursts +system.physmem.perBankWrBursts::5 9287 # Per bank write bursts +system.physmem.perBankWrBursts::6 9143 # Per bank write bursts +system.physmem.perBankWrBursts::7 9209 # Per bank write bursts +system.physmem.perBankWrBursts::8 8594 # Per bank write bursts +system.physmem.perBankWrBursts::9 8600 # Per bank write bursts +system.physmem.perBankWrBursts::10 8159 # Per bank write bursts +system.physmem.perBankWrBursts::11 7478 # Per bank write bursts +system.physmem.perBankWrBursts::12 8406 # Per bank write bursts +system.physmem.perBankWrBursts::13 8230 # Per bank write bursts +system.physmem.perBankWrBursts::14 8500 # Per bank write bursts +system.physmem.perBankWrBursts::15 8219 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 72 # Number of times write queue was full causing retry -system.physmem.totGap 2826653384500 # Total gap between requests +system.physmem.numWrRetry 60 # Number of times write queue was full causing retry +system.physmem.totGap 2826672288500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 551 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 3091 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 190135 # Read request sizes (log2) +system.physmem.readPktSize::6 190257 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 137105 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 58100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 70874 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15772 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12783 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8291 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6372 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4622 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1482 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 762 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 269 # What read queue length does an incoming req see +system.physmem.writePktSize::6 137351 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 58372 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 70356 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15687 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12836 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8377 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7582 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6463 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5422 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4671 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 747 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 270 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -189,165 +189,178 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 10301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 164 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 84669 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 250.358833 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 141.923887 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 307.724934 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 42961 50.74% 50.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17699 20.90% 71.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6074 7.17% 78.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3410 4.03% 82.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2753 3.25% 86.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1498 1.77% 87.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 998 1.18% 89.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 977 1.15% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8299 9.80% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 84669 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6797 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.488009 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 564.388330 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6795 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 10498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 187 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 84506 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 251.118169 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 142.721377 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 307.168687 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 42580 50.39% 50.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17667 20.91% 71.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6229 7.37% 78.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3460 4.09% 82.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2829 3.35% 86.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1565 1.85% 87.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 960 1.14% 89.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 994 1.18% 90.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8222 9.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 84506 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6824 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.393318 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 563.270042 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6822 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6797 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6797 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.241136 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.514528 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.610339 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 6111 89.91% 89.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 128 1.88% 91.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 273 4.02% 95.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 31 0.46% 96.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 13 0.19% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 14 0.21% 96.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 146 2.15% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 13 0.19% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 11 0.16% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 7 0.10% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 8 0.12% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 5 0.07% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 4 0.06% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 8 0.12% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 6 0.09% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 2 0.03% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 1 0.01% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 3 0.04% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 2 0.03% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 5 0.07% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 4 0.06% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-327 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6797 # Writes before turning the bus around for reads -system.physmem.totQLat 9919718835 # Total ticks spent queuing -system.physmem.totMemAccLat 13550356335 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 968170000 # Total ticks spent in databus transfers -system.physmem.avgQLat 51228.96 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6824 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6824 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.195780 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.530637 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.731147 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5748 84.23% 84.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 362 5.30% 89.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 98 1.44% 90.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 53 0.78% 91.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 250 3.66% 95.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 24 0.35% 95.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 17 0.25% 96.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 13 0.19% 96.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 6 0.09% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.12% 96.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 10 0.15% 96.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 144 2.11% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 13 0.19% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 7 0.10% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 6 0.09% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 7 0.10% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.06% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 7 0.10% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 5 0.07% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.03% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.03% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 5 0.07% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 9 0.13% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 5 0.07% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.04% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.04% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6824 # Writes before turning the bus around for reads +system.physmem.totQLat 10004432906 # Total ticks spent queuing +system.physmem.totMemAccLat 13637470406 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 968810000 # Total ticks spent in databus transfers +system.physmem.avgQLat 51632.32 # Average queueing delay per DRAM burst system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 69978.86 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 70382.22 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.39 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.11 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.33 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.07 # Average write queue length when enqueuing -system.physmem.readRowHits 161407 # Number of row buffer hits during reads -system.physmem.writeRowHits 85137 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 61.87 # Row buffer hit rate for writes -system.physmem.avgGap 8430196.70 # Average gap between requests -system.physmem.pageHitRate 74.43 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 316180620 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 168053985 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 722667960 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 373543200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4556326320.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4729873110 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 240133440 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 9128983770 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 6579538080 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 667569876735 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 694387365510 # Total energy per rank (pJ) -system.physmem_0.averagePower 245.657037 # Core power per rank (mW) -system.physmem_0.totalIdleTime 2815586462334 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 417040689 # Time in different power states -system.physmem_0.memoryStateTime::REF 1935564000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 2778497008500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 17134268560 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8650044977 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 20019739274 # Time in different power states -system.physmem_1.actEnergy 288356040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 153264870 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 659878800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 344619180 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4568619120.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4738351860 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 236664480 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 8828064240 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 6766632480 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 667633644195 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 694220207745 # Total energy per rank (pJ) -system.physmem_1.averagePower 245.597901 # Core power per rank (mW) -system.physmem_1.totalIdleTime 2815641624954 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 407791169 # Time in different power states -system.physmem_1.memoryStateTime::REF 1940956000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 2778660280000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 17621547350 # Time in different power states -system.physmem_1.memoryStateTime::ACT 8663293877 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 19359797604 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.32 # Average write queue length when enqueuing +system.physmem.readRowHits 161584 # Number of row buffer hits during reads +system.physmem.writeRowHits 85488 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.39 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.02 # Row buffer hit rate for writes +system.physmem.avgGap 8421010.84 # Average gap between requests +system.physmem.pageHitRate 74.51 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 316830360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 168399330 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 723046380 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 373908600 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4521291840.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4723358580 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 248942400 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 9096613470 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 6505168320 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 667621594905 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 694301661855 # Total energy per rank (pJ) +system.physmem_0.averagePower 245.625060 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2815660418258 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 439528927 # Time in different power states +system.physmem_0.memoryStateTime::REF 1920369500 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2778771385500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 16940567035 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8652241815 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 19948465723 # Time in different power states +system.physmem_1.actEnergy 286542480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 152300940 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 660414300 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 345490920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 4558170240.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4719582900 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 238189440 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 8751236790 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 6789483360 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 667674392880 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 694177600920 # Total energy per rank (pJ) +system.physmem_1.averagePower 245.581186 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2815698296531 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 410333187 # Time in different power states +system.physmem_1.memoryStateTime::REF 1936500000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2778826050750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 17681028809 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8627428782 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 19191216972 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory @@ -366,30 +379,30 @@ system.realview.nvmem.bw_inst_read::total 102 # I system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 53099847 # Number of BP lookups -system.cpu0.branchPred.condPredicted 24413538 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 933900 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 32114969 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 13973138 # Number of BTB hits +system.cpu0.branchPred.lookups 23882865 # Number of BP lookups +system.cpu0.branchPred.condPredicted 15636955 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 931558 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 14470894 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 9520533 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 43.509735 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 15469071 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 33231 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 10119740 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 9963994 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 155746 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 49057 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 65.790911 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3844072 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 34146 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 1359371 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 1203202 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 156169 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 49075 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -419,84 +432,83 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 65583 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 65583 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25222 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18949 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 21412 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 44171 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 487.310679 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 3087.040611 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-8191 42986 97.32% 97.32% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-16383 897 2.03% 99.35% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-24575 125 0.28% 99.63% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-32767 93 0.21% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-40959 33 0.07% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-49151 20 0.05% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::57344-65535 15 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 66298 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 66298 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25087 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 19168 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 22043 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 44255 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 493.831206 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 3088.958464 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-8191 43053 97.28% 97.28% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::8192-16383 899 2.03% 99.32% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-24575 141 0.32% 99.63% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-32767 95 0.21% 99.85% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-40959 32 0.07% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::40960-49151 18 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::49152-57343 1 0.00% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::57344-65535 14 0.03% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 44171 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 16005 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 11349.047173 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9735.111358 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7638.174811 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 14581 91.10% 91.10% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1176 7.35% 98.45% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 210 1.31% 99.76% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 16 0.10% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.01% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::114688-131071 7 0.04% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-147455 12 0.07% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 16005 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 82168586356 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.591771 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.502145 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 82111702356 99.93% 99.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 39388000 0.05% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 7963500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 4902500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 2427000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 777000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 938000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 463500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 24500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 82168586356 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5127 78.72% 78.72% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1386 21.28% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6513 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65583 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::total 44255 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 16149 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 11407.424608 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9685.730755 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 9901.207568 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 14668 90.83% 90.83% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1230 7.62% 98.45% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 211 1.31% 99.75% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 16 0.10% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.02% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::114688-131071 4 0.02% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-245759 17 0.11% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 16149 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 86482404152 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.594104 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.503301 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 86424292152 99.93% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 40499500 0.05% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 7958000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 4655000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 1502500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 969000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 1099000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 1428000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 1000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 86482404152 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5106 78.70% 78.70% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1382 21.30% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6488 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 66298 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65583 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6513 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 66298 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6488 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6513 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 72096 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6488 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 72786 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 23662283 # DTB read hits -system.cpu0.dtb.read_misses 55655 # DTB read misses -system.cpu0.dtb.write_hits 17589226 # DTB write hits -system.cpu0.dtb.write_misses 9928 # DTB write misses +system.cpu0.dtb.read_hits 17693188 # DTB read hits +system.cpu0.dtb.read_misses 55688 # DTB read misses +system.cpu0.dtb.write_hits 14580631 # DTB write hits +system.cpu0.dtb.write_misses 10610 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3427 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 148 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2234 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3435 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 159 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2213 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 915 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 23717938 # DTB read accesses -system.cpu0.dtb.write_accesses 17599154 # DTB write accesses +system.cpu0.dtb.perms_faults 845 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 17748876 # DTB read accesses +system.cpu0.dtb.write_accesses 14591241 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 41251509 # DTB hits -system.cpu0.dtb.misses 65583 # DTB misses -system.cpu0.dtb.accesses 41317092 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 32273819 # DTB hits +system.cpu0.dtb.misses 66298 # DTB misses +system.cpu0.dtb.accesses 32340117 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -526,61 +538,64 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 10907 # Table walker walks requested -system.cpu0.itb.walker.walksShort 10907 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3899 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5942 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 1066 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 9841 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 431.460217 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 2241.549622 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-4095 9464 96.17% 96.17% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::4096-8191 172 1.75% 97.92% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-12287 123 1.25% 99.17% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::12288-16383 49 0.50% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-20479 6 0.06% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::20480-24575 19 0.19% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::28672-32767 1 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 9841 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 3645 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12380.384088 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11386.423562 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5549.123195 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 601 16.49% 16.49% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 2727 74.81% 91.30% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 175 4.80% 96.10% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 87 2.39% 98.49% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 49 1.34% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 3 0.08% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-73727 1 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 11677 # Table walker walks requested +system.cpu0.itb.walker.walksShort 11677 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3850 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6772 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 1055 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 10622 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1021.559028 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 3971.298769 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-4095 9829 92.53% 92.53% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::4096-8191 232 2.18% 94.72% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-12287 234 2.20% 96.92% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::12288-16383 118 1.11% 98.03% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-20479 84 0.79% 98.82% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::20480-24575 68 0.64% 99.46% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-28671 21 0.20% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::28672-32767 17 0.16% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-36863 11 0.10% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::36864-40959 4 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::45056-49151 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::49152-53247 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 10622 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 3671 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12324.162354 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11375.149198 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5369.602272 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 593 16.15% 16.15% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 2793 76.08% 92.24% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 150 4.09% 96.32% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 91 2.48% 98.80% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 38 1.04% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.03% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 3 0.08% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.03% 99.97% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 3645 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 22038229712 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.837207 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.369334 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 3588883500 16.28% 16.28% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 18448211212 83.71% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 1065000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 70000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 22038229712 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2246 87.09% 87.09% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 333 12.91% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2579 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 3671 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 22057105212 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.847252 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.360404 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 3373925500 15.30% 15.30% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 18678889712 84.68% 99.98% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 3873000 0.02% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 379500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 37500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 22057105212 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2281 87.19% 87.19% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 335 12.81% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2616 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10907 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10907 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 11677 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 11677 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2579 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2579 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 13486 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 72758108 # ITB inst hits -system.cpu0.itb.inst_misses 10907 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2616 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2616 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 14293 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 37442886 # ITB inst hits +system.cpu0.itb.inst_misses 11677 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -589,1058 +604,1066 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2282 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2325 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1937 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 2439 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 72769015 # ITB inst accesses -system.cpu0.itb.hits 72758108 # DTB hits -system.cpu0.itb.misses 10907 # DTB misses -system.cpu0.itb.accesses 72769015 # DTB accesses +system.cpu0.itb.inst_accesses 37454563 # ITB inst accesses +system.cpu0.itb.hits 37442886 # DTB hits +system.cpu0.itb.misses 11677 # DTB misses +system.cpu0.itb.accesses 37454563 # DTB accesses system.cpu0.numPwrStateTransitions 3670 # Number of power state transitions system.cpu0.pwrStateClkGateDist::samples 1835 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1484523232.318801 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23903491534.812244 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1057 57.60% 57.60% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 773 42.13% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1504014886.326976 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 24031487578.448807 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1058 57.66% 57.66% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 770 41.96% 99.62% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 2 0.11% 99.73% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::max_value 499970835992 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::total 1835 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 102553534695 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2724100131305 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 205108250 # number of cpu cycles simulated +system.cpu0.pwrStateResidencyTicks::ON 66805242090 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2759867316410 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 133611951 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 20843459 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 195936196 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 53099847 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 39406203 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 175823444 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 5691288 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 148299 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 58157 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 416860 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 413792 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 98564 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 72757810 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 257476 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 5315 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 200648219 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.193498 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.306871 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 19303849 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 111829084 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 23882865 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 14567807 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 107369786 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2747392 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 153767 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 58387 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 435607 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 423633 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 97811 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 37442098 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 257331 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 6030 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 129216536 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.043099 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.255701 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 95712766 47.70% 47.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 30373277 15.14% 62.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 14586568 7.27% 70.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 59975608 29.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67189169 52.00% 52.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 21288743 16.48% 68.47% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 8719000 6.75% 75.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 32019624 24.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 200648219 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.258887 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.955282 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 25818393 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 108480918 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 58863420 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 4969304 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2516184 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 3061987 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 333558 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 154376244 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 3806825 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 2516184 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 34429607 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12873889 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 83899455 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 55085453 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 11843631 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 137696782 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 1037438 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 1493634 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 164344 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 57817 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 7635337 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 141807029 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 635200062 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 152788581 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 9462 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 130609661 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 11197357 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 2697375 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 2554361 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 22576827 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 24592847 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 19077592 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1691886 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2320615 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 134759616 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1714081 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 132897861 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 450666 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10595447 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 21697472 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 119702 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 200648219 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.662343 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 0.961216 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 129216536 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.178748 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.836969 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 19892285 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 62318410 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 41002144 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 4961574 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1042123 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 8668351 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 335752 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 109935605 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 3778741 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1042123 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 25542587 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12841185 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 37729185 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 40176897 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 11884559 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 104971930 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 1005936 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1490559 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 163297 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 57296 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 7681326 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 109147487 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 479167735 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 120008007 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 9453 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 98091135 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 11056341 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1226764 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1083940 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12369905 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 18622381 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 16045587 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1690063 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2196173 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 102089116 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1690972 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 100270845 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 450536 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9007472 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 21276029 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 120459 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 129216536 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.775991 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.026149 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 123885975 61.74% 61.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 33618455 16.75% 78.50% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 31280513 15.59% 94.09% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 10734778 5.35% 99.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1128444 0.56% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 54 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 73187499 56.64% 56.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 23243158 17.99% 74.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 22432715 17.36% 91.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 9250445 7.16% 99.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1102673 0.85% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 46 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 200648219 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 129216536 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 10806493 43.96% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 67 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMisc 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5620315 22.86% 66.82% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 8146085 33.14% 99.96% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMemRead 2848 0.01% 99.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMemWrite 7137 0.03% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 9305182 40.57% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 67 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMisc 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5565388 24.27% 64.84% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 8055351 35.12% 99.96% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemRead 2851 0.01% 99.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemWrite 6938 0.03% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 89788621 67.56% 67.56% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 110178 0.08% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 2 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 8088 0.01% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.65% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 24348007 18.32% 85.97% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 18629393 14.02% 99.99% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMemRead 3106 0.00% 99.99% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMemWrite 8193 0.01% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 66163298 65.98% 65.99% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 92264 0.09% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 8058 0.01% 66.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.09% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.09% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 18375460 18.33% 84.41% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 15618206 15.58% 99.99% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemRead 3108 0.00% 99.99% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemWrite 8177 0.01% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 132897861 # Type of FU issued -system.cpu0.iq.rate 0.647940 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 24582945 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.184976 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 491444928 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 147076893 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 129373990 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 32623 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 11320 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 9717 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 157457242 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 21291 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 367347 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 100270845 # Type of FU issued +system.cpu0.iq.rate 0.750463 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 22935777 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.228738 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 353112143 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 112794988 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 98251090 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 32395 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 11310 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 9716 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 123183269 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 21080 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 364715 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1915298 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2464 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 19139 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 903377 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1893331 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2466 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 18814 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 881018 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 121005 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 360360 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 109546 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 360879 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2516184 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1671558 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 251575 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 136626375 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 1042123 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1649895 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 244572 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 103932598 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 24592847 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 19077592 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 875905 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 27780 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 199746 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 19139 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 262593 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 398520 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 661113 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 131868425 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 23910267 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 963966 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 18622381 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 16045587 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 874828 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 27967 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 192686 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 18814 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 252890 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 404204 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 657094 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 99256545 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 17939836 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 948116 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 152678 # number of nop insts executed -system.cpu0.iew.exec_refs 42387378 # number of memory reference insts executed -system.cpu0.iew.exec_branches 25593933 # Number of branches executed -system.cpu0.iew.exec_stores 18477111 # Number of stores executed -system.cpu0.iew.exec_rate 0.642921 # Inst execution rate -system.cpu0.iew.wb_sent 131315181 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 129383707 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 66018205 # num instructions producing a value -system.cpu0.iew.wb_consumers 106739719 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.630807 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.618497 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 9567606 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1594379 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 604440 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 197485844 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.638022 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.337140 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 152510 # number of nop insts executed +system.cpu0.iew.exec_refs 33405569 # number of memory reference insts executed +system.cpu0.iew.exec_branches 16813883 # Number of branches executed +system.cpu0.iew.exec_stores 15465733 # Number of stores executed +system.cpu0.iew.exec_rate 0.742872 # Inst execution rate +system.cpu0.iew.wb_sent 98711091 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 98260806 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 51187228 # num instructions producing a value +system.cpu0.iew.wb_consumers 84552650 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.735419 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.605389 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 8010093 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1570513 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 599985 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 127532122 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.744084 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.464109 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 137054336 69.40% 69.40% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 33455560 16.94% 86.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 12646051 6.40% 92.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 3243439 1.64% 94.39% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 4914257 2.49% 96.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 2777569 1.41% 98.28% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1312207 0.66% 98.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 555201 0.28% 99.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1527224 0.77% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 83238506 65.27% 65.27% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 24683933 19.36% 84.62% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 8242078 6.46% 91.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3223359 2.53% 93.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 3451127 2.71% 96.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 1466865 1.15% 97.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1171264 0.92% 98.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 549844 0.43% 98.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1505146 1.18% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 197485844 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 104056922 # Number of instructions committed -system.cpu0.commit.committedOps 126000293 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 127532122 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 78880347 # Number of instructions committed +system.cpu0.commit.committedOps 94894659 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 40851763 # Number of memory references committed -system.cpu0.commit.loads 22677548 # Number of loads committed -system.cpu0.commit.membars 647714 # Number of memory barriers committed -system.cpu0.commit.branches 24989662 # Number of branches committed +system.cpu0.commit.refs 31893618 # Number of memory references committed +system.cpu0.commit.loads 16729049 # Number of loads committed +system.cpu0.commit.membars 646523 # Number of memory barriers committed +system.cpu0.commit.branches 16211772 # Number of branches committed system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 109983283 # Number of committed integer instructions. -system.cpu0.commit.function_calls 4835482 # Number of function calls committed. +system.cpu0.commit.int_insts 81832780 # Number of committed integer instructions. +system.cpu0.commit.function_calls 1927003 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 85032586 67.49% 67.49% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 107857 0.09% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 8087 0.01% 67.58% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.58% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.58% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.58% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 22675292 18.00% 85.57% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 18166767 14.42% 99.99% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 62903043 66.29% 66.29% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 89941 0.09% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 8057 0.01% 66.39% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.39% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.39% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.39% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 16726793 17.63% 84.02% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 15157121 15.97% 99.99% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMemRead 2256 0.00% 99.99% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMemWrite 7448 0.01% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 126000293 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1527224 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 308240127 # The number of ROB reads -system.cpu0.rob.rob_writes 274288918 # The number of ROB writes -system.cpu0.timesIdled 136024 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 4460031 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5448199500 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 103934870 # Number of Instructions Simulated -system.cpu0.committedOps 125878241 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.973431 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.973431 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.506732 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.506732 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 142861191 # number of integer regfile reads -system.cpu0.int_regfile_writes 81742978 # number of integer regfile writes -system.cpu0.fp_regfile_reads 8188 # number of floating regfile reads -system.cpu0.fp_regfile_writes 2265 # number of floating regfile writes -system.cpu0.cc_regfile_reads 465378109 # number of cc regfile reads -system.cpu0.cc_regfile_writes 49818068 # number of cc regfile writes -system.cpu0.misc_regfile_reads 399016543 # number of misc regfile reads -system.cpu0.misc_regfile_writes 1225433 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 712812 # number of replacements -system.cpu0.dcache.tags.tagsinuse 499.246418 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 37680999 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 713324 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 52.824522 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 94894659 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1505146 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 224742704 # The number of ROB reads +system.cpu0.rob.rob_writes 207484818 # The number of ROB writes +system.cpu0.timesIdled 136289 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 4395415 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5519733867 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 78758295 # Number of Instructions Simulated +system.cpu0.committedOps 94772607 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.696481 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.696481 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.589455 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.589455 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 110218064 # number of integer regfile reads +system.cpu0.int_regfile_writes 59484746 # number of integer regfile writes +system.cpu0.fp_regfile_reads 8170 # number of floating regfile reads +system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes +system.cpu0.cc_regfile_reads 349694687 # number of cc regfile reads +system.cpu0.cc_regfile_writes 40999571 # number of cc regfile writes +system.cpu0.misc_regfile_reads 254801117 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1223326 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 712506 # number of replacements +system.cpu0.dcache.tags.tagsinuse 498.213160 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 28740042 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 713018 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 40.307597 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 296154500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.246418 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.975091 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.975091 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 498.213160 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.973073 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.973073 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 347 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 81225267 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 81225267 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 21467047 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 21467047 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 14989931 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 14989931 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307917 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 307917 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363108 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 363108 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361279 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361279 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 36456978 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 36456978 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 36764895 # number of overall hits -system.cpu0.dcache.overall_hits::total 36764895 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 649306 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 649306 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1896144 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1896144 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 148546 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 148546 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25295 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 25295 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20257 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20257 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2545450 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2545450 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2693996 # number of overall misses -system.cpu0.dcache.overall_misses::total 2693996 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9384044500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 9384044500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32956196365 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 32956196365 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 411578000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 411578000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 478843500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 478843500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 432000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 432000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 42340240865 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 42340240865 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 42340240865 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 42340240865 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 22116353 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 22116353 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 16886075 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 16886075 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456463 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 456463 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388403 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 388403 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381536 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381536 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 39002428 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 39002428 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 39458891 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 39458891 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029359 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.029359 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.112290 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.112290 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.325428 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.325428 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065126 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065126 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053093 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053093 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.065264 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.065264 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.068273 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.068273 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14452.422279 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14452.422279 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17380.640060 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17380.640060 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16271.120775 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16271.120775 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23638.421286 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23638.421286 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 63341698 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63341698 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 15523802 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 15523802 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 11993925 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 11993925 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307586 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 307586 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 362517 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 362517 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360768 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 360768 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 27517727 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 27517727 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 27825313 # number of overall hits +system.cpu0.dcache.overall_hits::total 27825313 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 649486 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 649486 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1895154 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1895154 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 148364 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 148364 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25286 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 25286 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20247 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20247 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2544640 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2544640 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2693004 # number of overall misses +system.cpu0.dcache.overall_misses::total 2693004 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9367064500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 9367064500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 33076385872 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 33076385872 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 412133000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 412133000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 479472000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 479472000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 454500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 454500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 42443450372 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 42443450372 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 42443450372 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 42443450372 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16173288 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16173288 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 13889079 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 13889079 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 455950 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 455950 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387803 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 387803 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381015 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381015 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 30062367 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 30062367 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 30518317 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 30518317 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040158 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.040158 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136449 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.136449 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.325395 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.325395 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065203 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065203 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053140 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053140 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084645 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.084645 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088242 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.088242 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14422.273151 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14422.273151 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17453.138833 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17453.138833 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16298.861030 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16298.861030 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23681.137946 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23681.137946 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16633.695757 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16633.695757 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15716.519574 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15716.519574 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 757 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 4969613 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 42 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 201973 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.023810 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 24.605333 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 712815 # number of writebacks -system.cpu0.dcache.writebacks::total 712815 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 260774 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 260774 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1570443 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1570443 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18576 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18576 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1831217 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1831217 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1831217 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1831217 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 388532 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 388532 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325701 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 325701 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102377 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 102377 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6719 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6719 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20257 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20257 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 714233 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 714233 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 816610 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 816610 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32008 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32008 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28682 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28682 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60690 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60690 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5031436500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5031436500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6631878895 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6631878895 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1714108500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1714108500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 107735000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 107735000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 458598500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 458598500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 420000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 420000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11663315395 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11663315395 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13377423895 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13377423895 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6681974000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6681974000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6681974000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6681974000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017568 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017568 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019288 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019288 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224283 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224283 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017299 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017299 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053093 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053093 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018313 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.018313 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020695 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.020695 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12949.863846 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12949.863846 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20361.862245 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20361.862245 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16743.101478 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16743.101478 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16034.380116 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16034.380116 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22639.013674 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22639.013674 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16679.550102 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16679.550102 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15760.633988 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15760.633988 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 689 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 4988118 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 32 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 201830 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.531250 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 24.714453 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 712509 # number of writebacks +system.cpu0.dcache.writebacks::total 712509 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 261058 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 261058 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1569543 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1569543 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18570 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18570 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1830601 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1830601 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1830601 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1830601 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 388428 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 388428 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325611 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 325611 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102372 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 102372 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6716 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6716 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20247 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20247 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 714039 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 714039 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 816411 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 816411 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20577 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20577 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19269 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19269 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39846 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39846 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5013254500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5013254500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6647950897 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6647950897 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1709667500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1709667500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 108314000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 108314000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 459237000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 459237000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 442500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 442500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11661205397 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11661205397 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13370872897 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13370872897 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4595503500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4595503500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4595503500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4595503500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024017 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024017 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023444 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023444 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224525 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224525 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017318 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017318 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053140 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053140 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023752 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023752 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026752 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026752 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12906.521929 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12906.521929 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20416.849852 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20416.849852 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16700.538233 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16700.538233 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16127.754616 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16127.754616 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22681.730627 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22681.730627 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16329.846696 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16329.846696 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16381.655741 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16381.655741 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208759.497626 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208759.497626 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110100.082386 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110100.082386 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1249331 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.757700 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 71450204 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1249842 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 57.167389 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6584638000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.757700 # Average occupied blocks per requestor +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16331.328397 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16331.328397 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16377.624624 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16377.624624 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223332.045488 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223332.045488 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115331.614215 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115331.614215 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1246758 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.757641 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 36137139 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1247269 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 28.973011 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6586723000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.757641 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999527 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999527 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 125 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 126 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 146758301 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 146758301 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 71450207 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 71450207 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 71450207 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 71450207 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 71450207 # number of overall hits -system.cpu0.icache.overall_hits::total 71450207 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1303999 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1303999 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1303999 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1303999 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1303999 # number of overall misses -system.cpu0.icache.overall_misses::total 1303999 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14174791933 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14174791933 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14174791933 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14174791933 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14174791933 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14174791933 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 72754206 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 72754206 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 72754206 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 72754206 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 72754206 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 72754206 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017923 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.017923 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017923 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.017923 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017923 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.017923 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10870.247549 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10870.247549 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10870.247549 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10870.247549 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10870.247549 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10870.247549 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1760744 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 1640 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 114723 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 76124237 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 76124237 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 36137142 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 36137142 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 36137142 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 36137142 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 36137142 # number of overall hits +system.cpu0.icache.overall_hits::total 36137142 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1301318 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1301318 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1301318 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1301318 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1301318 # number of overall misses +system.cpu0.icache.overall_misses::total 1301318 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14070925518 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14070925518 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14070925518 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14070925518 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14070925518 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14070925518 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 37438460 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 37438460 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 37438460 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 37438460 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 37438460 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 37438460 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034759 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.034759 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034759 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.034759 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034759 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.034759 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10812.826318 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10812.826318 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10812.826318 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10812.826318 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10812.826318 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10812.826318 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1742114 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 1649 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 114160 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.347786 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 126.153846 # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1249331 # number of writebacks -system.cpu0.icache.writebacks::total 1249331 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54109 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 54109 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 54109 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 54109 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 54109 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 54109 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1249890 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1249890 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1249890 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1249890 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1249890 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1249890 # number of overall MSHR misses +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.260284 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 126.846154 # average number of cycles each access was blocked +system.cpu0.icache.writebacks::writebacks 1246758 # number of writebacks +system.cpu0.icache.writebacks::total 1246758 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54000 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 54000 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 54000 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 54000 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 54000 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 54000 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1247318 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1247318 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1247318 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1247318 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1247318 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1247318 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3008 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 3008 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3008 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 3008 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12814231927 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12814231927 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12814231927 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12814231927 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12814231927 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12814231927 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12734729518 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12734729518 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12734729518 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12734729518 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12734729518 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12734729518 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 287646998 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 287646998 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 287646998 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 287646998 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017180 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017180 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017180 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.017180 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017180 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.017180 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10252.287743 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10252.287743 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10252.287743 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10252.287743 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10252.287743 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10252.287743 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033316 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033316 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033316 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.033316 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033316 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.033316 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10209.689524 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10209.689524 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10209.689524 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10209.689524 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10209.689524 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10209.689524 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95627.326463 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95627.326463 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95627.326463 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95627.326463 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1846767 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1849379 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 2365 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1845705 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1848223 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 2284 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 236461 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 270933 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15649.129225 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1883932 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 286558 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.574348 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 235089 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 270085 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15641.965642 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1885208 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 285711 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.598304 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14546.798617 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.022626 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.137647 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1090.170335 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.887866 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000734 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.066539 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.955147 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 298 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15316 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 69 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 145 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 80 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 327 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1433 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7528 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4690 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1338 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.018188 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.934814 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 67601036 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 67601036 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 54858 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13069 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 67927 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 483646 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 483646 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 1447155 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 1447155 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 221212 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 221212 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1179291 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1179291 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 390010 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 390010 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 54858 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13069 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1179291 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 611222 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1858440 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 54858 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13069 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1179291 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 611222 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1858440 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 514 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 209 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 723 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55801 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 55801 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20257 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 20257 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 48873 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 48873 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 70560 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 70560 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 107498 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 107498 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 514 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 209 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 70560 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 156371 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 227654 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 514 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 209 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 70560 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 156371 # number of overall misses -system.cpu0.l2cache.overall_misses::total 227654 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 15837500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 5057000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 20894500 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 37580500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 37580500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 9656000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 9656000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 401500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 401500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 3379601499 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 3379601499 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3771387500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3771387500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3519117997 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3519117997 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 15837500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 5057000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3771387500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 6898719496 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 10691001496 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 15837500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 5057000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3771387500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 6898719496 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 10691001496 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 55372 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 13278 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 68650 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 483646 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 483646 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 1447155 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 1447155 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55802 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 55802 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20257 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 20257 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270085 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 270085 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1249851 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 1249851 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 497508 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 497508 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 55372 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 13278 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1249851 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 767593 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 2086094 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 55372 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 13278 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1249851 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 767593 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 2086094 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009283 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.015740 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.010532 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999982 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999982 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.tags.occ_blocks::writebacks 14498.888394 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.509265 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.944405 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1130.623578 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.884942 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000702 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000058 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.069008 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.954710 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 275 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15342 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 64 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 136 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 72 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 282 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1456 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7618 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4683 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1303 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.016785 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.936401 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 67537653 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 67537653 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 55283 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 14603 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 69886 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 482862 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 482862 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 1445066 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 1445066 # number of WritebackClean hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 220992 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 220992 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1177410 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 1177410 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 389847 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 389847 # number of ReadSharedReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 55283 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 14603 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1177410 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 610839 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1858135 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 55283 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 14603 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1177410 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 610839 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1858135 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 528 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 200 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 728 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55774 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 55774 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20246 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 20246 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 49029 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 49029 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 69866 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 69866 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 107548 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 107548 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 528 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 200 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 69866 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 156577 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 227171 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 528 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 200 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 69866 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 156577 # number of overall misses +system.cpu0.l2cache.overall_misses::total 227171 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 17967500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4680500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 22648000 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 38083500 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 38083500 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 9705500 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 9705500 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 424500 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 424500 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 3399006998 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 3399006998 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3707068000 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3707068000 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3498037999 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3498037999 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 17967500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4680500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3707068000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 6897044997 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 10626760997 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 17967500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4680500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3707068000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 6897044997 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 10626760997 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 55811 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 14803 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 70614 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 482862 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 482862 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 1445066 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 1445066 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55774 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 55774 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20246 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 20246 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270021 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 270021 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1247276 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 1247276 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 497395 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 497395 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 55811 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 14803 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1247276 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 767416 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 2085306 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 55811 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 14803 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1247276 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 767416 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 2085306 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.009461 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.013511 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.010310 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.180954 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.180954 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.056455 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.056455 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.216073 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.216073 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009283 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.015740 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.056455 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.203716 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.109129 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009283 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.015740 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.056455 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.203716 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.109129 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 30812.256809 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24196.172249 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 28899.723375 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 673.473594 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 673.473594 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 476.674730 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 476.674730 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 69150.686453 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 69150.686453 # average ReadExReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 53449.369331 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 53449.369331 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32736.590420 # average ReadSharedReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32736.590420 # average ReadSharedReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 30812.256809 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24196.172249 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 53449.369331 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 44117.640074 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 46961.623762 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 30812.256809 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24196.172249 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 53449.369331 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 44117.640074 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 46961.623762 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked +system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.181575 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.181575 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.056015 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.056015 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.216223 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.216223 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.009461 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.013511 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.056015 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.204031 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.108939 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.009461 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.013511 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.056015 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.204031 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.108939 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34029.356061 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23402.500000 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31109.890110 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 682.818159 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 682.818159 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 479.378643 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 479.378643 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 424500 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 424500 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 69326.459810 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 69326.459810 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 53059.685684 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 53059.685684 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32525.365409 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32525.365409 # average ReadSharedReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34029.356061 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23402.500000 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 53059.685684 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 44048.902438 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 46778.686527 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34029.356061 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23402.500000 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 53059.685684 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 44048.902438 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 46778.686527 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 192 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 28.714286 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 32 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.unused_prefetches 10601 # number of HardPF blocks evicted w/o reference -system.cpu0.l2cache.writebacks::writebacks 229825 # number of writebacks -system.cpu0.l2cache.writebacks::total 229825 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 3 # number of ReadReq MSHR hits +system.cpu0.l2cache.unused_prefetches 10583 # number of HardPF blocks evicted w/o reference +system.cpu0.l2cache.writebacks::writebacks 229428 # number of writebacks +system.cpu0.l2cache.writebacks::total 229428 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 2 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 2 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5836 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 5836 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 40 # number of ReadCleanReq MSHR hits -system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 40 # number of ReadCleanReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 788 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 788 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 3 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 40 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6624 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 6668 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 3 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 40 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6624 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 6668 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 513 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 206 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 719 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 262614 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 262614 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55801 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55801 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20257 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20257 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43037 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 43037 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 70520 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 70520 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 106710 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 106710 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 513 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 206 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 70520 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 149747 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 220986 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 513 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 206 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 70520 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 149747 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 262614 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 483600 # number of overall MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5884 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 5884 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 42 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 42 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 782 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 782 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 2 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 2 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 42 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6666 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 6712 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 2 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 2 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 42 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6666 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 6712 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 526 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 198 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 724 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 262267 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 262267 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55774 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55774 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20246 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20246 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43145 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 43145 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 69824 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 69824 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 106766 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 106766 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 526 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 198 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 69824 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 149911 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 220459 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 526 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 198 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 69824 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 149911 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 262267 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 482726 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3008 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32008 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 35016 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28682 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28682 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20577 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 23585 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19269 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19269 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3008 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60690 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 63698 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 12741500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3770500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 16512000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17165691219 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17165691219 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 965407999 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 965407999 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 305528000 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 305528000 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 329500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 329500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2246676499 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2246676499 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3346200500 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3346200500 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2833954497 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2833954497 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 12741500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3770500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3346200500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5080630996 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 8443343496 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 12741500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3770500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3346200500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5080630996 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17165691219 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 25609034715 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39846 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 42854 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 14785500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3455500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 18241000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17281059402 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 17281059402 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 963844000 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 963844000 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 306251499 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 306251499 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 352500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 352500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2242873000 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2242873000 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3286309500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3286309500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2812269499 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2812269499 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 14785500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3455500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3286309500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5055142499 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 8359692999 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 14785500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3455500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3286309500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5055142499 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17281059402 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 25640752401 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 265086000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6425579500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6690665500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4430574500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4695660500 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 265086000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6425579500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6690665500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009265 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.015514 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.010473 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4430574500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4695660500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009425 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013376 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.010253 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159346 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159346 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056423 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056423 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.214489 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.214489 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009265 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.015514 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056423 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.195086 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.105933 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009265 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.015514 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056423 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.195086 # mshr miss rate for overall accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159784 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159784 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.055981 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.055981 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.214650 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.214650 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009425 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.013376 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.055981 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.195345 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.105720 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009425 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.013376 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.055981 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.195345 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231821 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24837.231969 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18303.398058 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22965.229485 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65364.722441 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65364.722441 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17300.908568 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17300.908568 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15082.588735 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15082.588735 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 52203.371494 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 52203.371494 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47450.375780 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47450.375780 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26557.534411 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26557.534411 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24837.231969 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18303.398058 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47450.375780 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33928.098700 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38207.594581 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24837.231969 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18303.398058 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47450.375780 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33928.098700 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65364.722441 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52954.993207 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231489 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28109.315589 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17452.020202 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25194.751381 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65891.093435 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65891.093435 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17281.242156 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17281.242156 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15126.518769 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15126.518769 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 352500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 352500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 51984.540503 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 51984.540503 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47065.614975 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47065.614975 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26340.496965 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26340.496965 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28109.315589 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17452.020202 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47065.614975 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33720.957762 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37919.490694 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28109.315589 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17452.020202 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47065.614975 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33720.957762 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65891.093435 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 53116.576279 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200749.172082 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 191074.523075 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215316.834330 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 199095.208819 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88126.994681 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105875.424287 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 105037.293165 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 4075722 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2058160 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 32446 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 214641 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 212781 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1860 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 113949 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1910077 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28682 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28682 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 713807 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1478497 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 89121 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 330731 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 87625 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42853 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 113662 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111192.453446 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109573.447053 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 4070347 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2055545 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 32650 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 214495 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 212607 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1888 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 104418 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1897981 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 19269 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19269 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 712665 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1476401 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 88407 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 330099 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 87722 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42827 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 113743 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 288564 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284982 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1249890 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 587175 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3237 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 288516 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284937 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1247318 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 587795 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3260 # Transaction distribution system.cpu0.toL2Bus.trans_dist::InvalidateResp 16 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3755087 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2622795 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29061 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 118492 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6525435 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 159995712 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99013924 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53112 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 221488 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 259284236 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 927446 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 18848064 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 3052004 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.088140 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.285640 # Request fanout histogram +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3747367 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2580614 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 32197 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119234 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6479412 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 159666240 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98907572 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 59212 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 223244 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 258856268 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 926807 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 18833272 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 3029449 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.088921 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.286812 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2784861 91.25% 91.25% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 265283 8.69% 99.94% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 1860 0.06% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2761954 91.17% 91.17% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 265607 8.77% 99.94% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 1888 0.06% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3052004 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 4075635489 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3029449 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 4055747992 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 114371967 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 114619003 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1878285609 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1874463037 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1237556949 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1221112489 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 15793479 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 17401984 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 63149938 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 63454935 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 4617850 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2715513 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 269466 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2413279 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1525969 # Number of BTB hits +system.cpu1.branchPred.lookups 33856624 # Number of BP lookups +system.cpu1.branchPred.condPredicted 11500186 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 284574 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 18698220 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5965214 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 63.232183 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 876806 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7196 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 247807 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 212871 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 34936 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 10588 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 31.902577 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 12503434 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7767 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 9010077 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 8973983 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 36094 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 10763 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1670,95 +1693,95 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 21585 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 21585 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8697 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5905 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 6983 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 14602 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 620.599918 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 3321.361869 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-4095 13932 95.41% 95.41% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::4096-8191 194 1.33% 96.74% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::8192-12287 228 1.56% 98.30% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::12288-16383 109 0.75% 99.05% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-20479 24 0.16% 99.21% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::20480-24575 26 0.18% 99.39% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-28671 9 0.06% 99.45% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::28672-32767 64 0.44% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-36863 7 0.05% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::36864-40959 6 0.04% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 14602 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5436 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11628.403238 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9929.194928 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 8303.343609 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 1858 34.18% 34.18% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2915 53.62% 87.80% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 446 8.20% 96.01% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 133 2.45% 98.45% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 34 0.63% 99.08% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 25 0.46% 99.54% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 6 0.11% 99.65% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.02% 99.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-106495 11 0.20% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::106496-114687 7 0.13% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5436 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 81885681356 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.177146 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.385706 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 67426452132 82.34% 82.34% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 14437765724 17.63% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2 12512000 0.02% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::3 4018500 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4 1336000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::5 984500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6 1256500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::7 435000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8 231000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::9 183500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10 98500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::11 31000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12 125000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::13 34000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14 29500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::15 188500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 81885681356 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1913 75.20% 75.20% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 631 24.80% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2544 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21585 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 21842 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 21842 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8830 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5887 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 7125 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 14717 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 626.588299 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 3443.893339 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-4095 14047 95.45% 95.45% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::4096-8191 191 1.30% 96.75% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::8192-12287 228 1.55% 98.29% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::12288-16383 115 0.78% 99.08% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-20479 21 0.14% 99.22% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::20480-24575 23 0.16% 99.37% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-28671 7 0.05% 99.42% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::28672-32767 61 0.41% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-36863 9 0.06% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::36864-40959 3 0.02% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::40960-45055 7 0.05% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::57344-61439 4 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 14717 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5501 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11163.061262 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9675.830911 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6263.258432 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 1953 35.50% 35.50% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2904 52.79% 88.29% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 452 8.22% 96.51% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 149 2.71% 99.22% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 15 0.27% 99.49% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 22 0.40% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 4 0.07% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5501 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 77610116560 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.192083 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.397646 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 62747643816 80.85% 80.85% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 14840857744 19.12% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2 12907000 0.02% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::3 3989500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4 1311000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::5 947500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6 1279000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::7 355000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8 209000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::9 144500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10 123000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::11 26500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12 158000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::13 24500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14 7000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::15 133500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 77610116560 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1910 75.26% 75.26% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 628 24.74% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2538 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21842 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21585 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2544 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21842 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2538 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2544 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 24129 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2538 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 24380 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4154069 # DTB read hits -system.cpu1.dtb.read_misses 18709 # DTB read misses -system.cpu1.dtb.write_hits 3480708 # DTB write hits -system.cpu1.dtb.write_misses 2876 # DTB write misses +system.cpu1.dtb.read_hits 10130559 # DTB read hits +system.cpu1.dtb.read_misses 18924 # DTB read misses +system.cpu1.dtb.write_hits 6492882 # DTB write hits +system.cpu1.dtb.write_misses 2918 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1944 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 52 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 415 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1948 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 62 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 418 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 381 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4172778 # DTB read accesses -system.cpu1.dtb.write_accesses 3483584 # DTB write accesses +system.cpu1.dtb.perms_faults 414 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10149483 # DTB read accesses +system.cpu1.dtb.write_accesses 6495800 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7634777 # DTB hits -system.cpu1.dtb.misses 21585 # DTB misses -system.cpu1.dtb.accesses 7656362 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 16623441 # DTB hits +system.cpu1.dtb.misses 21842 # DTB misses +system.cpu1.dtb.accesses 16645283 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1788,64 +1811,59 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 5903 # Table walker walks requested -system.cpu1.itb.walker.walksShort 5903 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2681 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2633 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 589 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 5314 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 359.427926 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 2179.481540 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-2047 5115 96.26% 96.26% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::2048-4095 44 0.83% 97.08% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::4096-6143 38 0.72% 97.80% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::6144-8191 21 0.40% 98.19% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-10239 22 0.41% 98.61% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::10240-12287 26 0.49% 99.10% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::12288-14335 16 0.30% 99.40% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::14336-16383 5 0.09% 99.49% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-18431 7 0.13% 99.62% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::18432-20479 3 0.06% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::20480-22527 3 0.06% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::22528-24575 4 0.08% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-26623 5 0.09% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::26624-28671 4 0.08% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::28672-30719 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 5314 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1751 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12219.588806 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11149.776616 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5813.276337 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-8191 298 17.02% 17.02% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-16383 1260 71.96% 88.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-24575 107 6.11% 95.09% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-32767 68 3.88% 98.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-40959 8 0.46% 99.43% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-49151 5 0.29% 99.71% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-57343 3 0.17% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::57344-65535 1 0.06% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 6562 # Table walker walks requested +system.cpu1.itb.walker.walksShort 6562 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2897 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 3033 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 632 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 5930 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 575.716695 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 2785.933852 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-4095 5654 95.35% 95.35% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::4096-8191 104 1.75% 97.10% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-12287 84 1.42% 98.52% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::12288-16383 46 0.78% 99.29% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-20479 13 0.22% 99.51% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::20480-24575 9 0.15% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-28671 14 0.24% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::28672-32767 3 0.05% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-36863 2 0.03% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::36864-40959 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 5930 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1787 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12039.171796 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10885.386949 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5807.969289 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 326 18.24% 18.24% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 1260 70.51% 88.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 112 6.27% 95.02% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-32767 73 4.09% 99.10% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-40959 5 0.28% 99.38% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-49151 6 0.34% 99.72% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-57343 4 0.22% 99.94% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1751 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 17441612916 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.860137 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.346964 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 2440154764 13.99% 13.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 15000736652 86.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 721500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 17441612916 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 992 85.37% 85.37% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 170 14.63% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1162 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 1787 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 17460932916 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.922072 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.268326 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1361890264 7.80% 7.80% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 16097906652 92.19% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 1078000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 58000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 17460932916 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 986 85.37% 85.37% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 169 14.63% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1155 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5903 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5903 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6562 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6562 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1162 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1162 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 7065 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 8146400 # ITB inst hits -system.cpu1.itb.inst_misses 5903 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1155 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1155 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 7717 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 43481037 # ITB inst hits +system.cpu1.itb.inst_misses 6562 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1854,928 +1872,936 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1127 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1123 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 570 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 565 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8152303 # ITB inst accesses -system.cpu1.itb.hits 8146400 # DTB hits -system.cpu1.itb.misses 5903 # DTB misses -system.cpu1.itb.accesses 8152303 # DTB accesses -system.cpu1.numPwrStateTransitions 5563 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2782 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1009807188.625809 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25701428342.991928 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1977 71.06% 71.06% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 799 28.72% 99.78% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 3 0.11% 99.89% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 43487599 # ITB inst accesses +system.cpu1.itb.hits 43481037 # DTB hits +system.cpu1.itb.misses 6562 # DTB misses +system.cpu1.itb.accesses 43487599 # DTB accesses +system.cpu1.numPwrStateTransitions 5583 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2792 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 993380119.566619 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25601801103.735863 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1979 70.88% 70.88% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 809 28.98% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 959983958132 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2782 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 17370067243 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2809283598757 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 34740953 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 959983178648 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2792 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 53155264670 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2773517293830 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 106311330 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 8935699 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 24503906 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4617850 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 2615646 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 23842655 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 779742 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 80208 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 31335 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 166914 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 295220 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 22708 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8145254 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 111581 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2082 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 33764610 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.884848 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.220160 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 10498191 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 108665043 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 33856624 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 27442631 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 92291638 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3748932 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 86712 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 30975 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 185919 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 298023 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 23349 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 43479865 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 112855 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2560 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 105289273 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.278878 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.339497 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 20042304 59.36% 59.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 4827845 14.30% 73.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1634677 4.84% 78.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 7259784 21.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 48625526 46.18% 46.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 13920511 13.22% 59.40% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7498101 7.12% 66.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 35245135 33.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 33764610 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.132922 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.705332 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 7349000 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 16390631 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 8692861 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1069281 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 262837 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 706015 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 129761 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 23185557 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 1033744 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 262837 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 8748161 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2379135 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11360118 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8342372 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 2671987 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 22035257 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 184232 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 261771 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 36717 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 15492 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1677749 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 21981180 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 102687971 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 25443797 # Number of integer rename lookups +system.cpu1.fetch.rateDist::total 105289273 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.318467 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.022140 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 13318727 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 62566078 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 26583147 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1076022 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1745299 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 4334852 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 132018 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 67655162 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1099039 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1745299 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17698509 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2385948 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 57515508 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 23258780 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 2685229 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 54782270 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 214949 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 261715 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 37045 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 16294 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1684754 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 54670319 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 258827504 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 58243055 # Number of integer rename lookups system.cpu1.rename.fp_rename_lookups 1689 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 19631101 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2350079 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 398085 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 327427 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2832658 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 4406260 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 3798525 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 616794 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 601017 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 21230855 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 553061 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 21048993 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 91520 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2000545 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 4635811 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 42283 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 33764610 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.623404 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.949604 # Number of insts issued each cycle +system.cpu1.rename.CommittedMaps 52176795 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 2493524 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1869295 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1798183 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 13052424 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 10386014 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6834101 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 620797 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 744232 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 53921335 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 577687 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 53701083 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 93984 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 3580846 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 5052182 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 42977 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 105289273 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.510034 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.848273 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 21364495 63.27% 63.27% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6105280 18.08% 81.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4197946 12.43% 93.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 1839743 5.45% 99.24% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 257138 0.76% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 72135914 68.51% 68.51% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 16498960 15.67% 84.18% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 13045494 12.39% 96.57% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3324500 3.16% 99.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 284390 0.27% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 15 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 33764610 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 105289273 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 1397917 29.28% 29.28% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 677 0.01% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMisc 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 29.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1598296 33.48% 62.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 1774858 37.18% 99.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMemRead 659 0.01% 99.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMemWrite 1349 0.03% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2891632 45.26% 45.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 674 0.01% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMisc 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1660257 25.99% 71.25% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 1834987 28.72% 99.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemRead 656 0.01% 99.98% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemWrite 1067 0.02% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 12978869 61.66% 61.66% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 28429 0.14% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 3301 0.02% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 4359753 20.71% 82.52% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 3676453 17.47% 99.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMemRead 718 0.00% 99.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMemWrite 1404 0.01% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 36615420 68.18% 68.18% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46378 0.09% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 3321 0.01% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 10339913 19.25% 87.53% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6693876 12.47% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemRead 720 0.00% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemWrite 1389 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 21048993 # Type of FU issued -system.cpu1.iq.rate 0.605884 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4773756 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.226793 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 80721609 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 23791762 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 20591914 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 6263 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 2082 # Number of floating instruction queue writes +system.cpu1.iq.FU_type_0::total 53701083 # Type of FU issued +system.cpu1.iq.rate 0.505130 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 6389273 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.118978 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 219168744 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 58087331 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 51738316 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 5952 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 2080 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 1787 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 25818553 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 4130 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 87577 # Number of loads that had data forwarded from stores +system.cpu1.iq.int_alu_accesses 60086458 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 3832 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 90387 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 404936 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 702 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 9416 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 250549 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 431562 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 735 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 9576 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 270603 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 40531 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 75671 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 51945 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 76138 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 262837 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 524383 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 105080 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 21825012 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 1745299 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 526771 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 105542 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 54540026 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 4406260 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 3798525 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 290384 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 7837 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 90528 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 9416 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 33554 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 119405 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 152959 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 20820702 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 4265911 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 206727 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 10386014 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6834101 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 292206 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 7827 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 90888 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 9576 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 43509 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 122774 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 166283 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 53458422 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 10243364 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 220834 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 41096 # number of nop insts executed -system.cpu1.iew.exec_refs 7893380 # number of memory reference insts executed -system.cpu1.iew.exec_branches 3012609 # Number of branches executed -system.cpu1.iew.exec_stores 3627469 # Number of stores executed -system.cpu1.iew.exec_rate 0.599313 # Inst execution rate -system.cpu1.iew.wb_sent 20691409 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 20593701 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 10296891 # num instructions producing a value -system.cpu1.iew.wb_consumers 16154886 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.592779 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.637386 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 1790740 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 510778 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 142432 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 33360276 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.594007 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.352197 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 41004 # number of nop insts executed +system.cpu1.iew.exec_refs 16887479 # number of memory reference insts executed +system.cpu1.iew.exec_branches 11797622 # Number of branches executed +system.cpu1.iew.exec_stores 6644115 # Number of stores executed +system.cpu1.iew.exec_rate 0.502848 # Inst execution rate +system.cpu1.iew.wb_sent 53318700 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 51740103 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 25143993 # num instructions producing a value +system.cpu1.iew.wb_consumers 38375917 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.486685 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.655202 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 3338971 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 534710 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 155407 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 103400366 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.492755 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.151487 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 23884731 71.60% 71.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 5569703 16.70% 88.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1678289 5.03% 93.32% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 665043 1.99% 95.32% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 510124 1.53% 96.85% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 336609 1.01% 97.85% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 218533 0.66% 98.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 117875 0.35% 98.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 379369 1.14% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 77772385 75.21% 75.21% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 14344116 13.87% 89.09% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6076791 5.88% 94.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 698306 0.68% 95.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1980317 1.92% 97.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 1651720 1.60% 99.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 355943 0.34% 99.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 123415 0.12% 99.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 397373 0.38% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 33360276 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 16156383 # Number of instructions committed -system.cpu1.commit.committedOps 19816226 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 103400366 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 41357318 # Number of instructions committed +system.cpu1.commit.committedOps 50951031 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 7549300 # Number of memory references committed -system.cpu1.commit.loads 4001324 # Number of loads committed -system.cpu1.commit.membars 208499 # Number of memory barriers committed -system.cpu1.commit.branches 2862007 # Number of branches committed +system.cpu1.commit.refs 16517950 # Number of memory references committed +system.cpu1.commit.loads 9954452 # Number of loads committed +system.cpu1.commit.membars 209769 # Number of memory barriers committed +system.cpu1.commit.branches 11645067 # Number of branches committed system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 17632180 # Number of committed integer instructions. -system.cpu1.commit.function_calls 461985 # Number of function calls committed. +system.cpu1.commit.int_insts 45808028 # Number of committed integer instructions. +system.cpu1.commit.function_calls 3371132 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 12236255 61.75% 61.75% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 27370 0.14% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 3301 0.02% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.90% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 4000808 20.19% 82.09% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 3546708 17.90% 99.99% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMemRead 516 0.00% 99.99% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMemWrite 1268 0.01% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 34384478 67.49% 67.49% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 45282 0.09% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 3321 0.01% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 9953936 19.54% 87.12% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 6562230 12.88% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemRead 516 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemWrite 1268 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 19816226 # Class of committed instruction -system.cpu1.commit.bw_lim_events 379369 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 53607539 # The number of ROB reads -system.cpu1.rob.rob_writes 43609460 # The number of ROB writes -system.cpu1.timesIdled 58654 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 976343 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5617999605 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 16123527 # Number of Instructions Simulated -system.cpu1.committedOps 19783370 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 2.154675 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.154675 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.464107 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.464107 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 23404305 # number of integer regfile reads -system.cpu1.int_regfile_writes 13364979 # number of integer regfile writes -system.cpu1.fp_regfile_reads 1400 # number of floating regfile reads +system.cpu1.commit.op_class_0::total 50951031 # Class of committed instruction +system.cpu1.commit.bw_lim_events 397373 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 137214928 # The number of ROB reads +system.cpu1.rob.rob_writes 110460111 # The number of ROB writes +system.cpu1.timesIdled 59286 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1022057 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5546467999 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 41324462 # Number of Instructions Simulated +system.cpu1.committedOps 50918175 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.572600 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.572600 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.388712 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.388712 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 56077052 # number of integer regfile reads +system.cpu1.int_regfile_writes 35632532 # number of integer regfile writes +system.cpu1.fp_regfile_reads 1385 # number of floating regfile reads system.cpu1.fp_regfile_writes 516 # number of floating regfile writes -system.cpu1.cc_regfile_reads 74742517 # number of cc regfile reads -system.cpu1.cc_regfile_writes 6682824 # number of cc regfile writes -system.cpu1.misc_regfile_reads 68400417 # number of misc regfile reads -system.cpu1.misc_regfile_writes 381677 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 186538 # number of replacements -system.cpu1.dcache.tags.tagsinuse 471.297864 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 6754124 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 186882 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 36.141116 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 89307598000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.297864 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920504 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.920504 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 344 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 325 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.671875 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 14996504 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 14996504 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 3592307 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3592307 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2912324 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2912324 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49253 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 49253 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78431 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 78431 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70573 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 70573 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 6504631 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6504631 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6553884 # number of overall hits -system.cpu1.dcache.overall_hits::total 6553884 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 213962 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 213962 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 393973 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 393973 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30075 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30075 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18449 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 18449 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23608 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23608 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 607935 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 607935 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 638010 # number of overall misses -system.cpu1.dcache.overall_misses::total 638010 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3561244000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3561244000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10027675956 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 10027675956 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 364257500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 364257500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 554259000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 554259000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 434000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 434000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 13588919956 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 13588919956 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 13588919956 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 13588919956 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3806269 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3806269 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3306297 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3306297 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79328 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 79328 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96880 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96880 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94181 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 94181 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 7112566 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 7112566 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 7191894 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 7191894 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.056213 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.056213 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.119158 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.119158 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.379122 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.379122 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.190431 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.190431 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.250666 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250666 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085473 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.085473 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.088712 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.088712 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16644.282630 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16644.282630 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25452.698423 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 25452.698423 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19744.024066 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19744.024066 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23477.592342 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23477.592342 # average StoreCondReq miss latency +system.cpu1.cc_regfile_reads 190521590 # number of cc regfile reads +system.cpu1.cc_regfile_writes 15513949 # number of cc regfile writes +system.cpu1.misc_regfile_reads 212156067 # number of misc regfile reads +system.cpu1.misc_regfile_writes 383841 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 187625 # number of replacements +system.cpu1.dcache.tags.tagsinuse 471.246001 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 15706444 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 187980 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 83.553804 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 89314291000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.246001 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920402 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.920402 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.693359 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 32901851 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 32901851 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 9540637 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 9540637 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 5911714 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 5911714 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49749 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 49749 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78973 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 78973 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71099 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71099 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 15452351 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 15452351 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 15502100 # number of overall hits +system.cpu1.dcache.overall_hits::total 15502100 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 214896 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 214896 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 395681 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 395681 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30189 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30189 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18483 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 18483 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23644 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23644 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 610577 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 610577 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 640766 # number of overall misses +system.cpu1.dcache.overall_misses::total 640766 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3583570500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3583570500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10071608465 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 10071608465 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 363005500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 363005500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 554928000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 554928000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 408500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 408500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 13655178965 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 13655178965 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 13655178965 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 13655178965 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9755533 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9755533 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6307395 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6307395 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79938 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 79938 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97456 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 97456 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94743 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 94743 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 16062928 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 16062928 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 16142866 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 16142866 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022028 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.022028 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.062733 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.062733 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377655 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377655 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.189655 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.189655 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.249559 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.249559 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038012 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.038012 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039693 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.039693 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16675.836218 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16675.836218 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25453.859207 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 25453.859207 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19639.966456 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19639.966456 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23470.140416 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23470.140416 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22352.586964 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 22352.586964 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21298.913741 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 21298.913741 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 300 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1464130 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 31 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 39463 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.677419 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 37.101335 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 186538 # number of writebacks -system.cpu1.dcache.writebacks::total 186538 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 78472 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 78472 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 304164 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 304164 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13133 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13133 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 382636 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 382636 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 382636 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 382636 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 135490 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 135490 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 89809 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 89809 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28779 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 28779 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5316 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5316 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23608 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23608 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 225299 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 225299 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 254078 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 254078 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2880 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2880 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2230 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2230 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5110 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5110 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1973019500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1973019500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2438757966 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2438757966 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 489881500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 489881500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 95317000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 95317000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 530661000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 530661000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 424000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 424000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4411777466 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4411777466 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4901658966 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4901658966 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 386538000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 386538000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 386538000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 386538000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035597 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035597 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027163 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027163 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.362785 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.362785 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054872 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054872 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.250666 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250666 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031676 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031676 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035328 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035328 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14562.104214 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14562.104214 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27154.939549 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27154.939549 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17022.186316 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17022.186316 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17930.210685 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17930.210685 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22478.015927 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22478.015927 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22364.384779 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 22364.384779 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21310.710876 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 21310.710876 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 381 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1471779 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 29 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 39630 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13.137931 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 37.138002 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 187625 # number of writebacks +system.cpu1.dcache.writebacks::total 187625 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 78547 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 78547 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 305511 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 305511 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13157 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13157 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 384058 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 384058 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 384058 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 384058 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 136349 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 136349 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90170 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 90170 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28879 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 28879 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5326 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5326 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23644 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23644 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 226519 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 226519 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 255398 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 255398 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14314 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14314 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11648 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11648 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 25962 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 25962 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1988454500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1988454500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2445262471 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2445262471 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 492196500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 492196500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 93636000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 93636000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 531294000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 531294000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 398500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 398500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4433716971 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4433716971 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4925913471 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4925913471 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2472670000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2472670000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2472670000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2472670000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013977 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013977 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014296 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014296 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.361267 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.361267 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054650 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054650 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.249559 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.249559 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014102 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.014102 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015821 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.015821 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14583.564969 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14583.564969 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27118.359443 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27118.359443 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17043.405243 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17043.405243 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17580.923770 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17580.923770 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22470.563356 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22470.563356 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19581.877709 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19581.877709 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19291.945647 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19291.945647 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134214.583333 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 134214.583333 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 75643.444227 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 75643.444227 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 594968 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.436901 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 7527273 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 595480 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 12.640681 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 79132209500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.436901 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975463 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.975463 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19573.267457 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19573.267457 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19287.204563 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19287.204563 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172744.865167 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172744.865167 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95241.891996 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95241.891996 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 599092 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.435973 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 42856272 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 599604 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 71.474293 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 79139515500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.435973 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975461 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975461 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 494 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 16885432 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 16885432 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 7527273 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7527273 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7527273 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7527273 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7527273 # number of overall hits -system.cpu1.icache.overall_hits::total 7527273 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 617701 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 617701 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 617701 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 617701 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 617701 # number of overall misses -system.cpu1.icache.overall_misses::total 617701 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5784933521 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5784933521 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5784933521 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5784933521 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5784933521 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5784933521 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8144974 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8144974 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8144974 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8144974 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8144974 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8144974 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.075838 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.075838 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.075838 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.075838 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.075838 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.075838 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9365.264944 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9365.264944 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9365.264944 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9365.264944 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9365.264944 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9365.264944 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 523604 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 40 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 42411 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 87558770 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 87558770 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 42856272 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 42856272 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 42856272 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 42856272 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 42856272 # number of overall hits +system.cpu1.icache.overall_hits::total 42856272 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 623309 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 623309 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 623309 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 623309 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 623309 # number of overall misses +system.cpu1.icache.overall_misses::total 623309 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5905173986 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5905173986 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5905173986 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5905173986 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5905173986 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5905173986 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 43479581 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 43479581 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 43479581 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 43479581 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 43479581 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 43479581 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014336 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014336 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014336 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014336 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014336 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014336 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9473.910991 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9473.910991 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9473.910991 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9473.910991 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9473.910991 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9473.910991 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 533657 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 290 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 42078 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.345948 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 40 # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 594968 # number of writebacks -system.cpu1.icache.writebacks::total 594968 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22217 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 22217 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 22217 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 22217 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 22217 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 22217 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 595484 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 595484 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 595484 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 595484 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 595484 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 595484 # number of overall MSHR misses +system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.682566 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 290 # average number of cycles each access was blocked +system.cpu1.icache.writebacks::writebacks 599092 # number of writebacks +system.cpu1.icache.writebacks::total 599092 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 23701 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 23701 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 23701 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 23701 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 23701 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 23701 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 599608 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 599608 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 599608 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 599608 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 599608 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 599608 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 101 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 101 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5318077800 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5318077800 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5318077800 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5318077800 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5318077800 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5318077800 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9663500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9663500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9663500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 9663500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.073111 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.073111 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.073111 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.073111 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.073111 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.073111 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8930.681261 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8930.681261 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8930.681261 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8930.681261 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8930.681261 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8930.681261 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95678.217822 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95678.217822 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95678.217822 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95678.217822 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 194116 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 194726 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 546 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5403181271 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5403181271 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5403181271 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5403181271 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5403181271 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5403181271 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9499999 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9499999 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9499999 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 9499999 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013791 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013791 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013791 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.013791 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013791 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.013791 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9011.189429 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9011.189429 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9011.189429 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9011.189429 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9011.189429 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9011.189429 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94059.396040 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 94059.396040 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94059.396040 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 94059.396040 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 194821 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 195463 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 575 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 59858 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 43575 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14594.735842 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 700816 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 57699 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 12.146068 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 59841 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 44456 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14684.761874 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 706823 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 58616 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 12.058534 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14193.075757 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 10.827460 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.968470 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 387.864155 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.866277 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000661 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000181 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.023673 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.890792 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 356 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 30 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13738 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 15 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 202 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 139 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1740 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8639 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3359 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.021729 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001831 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.838501 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 27539438 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 27539438 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 17059 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6202 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 23261 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 113931 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 113931 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 655101 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 655101 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27113 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 27113 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 571525 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 571525 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 98074 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 98074 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 17059 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 6202 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 571525 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 125187 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 719973 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 17059 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 6202 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 571525 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 125187 # number of overall hits -system.cpu1.l2cache.overall_hits::total 719973 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 502 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 304 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 806 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29460 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29460 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23607 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23607 # number of SCUpgradeReq misses +system.cpu1.l2cache.tags.occ_blocks::writebacks 14300.099102 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 10.020323 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.955758 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 371.686691 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.872809 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000612 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000180 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.022686 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.896287 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 332 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 32 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13796 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 10 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 205 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 117 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1791 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8656 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3349 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.020264 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001953 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.842041 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 27731086 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 27731086 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 17081 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7133 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 24214 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 114521 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 114521 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 659711 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 659711 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27226 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 27226 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 575115 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 575115 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 98702 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 98702 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 17081 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7133 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 575115 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 125928 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 725257 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 17081 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7133 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 575115 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 125928 # number of overall hits +system.cpu1.l2cache.overall_hits::total 725257 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 517 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 296 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 813 # number of ReadReq misses +system.cpu1.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses +system.cpu1.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29667 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 29667 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23643 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 23643 # number of SCUpgradeReq misses system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33905 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 33905 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 23957 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 23957 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 71492 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 71492 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 502 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 304 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 23957 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 105397 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 130160 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 502 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 304 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 23957 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 105397 # number of overall misses -system.cpu1.l2cache.overall_misses::total 130160 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10772500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6194000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 16966500 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 12496500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 12496500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 18899500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 18899500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 407499 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 407499 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1469375000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1469375000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 945511500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 945511500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1646741997 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1646741997 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10772500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6194000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 945511500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 3116116997 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 4078594997 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10772500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6194000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 945511500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3116116997 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 4078594997 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 17561 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 6506 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 24067 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 113931 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 113931 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 655101 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 655101 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29460 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 29460 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23607 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23607 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33950 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 33950 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 24491 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 24491 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 71832 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 71832 # number of ReadSharedReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 517 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 296 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 24491 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 105782 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 131086 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 517 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 296 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 24491 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 105782 # number of overall misses +system.cpu1.l2cache.overall_misses::total 131086 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 11135000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6028000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 17163000 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 12712500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 12712500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 18521500 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 18521500 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 382999 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 382999 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1470067999 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1470067999 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1003037500 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1003037500 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1657187499 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1657187499 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 11135000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6028000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1003037500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 3127255498 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 4147455998 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 11135000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6028000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1003037500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 3127255498 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 4147455998 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 17598 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7429 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 25027 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 114522 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 114522 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 659711 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 659711 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29667 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 29667 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23643 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23643 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61018 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 61018 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 595482 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 595482 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 169566 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 169566 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 17561 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 6506 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 595482 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 230584 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 850133 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 17561 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 6506 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 595482 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 230584 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 850133 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.028586 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.046726 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.033490 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61176 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 61176 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 599606 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 599606 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 170534 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 170534 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 17598 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7429 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 599606 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 231710 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 856343 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 17598 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7429 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 599606 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 231710 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 856343 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.029378 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.039844 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.032485 # miss rate for ReadReq accesses +system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000009 # miss rate for WritebackDirty accesses +system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000009 # miss rate for WritebackDirty accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.555656 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.555656 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.040231 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.040231 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.421618 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.421618 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.028586 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.046726 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.040231 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.457087 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.153105 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.028586 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.046726 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.040231 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.457087 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.153105 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21459.163347 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20375 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21050.248139 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 424.185336 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 424.185336 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 800.588808 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 800.588808 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 407499 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 407499 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43338.003244 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43338.003244 # average ReadExReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39467.024252 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39467.024252 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23033.933825 # average ReadSharedReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23033.933825 # average ReadSharedReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21459.163347 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20375 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39467.024252 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29565.518914 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 31335.241219 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21459.163347 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20375 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39467.024252 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29565.518914 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 31335.241219 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 117 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.554956 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.554956 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.040845 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.040845 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.421218 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.421218 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.029378 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.039844 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.040845 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.456528 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.153077 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.029378 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.039844 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.040845 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.456528 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.153077 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21537.717602 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20364.864865 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21110.701107 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 428.506421 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 428.506421 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 783.381974 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 783.381974 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 382999 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 382999 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43300.971988 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43300.971988 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 40955.350945 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 40955.350945 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23070.323797 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23070.323797 # average ReadSharedReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21537.717602 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20364.864865 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40955.350945 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29563.210168 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 31639.198679 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21537.717602 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20364.864865 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40955.350945 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29563.210168 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 31639.198679 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 182 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 23.400000 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 30.333333 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.unused_prefetches 799 # number of HardPF blocks evicted w/o reference -system.cpu1.l2cache.writebacks::writebacks 31397 # number of writebacks -system.cpu1.l2cache.writebacks::total 31397 # number of writebacks +system.cpu1.l2cache.unused_prefetches 827 # number of HardPF blocks evicted w/o reference +system.cpu1.l2cache.writebacks::writebacks 31720 # number of writebacks +system.cpu1.l2cache.writebacks::total 31720 # number of writebacks system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 2 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 430 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 430 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 426 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 426 # number of ReadExReq MSHR hits system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 7 # number of ReadCleanReq MSHR hits system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 7 # number of ReadCleanReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 65 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 65 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 74 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 74 # number of ReadSharedReq MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 2 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 495 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 505 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 500 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 509 # number of demand (read+write) MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 2 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 495 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 505 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 501 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 302 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 803 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25004 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 25004 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29460 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29460 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23607 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23607 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 500 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 509 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 516 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 295 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 811 # number of ReadReq MSHR misses +system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses +system.cpu1.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25186 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 25186 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29667 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29667 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23643 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23643 # number of SCUpgradeReq MSHR misses system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33475 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 33475 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 23950 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 23950 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 71427 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 71427 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 501 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 302 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 23950 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104902 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 129655 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 501 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 302 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 23950 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104902 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25004 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 154659 # number of overall MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33524 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 33524 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 24484 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 24484 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 71758 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 71758 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 516 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 295 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 24484 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 105282 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 130577 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 516 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 295 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 24484 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 105282 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25186 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 155763 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 2880 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 2981 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2230 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2230 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14314 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14415 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11648 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11648 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5110 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5211 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7748500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4342500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 12091000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1098165233 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1098165233 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 453245500 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 453245500 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 353298500 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 353298500 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 347499 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 347499 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1209651000 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1209651000 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 801689000 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 801689000 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1215836497 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1215836497 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7748500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4342500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 801689000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2425487497 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 3239267497 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7748500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4342500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 801689000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2425487497 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1098165233 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 4337432730 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8906000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 363460500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 372366500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8906000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 363460500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 372366500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028529 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.046419 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.033365 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 25962 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26063 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 8020500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4240500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 12261000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1092841786 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1092841786 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 456571000 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 456571000 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 353660000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 353660000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 322999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 322999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1211819000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1211819000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 855998500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 855998500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1224293499 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1224293499 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 8020500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4240500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 855998500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2436112499 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 3304371999 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 8020500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4240500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 855998500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2436112499 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1092841786 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4397213785 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8742000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2358114500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2366856500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8742000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2358114500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2366856500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.029322 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.039709 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.032405 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000009 # mshr miss rate for WritebackDirty accesses +system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000009 # mshr miss rate for WritebackDirty accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses @@ -2784,118 +2810,118 @@ system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.548609 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.548609 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.040220 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040220 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.421234 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.421234 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.028529 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046419 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.040220 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.454940 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.152511 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.028529 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046419 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.040220 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.454940 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.547993 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.547993 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.040833 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040833 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.420784 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.420784 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.029322 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.039709 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.040833 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.454370 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.152482 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.029322 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.039709 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.040833 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.454370 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181923 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15466.067864 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14379.139073 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15057.285181 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43919.582187 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43919.582187 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15385.115411 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15385.115411 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14965.836404 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14965.836404 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 347499 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 347499 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36135.952203 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36135.952203 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33473.444676 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33473.444676 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17022.085444 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17022.085444 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15466.067864 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14379.139073 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33473.444676 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23121.460954 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24983.745301 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15466.067864 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14379.139073 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33473.444676 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23121.460954 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43919.582187 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28045.136268 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88178.217822 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 126201.562500 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 124913.284133 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88178.217822 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 71127.299413 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 71457.781616 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 1670520 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 844468 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12481 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 115035 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 106284 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8751 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 31435 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 834833 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2230 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2230 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 146689 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 667575 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 29225 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 30255 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 73183 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41990 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85875 # Transaction distribution +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181893 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15543.604651 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14374.576271 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15118.372380 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43390.843564 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43390.843564 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15389.860788 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15389.860788 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14958.338620 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14958.338620 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 322999 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 322999 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36147.804558 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36147.804558 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34961.546316 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34961.546316 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17061.421709 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17061.421709 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15543.604651 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14374.576271 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34961.546316 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23138.926873 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25305.926764 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15543.604651 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14374.576271 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34961.546316 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23138.926873 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43390.843564 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28230.155974 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86554.455446 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164741.826184 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164193.999306 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86554.455446 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90829.462291 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90812.895676 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 1681326 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 850022 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12491 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 115149 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 106381 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8768 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 43982 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 852476 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11648 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11648 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 147635 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 672194 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 29901 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 30357 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 73327 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42065 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86118 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 68405 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 65523 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 595484 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 273707 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 370 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1786136 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 839744 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14453 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 38068 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2678401 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 76190416 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29457424 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 26024 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70244 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 105744108 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 346325 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 4857548 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 1179057 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.123952 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.351329 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadExReq 68535 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 65700 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 599608 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 274791 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 374 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1798508 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 885295 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 16392 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 38202 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2738397 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 76718288 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29683872 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29716 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70392 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 106502268 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 347702 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 4882288 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1207717 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.121214 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.347910 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1041662 88.35% 88.35% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 128644 10.91% 99.26% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 8751 0.74% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1070093 88.60% 88.60% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 128856 10.67% 99.27% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 8768 0.73% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1179057 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1629779992 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1207717 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1656031495 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80742792 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80775328 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 893427297 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 899618286 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 378082159 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 396030671 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 7957978 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 8974477 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 20520473 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 20614978 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 31012 # Transaction distribution system.iobus.trans_dist::ReadResp 31012 # Transaction distribution system.iobus.trans_dist::WriteReq 59420 # Transaction distribution @@ -2946,19 +2972,19 @@ system.iobus.pkt_size_system.bridge.master::total 162792 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484040 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40388000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 40387001 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 114000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 330000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 31500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 32000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 90000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 91000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 573500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 574500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2970,42 +2996,42 @@ system.iobus.reqLayer15.occupancy 12000 # La system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 53000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6114001 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6115000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33826000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 33791000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187862511 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187784301 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84716000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36458 # number of replacements -system.iocache.tags.tagsinuse 14.554422 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.554359 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 255374847000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.554422 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.909651 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.909651 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 255387586000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.554359 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.909647 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.909647 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328284 # Number of tag accesses system.iocache.tags.data_accesses 328284 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses system.iocache.ReadReq_misses::total 252 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -3014,14 +3040,14 @@ system.iocache.demand_misses::realview.ide 36476 # system.iocache.demand_misses::total 36476 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36476 # number of overall misses system.iocache.overall_misses::total 36476 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 39163375 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 39163375 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4357678136 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4357678136 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4396841511 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4396841511 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4396841511 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4396841511 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 40605876 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 40605876 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4346476425 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4346476425 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4387082301 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4387082301 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4387082301 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4387082301 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -3038,19 +3064,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 155410.218254 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 155410.218254 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120298.093419 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120298.093419 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120540.670879 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120540.670879 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120540.670879 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120540.670879 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 87 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 161134.428571 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 161134.428571 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119988.858906 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 119988.858906 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120273.119339 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120273.119339 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120273.119339 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120273.119339 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 191 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 21.750000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 63.666667 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks @@ -3062,14 +3088,14 @@ system.iocache.demand_mshr_misses::realview.ide 36476 system.iocache.demand_mshr_misses::total 36476 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36476 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36476 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 26563375 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 26563375 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2544616232 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2544616232 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2571179607 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2571179607 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2571179607 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2571179607 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 28005876 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 28005876 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2533401277 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2533401277 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2561407153 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2561407153 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2561407153 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2561407153 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -3078,621 +3104,622 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 105410.218254 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 105410.218254 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70246.693684 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70246.693684 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 70489.626247 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70489.626247 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 70489.626247 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70489.626247 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 137305 # number of replacements -system.l2c.tags.tagsinuse 65135.020938 # Cycle average of tags in use -system.l2c.tags.total_refs 548309 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 202660 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.705561 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 87489923000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 6043.335191 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.875782 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 1.068168 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8238.246856 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6901.068519 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37215.588563 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.685294 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909748 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1676.975803 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3036.574639 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2001.692374 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.092214 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000258 # Average percentage of cache occupancy +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 111134.428571 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 111134.428571 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69937.093557 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69937.093557 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70221.711619 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70221.711619 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70221.711619 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70221.711619 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 137443 # number of replacements +system.l2c.tags.tagsinuse 65137.298659 # Cycle average of tags in use +system.l2c.tags.total_refs 547823 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 202801 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.701284 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 87493786000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 6068.008119 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.951872 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.052619 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7988.261154 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6937.855049 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37116.430492 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 3.708460 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909745 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1897.444635 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3115.453147 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1993.223368 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.092590 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000228 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.125706 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.105302 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.567865 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.121891 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.105863 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.566352 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000057 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.025589 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.046334 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030543 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993882 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 33214 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 32119 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu1.inst 0.028953 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.047538 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030414 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993916 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 33259 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 25 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 32074 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::2 185 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 6015 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 27014 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5974 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 27100 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 133 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4859 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 27124 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.506805 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000336 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.490097 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6291007 # Number of tag accesses -system.l2c.tags.data_accesses 6291007 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 261222 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 261222 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 41572 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 4769 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 46341 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2758 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 2241 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 4999 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3976 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1584 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5560 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 265 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 106 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 50549 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 57222 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46457 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 49 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 18 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 21200 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 11593 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 4929 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 192388 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 265 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 106 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 50549 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 61198 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 46457 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 49 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 18 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 21200 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 13177 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 4929 # number of demand (read+write) hits -system.l2c.demand_hits::total 197948 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 265 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 106 # number of overall hits -system.l2c.overall_hits::cpu0.inst 50549 # number of overall hits -system.l2c.overall_hits::cpu0.data 61198 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 46457 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 49 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 18 # number of overall hits -system.l2c.overall_hits::cpu1.inst 21200 # number of overall hits -system.l2c.overall_hits::cpu1.data 13177 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 4929 # number of overall hits -system.l2c.overall_hits::total 197948 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 525 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 273 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 798 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 53 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 86 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 139 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11064 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8230 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19294 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 26 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 4 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 19971 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 9413 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 131312 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 6 # number of ReadSharedReq misses +system.l2c.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4863 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 27079 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.507492 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000381 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.489410 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6288814 # Number of tag accesses +system.l2c.tags.data_accesses 6288814 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 261149 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 261149 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 41513 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 4842 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 46355 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2681 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 2272 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 4953 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4003 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1563 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5566 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 282 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 80 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 50115 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 57309 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46378 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 44 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 17 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 21480 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 11675 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 4930 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 192310 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 282 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 80 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 50115 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 61312 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 46378 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 44 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 17 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 21480 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 13238 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 4930 # number of demand (read+write) hits +system.l2c.demand_hits::total 197876 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 282 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 80 # number of overall hits +system.l2c.overall_hits::cpu0.inst 50115 # number of overall hits +system.l2c.overall_hits::cpu0.data 61312 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 46378 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 44 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 17 # number of overall hits +system.l2c.overall_hits::cpu1.inst 21480 # number of overall hits +system.l2c.overall_hits::cpu1.data 13238 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 4930 # number of overall hits +system.l2c.overall_hits::total 197876 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 453 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 282 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 735 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 99 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 81 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 180 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 11239 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 8266 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 19505 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 29 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 19709 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 9351 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 131214 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 7 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 2746 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 945 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6765 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 171189 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 26 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 19971 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 20477 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 131312 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 6 # number of demand (read+write) misses +system.l2c.ReadSharedReq_misses::cpu1.inst 3001 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 1024 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6755 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 171094 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 29 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 19709 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 20590 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 131214 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 7 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2746 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 9175 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 6765 # number of demand (read+write) misses -system.l2c.demand_misses::total 190483 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 26 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu0.inst 19971 # number of overall misses -system.l2c.overall_misses::cpu0.data 20477 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 131312 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 6 # number of overall misses +system.l2c.demand_misses::cpu1.inst 3001 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 9290 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 6755 # number of demand (read+write) misses +system.l2c.demand_misses::total 190599 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 29 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses +system.l2c.overall_misses::cpu0.inst 19709 # number of overall misses +system.l2c.overall_misses::cpu0.data 20590 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 131214 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 7 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2746 # number of overall misses -system.l2c.overall_misses::cpu1.data 9175 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 6765 # number of overall misses -system.l2c.overall_misses::total 190483 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 10093000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 519000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 10612000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 709500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 365000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1074500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 1647098500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 779902000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2427000500 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 4012500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 353000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2097163000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 1106791000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 16321101734 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 538500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 90000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 295133500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 115926000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 986231086 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 20927340320 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 4012500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 353000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 2097163000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 2753889500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 16321101734 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 538500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 90000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 295133500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 895828000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 986231086 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 23354340820 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 4012500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 353000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 2097163000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 2753889500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 16321101734 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 538500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 90000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 295133500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 895828000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 986231086 # number of overall miss cycles -system.l2c.overall_miss_latency::total 23354340820 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 261222 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 261222 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 42097 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 5042 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 47139 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 2811 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 2327 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 5138 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 15040 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 9814 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 24854 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 291 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 110 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 70520 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 66635 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 177769 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 55 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 19 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 23946 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 12538 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11694 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 363577 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 291 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 110 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 70520 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 81675 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 177769 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 55 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 19 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 23946 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 22352 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11694 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 388431 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 291 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 110 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 70520 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 81675 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 177769 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 55 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 19 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 23946 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 22352 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11694 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 388431 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.012471 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.054145 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.016929 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.018855 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.036957 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.027053 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.735638 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.838598 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.776294 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.089347 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.036364 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.283196 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.141262 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.738666 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.109091 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.052632 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.114675 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.075371 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.578502 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.470847 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.089347 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.036364 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.283196 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.250713 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.738666 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.109091 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.052632 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.114675 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.410478 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.578502 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.490391 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.089347 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.036364 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.283196 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.250713 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.738666 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.109091 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.052632 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.114675 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.410478 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.578502 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.490391 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 19224.761905 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1901.098901 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 13298.245614 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 13386.792453 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4244.186047 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 7730.215827 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 148870.074114 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 94763.304982 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 125790.427076 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 154326.923077 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 88250 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 105010.415102 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 117581.111229 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 124292.537879 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89750 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 90000 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 107477.603787 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 122673.015873 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 145784.343829 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 122246.992038 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 154326.923077 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 105010.415102 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 134486.960981 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 124292.537879 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 90000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 107477.603787 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 97637.929155 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 145784.343829 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 122605.906144 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 154326.923077 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 105010.415102 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 134486.960981 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 124292.537879 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 90000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 107477.603787 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 97637.929155 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 145784.343829 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 122605.906144 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.overall_misses::cpu1.inst 3001 # number of overall misses +system.l2c.overall_misses::cpu1.data 9290 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 6755 # number of overall misses +system.l2c.overall_misses::total 190599 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 8930500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 709000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 9639500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 540000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 293500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 833500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 1649495000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 781758500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2431253500 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 5602000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 249000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2048083000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 1082250500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 16438409497 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 622500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 89500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 340295000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 119337000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 980449226 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 21015387223 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 5602000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 249000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 2048083000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 2731745500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 16438409497 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 622500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 89500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 340295000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 901095500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 980449226 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 23446640723 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 5602000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 249000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 2048083000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 2731745500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 16438409497 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 622500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 89500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 340295000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 901095500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 980449226 # number of overall miss cycles +system.l2c.overall_miss_latency::total 23446640723 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 261149 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 261149 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 41966 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5124 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 47090 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 2780 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 2353 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 5133 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 15242 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 9829 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 25071 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 311 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 83 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 69824 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 66660 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 177592 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 51 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 18 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 24481 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 12699 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11685 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 363404 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 311 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 83 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 69824 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 81902 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 177592 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 51 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 18 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 24481 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 22528 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11685 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 388475 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 311 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 83 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 69824 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 81902 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 177592 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 51 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 18 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 24481 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 22528 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11685 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 388475 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.010794 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.055035 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.015608 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.035612 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.034424 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.035067 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.737370 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.840981 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.777991 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.093248 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.036145 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.282267 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.140279 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.738851 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.137255 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.055556 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.122585 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.080636 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.578092 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.470809 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.093248 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.036145 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.282267 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.251398 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.738851 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.137255 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.055556 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.122585 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.412376 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.578092 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.490634 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.093248 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.036145 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.282267 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.251398 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.738851 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.137255 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.055556 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.122585 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.412376 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.578092 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.490634 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 19714.128035 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2514.184397 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 13114.965986 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5454.545455 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 3623.456790 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 4630.555556 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 146765.281609 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 94575.187515 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 124647.705716 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 193172.413793 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 83000 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 103916.129687 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 115736.338360 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 125279.387085 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 88928.571429 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 89500 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 113393.868710 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 116540.039062 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 145144.222946 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 122829.481005 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 193172.413793 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 103916.129687 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 132673.409422 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 125279.387085 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88928.571429 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 113393.868710 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 96996.286329 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 145144.222946 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 123015.549520 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 193172.413793 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 103916.129687 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 132673.409422 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 125279.387085 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88928.571429 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 113393.868710 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 96996.286329 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 145144.222946 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 123015.549520 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 153 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 76.500000 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 100899 # number of writebacks -system.l2c.writebacks::total 100899 # number of writebacks -system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 2 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 8 # number of ReadSharedReq MSHR hits +system.l2c.writebacks::writebacks 101145 # number of writebacks +system.l2c.writebacks::total 101145 # number of writebacks +system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 8 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 3 # number of ReadSharedReq MSHR hits system.l2c.ReadSharedReq_mshr_hits::cpu1.data 1 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 11 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 12 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 4091 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 4091 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 525 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 273 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 798 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 53 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 86 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 139 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 11064 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 8230 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 19294 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 26 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 4 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19969 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9413 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 131312 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 6 # number of ReadSharedReq MSHR misses +system.l2c.overall_mshr_hits::total 12 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 4176 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 4176 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 453 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 282 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 735 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 99 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 81 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 180 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 11239 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 8266 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 19505 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 29 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19701 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9351 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 131214 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 7 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2738 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 944 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6765 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 171178 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 26 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 4 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 19969 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 20477 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 131312 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 6 # number of demand (read+write) MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2998 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1023 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6755 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 171082 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 29 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 19701 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 20590 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 131214 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 7 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2738 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 9174 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6765 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 190472 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 26 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 4 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 19969 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 20477 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 131312 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 6 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2998 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 9289 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6755 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 190587 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 29 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 19701 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 20590 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 131214 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 7 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2738 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 9174 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6765 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 190472 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2998 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 9289 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6755 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 190587 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3008 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32008 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20577 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 2877 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 37994 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28682 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2230 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 30912 # number of WriteReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14311 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 37997 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19269 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11648 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 30917 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3008 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60690 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39846 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5107 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 68906 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 11977000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 6297000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 18274000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1386000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1952500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 3338500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1536458500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 697602000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 2234060500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 3752500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 313000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1897400002 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1012660501 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15007978241 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 478500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 80000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 267162500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 106122500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 918581086 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 19214528830 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 3752500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 313000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1897400002 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2549119001 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 15007978241 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 478500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 80000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 267162500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 803724500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 918581086 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 21448589330 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 3752500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 313000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1897400002 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2549119001 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15007978241 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 478500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 80000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 267162500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 803724500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 918581086 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 21448589330 # number of overall MSHR miss cycles +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 25959 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 68914 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 10270000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 6598500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 16868500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 2606000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 1791000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 4397000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1537104501 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 699098500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 2236203001 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 5312000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 219000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1850579001 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 988740500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15126263509 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 552500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 79500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 310216001 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 108988500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 912899226 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 19303849737 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 5312000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 219000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1850579001 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2525845001 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 15126263509 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 552500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 79500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 310216001 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 808087000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 912899226 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 21540052738 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 5312000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 219000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1850579001 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2525845001 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15126263509 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 552500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 79500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 310216001 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 808087000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 912899226 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 21540052738 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 210941500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5849372000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7087000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 311625000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6379025500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4060149000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6923000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2100456000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6378469500 # number of ReadReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 210941500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5849372000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7087000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 311625000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 6379025500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4060149000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6923000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2100456000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 6378469500 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.012471 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.054145 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.016929 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.018855 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.036957 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.027053 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.735638 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.838598 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.776294 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.089347 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.036364 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.283168 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.141262 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738666 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.109091 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.052632 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.114341 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.075291 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.578502 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.470816 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.089347 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.036364 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.283168 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.250713 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738666 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.109091 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.052632 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.114341 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.410433 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.578502 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.490363 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.089347 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.036364 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.283168 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.250713 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738666 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.109091 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.052632 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.114341 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.410433 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.578502 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.490363 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22813.333333 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23065.934066 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22899.749373 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26150.943396 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 22703.488372 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24017.985612 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 138870.074114 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 84763.304982 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 115790.427076 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 144326.923077 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 78250 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 95017.276879 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 107581.058217 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114292.511278 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79750 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 80000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 97575.785245 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 112417.902542 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135784.343829 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 112248.821870 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 144326.923077 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 95017.276879 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 124486.936612 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114292.511278 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 80000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 97575.785245 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 87608.949204 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135784.343829 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 112607.571349 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 144326.923077 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 95017.276879 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 124486.936612 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114292.511278 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 80000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 97575.785245 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 87608.949204 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135784.343829 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 112607.571349 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.010794 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.055035 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.015608 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.035612 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.034424 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.035067 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.737370 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.840981 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.777991 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.093248 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.036145 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.282152 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.140279 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738851 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.137255 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.055556 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.122462 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.080558 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.578092 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.470776 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.093248 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.036145 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.282152 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.251398 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738851 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.137255 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.055556 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.122462 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.412331 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.578092 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.490603 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.093248 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.036145 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.282152 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.251398 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738851 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.137255 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.055556 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.122462 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.412331 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.578092 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.490603 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22671.081678 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23398.936170 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22950.340136 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26323.232323 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 22111.111111 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24427.777778 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 136765.237210 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 84575.187515 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 114647.680133 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 183172.413793 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 93933.252170 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 105736.338360 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115279.341450 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 78928.571429 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 79500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 103474.316544 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 106538.123167 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135144.222946 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 112833.902672 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 183172.413793 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 93933.252170 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 122673.385187 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115279.341450 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78928.571429 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 103474.316544 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86993.971364 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135144.222946 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 113019.527764 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 183172.413793 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 93933.252170 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 122673.385187 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115279.341450 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78928.571429 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 103474.316544 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86993.971364 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135144.222946 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 113019.527764 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182747.188203 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70168.316832 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 108315.954119 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167895.601937 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197314.914711 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 68544.554455 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146772.133324 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167867.713241 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70126.828457 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96381.150107 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70168.316832 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 61019.189348 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 92575.762633 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 504615 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 283930 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 101896.024695 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 68544.554455 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80914.364960 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 92556.947790 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 505078 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 284284 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 621 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 37994 # Transaction distribution -system.membus.trans_dist::ReadResp 209423 # Transaction distribution -system.membus.trans_dist::WriteReq 30912 # Transaction distribution -system.membus.trans_dist::WriteResp 30912 # Transaction distribution -system.membus.trans_dist::WritebackDirty 137105 # Transaction distribution -system.membus.trans_dist::CleanEvict 16916 # Transaction distribution -system.membus.trans_dist::UpgradeReq 65086 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 38844 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 37997 # Transaction distribution +system.membus.trans_dist::ReadResp 209330 # Transaction distribution +system.membus.trans_dist::WriteReq 30917 # Transaction distribution +system.membus.trans_dist::WriteResp 30917 # Transaction distribution +system.membus.trans_dist::WritebackDirty 137351 # Transaction distribution +system.membus.trans_dist::CleanEvict 16880 # Transaction distribution +system.membus.trans_dist::UpgradeReq 65170 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 38916 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 38910 # Transaction distribution -system.membus.trans_dist::ReadExResp 19275 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 171430 # Transaction distribution +system.membus.trans_dist::ReadExReq 39129 # Transaction distribution +system.membus.trans_dist::ReadExResp 19493 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 171334 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 4600 # Transaction distribution +system.membus.trans_dist::InvalidateResp 4604 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13742 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 637823 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 759513 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13758 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 638434 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 760140 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 832462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 833089 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162792 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27484 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18694600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18885164 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27516 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18718152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18908748 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21203308 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 127782 # Total snoops (count) +system.membus.pkt_size::total 21226892 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 127972 # Total snoops (count) system.membus.snoopTraffic 36480 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 419404 # Request fanout histogram -system.membus.snoop_fanout::mean 0.012453 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.110898 # Request fanout histogram +system.membus.snoop_fanout::samples 419691 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012454 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.110902 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 414181 98.75% 98.75% # Request fanout histogram -system.membus.snoop_fanout::1 5223 1.25% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 414464 98.75% 98.75% # Request fanout histogram +system.membus.snoop_fanout::1 5227 1.25% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 419404 # Request fanout histogram -system.membus.reqLayer0.occupancy 81639999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 419691 # Request fanout histogram +system.membus.reqLayer0.occupancy 81605499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11433500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11449000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 984876925 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 986014542 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1099184232 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1099737525 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 7225285 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 7231369 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3724,82 +3751,82 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 1044885 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 541195 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 200373 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 29262 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 27938 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 1324 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826653666000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 37997 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 522881 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30912 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30912 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 362121 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 129726 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 111408 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 43843 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 155251 # Transaction distribution +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 1045202 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 540825 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 201129 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 29372 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 28126 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1246 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826672558500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 38000 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 522906 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30917 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30917 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 362294 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 129646 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 111513 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 43869 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 155382 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeFailReq 22 # Transaction distribution system.toL2Bus.trans_dist::UpgradeFailResp 22 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50410 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50410 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 484889 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4647 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 3467 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1304964 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 322117 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1627081 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36107224 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5745684 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 41852908 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 395541 # Total snoops (count) -system.toL2Bus.snoopTraffic 15858252 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 901455 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.406700 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.494199 # Request fanout histogram +system.toL2Bus.trans_dist::ReadExReq 50631 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50631 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 484911 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4651 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 3495 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1260717 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 366727 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1627444 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35956648 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5894436 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 41851084 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 396095 # Total snoops (count) +system.toL2Bus.snoopTraffic 15886732 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 901981 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.407509 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.494174 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 536157 59.48% 59.48% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 363974 40.38% 99.85% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1324 0.15% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 535662 59.39% 59.39% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 365073 40.47% 99.86% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1246 0.14% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 901455 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 896599840 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 901981 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 896811514 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2176474 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2185239 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 692364962 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 675176627 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 244002323 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 261628851 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 1835 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2782 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2792 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 5548f90e7..d37cf635d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.829116 # Number of seconds simulated -sim_ticks 2829116273500 # Number of ticks simulated -final_tick 2829116273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.829112 # Number of seconds simulated +sim_ticks 2829111899000 # Number of ticks simulated +final_tick 2829111899000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 175307 # Simulator instruction rate (inst/s) -host_op_rate 212638 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4382427767 # Simulator tick rate (ticks/s) -host_mem_usage 587848 # Number of bytes of host memory used -host_seconds 645.56 # Real time elapsed on the host -sim_insts 113171321 # Number of instructions simulated -sim_ops 137270537 # Number of ops (including micro ops) simulated +host_inst_rate 175088 # Simulator instruction rate (inst/s) +host_op_rate 212371 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4377954653 # Simulator tick rate (ticks/s) +host_mem_usage 587752 # Number of bytes of host memory used +host_seconds 646.22 # Real time elapsed on the host +sim_insts 113144906 # Number of instructions simulated +sim_ops 137237936 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1316000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9472808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1316192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9473064 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10791176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1316000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1316000 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8091200 # Number of bytes written to this memory +system.physmem.bytes_read::total 10791560 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1316192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1316192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8091072 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8108724 # Number of bytes written to this memory +system.physmem.bytes_written::total 8108596 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22814 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 148533 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22817 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 148537 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 171384 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126425 # Number of write requests responded to by this memory +system.physmem.num_reads::total 171390 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126423 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 130806 # Number of write requests responded to by this memory +system.physmem.num_writes::total 130804 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 465163 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3348328 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 136 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 465232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3348423 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3814327 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 465163 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 465163 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2859974 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3814469 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 465232 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 465232 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2859934 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6194 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2866169 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2859974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2866128 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2859934 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 465163 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3354522 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 465232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3354617 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6680496 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 171385 # Number of read requests accepted -system.physmem.writeReqs 130806 # Number of write requests accepted -system.physmem.readBursts 171385 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 130806 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10959936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8640 # Total number of bytes read from write queue -system.physmem.bytesWritten 8121280 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10791240 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8108724 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 135 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6680597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 171391 # Number of read requests accepted +system.physmem.writeReqs 130804 # Number of write requests accepted +system.physmem.readBursts 171391 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 130804 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10959616 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue +system.physmem.bytesWritten 8121152 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10791624 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8108596 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10685 # Per bank write bursts -system.physmem.perBankRdBursts::1 10044 # Per bank write bursts -system.physmem.perBankRdBursts::2 10839 # Per bank write bursts -system.physmem.perBankRdBursts::3 10919 # Per bank write bursts -system.physmem.perBankRdBursts::4 13721 # Per bank write bursts -system.physmem.perBankRdBursts::5 10679 # Per bank write bursts -system.physmem.perBankRdBursts::6 11440 # Per bank write bursts -system.physmem.perBankRdBursts::7 11401 # Per bank write bursts -system.physmem.perBankRdBursts::8 10106 # Per bank write bursts -system.physmem.perBankRdBursts::9 10397 # Per bank write bursts -system.physmem.perBankRdBursts::10 10359 # Per bank write bursts -system.physmem.perBankRdBursts::11 9487 # Per bank write bursts -system.physmem.perBankRdBursts::12 10224 # Per bank write bursts +system.physmem.perBankRdBursts::0 10684 # Per bank write bursts +system.physmem.perBankRdBursts::1 10046 # Per bank write bursts +system.physmem.perBankRdBursts::2 10837 # Per bank write bursts +system.physmem.perBankRdBursts::3 10895 # Per bank write bursts +system.physmem.perBankRdBursts::4 13724 # Per bank write bursts +system.physmem.perBankRdBursts::5 10674 # Per bank write bursts +system.physmem.perBankRdBursts::6 11441 # Per bank write bursts +system.physmem.perBankRdBursts::7 11403 # Per bank write bursts +system.physmem.perBankRdBursts::8 10108 # Per bank write bursts +system.physmem.perBankRdBursts::9 10400 # Per bank write bursts +system.physmem.perBankRdBursts::10 10362 # Per bank write bursts +system.physmem.perBankRdBursts::11 9483 # Per bank write bursts +system.physmem.perBankRdBursts::12 10233 # Per bank write bursts system.physmem.perBankRdBursts::13 11051 # Per bank write bursts -system.physmem.perBankRdBursts::14 10016 # Per bank write bursts -system.physmem.perBankRdBursts::15 9881 # Per bank write bursts -system.physmem.perBankWrBursts::0 8064 # Per bank write bursts -system.physmem.perBankWrBursts::1 7693 # Per bank write bursts -system.physmem.perBankWrBursts::2 8368 # Per bank write bursts -system.physmem.perBankWrBursts::3 8158 # Per bank write bursts -system.physmem.perBankWrBursts::4 8126 # Per bank write bursts -system.physmem.perBankWrBursts::5 8035 # Per bank write bursts -system.physmem.perBankWrBursts::6 8543 # Per bank write bursts -system.physmem.perBankWrBursts::7 8476 # Per bank write bursts -system.physmem.perBankWrBursts::8 7685 # Per bank write bursts +system.physmem.perBankRdBursts::14 10017 # Per bank write bursts +system.physmem.perBankRdBursts::15 9886 # Per bank write bursts +system.physmem.perBankWrBursts::0 8065 # Per bank write bursts +system.physmem.perBankWrBursts::1 7694 # Per bank write bursts +system.physmem.perBankWrBursts::2 8363 # Per bank write bursts +system.physmem.perBankWrBursts::3 8151 # Per bank write bursts +system.physmem.perBankWrBursts::4 8125 # Per bank write bursts +system.physmem.perBankWrBursts::5 8034 # Per bank write bursts +system.physmem.perBankWrBursts::6 8547 # Per bank write bursts +system.physmem.perBankWrBursts::7 8477 # Per bank write bursts +system.physmem.perBankWrBursts::8 7686 # Per bank write bursts system.physmem.perBankWrBursts::9 7978 # Per bank write bursts -system.physmem.perBankWrBursts::10 7774 # Per bank write bursts -system.physmem.perBankWrBursts::11 7091 # Per bank write bursts -system.physmem.perBankWrBursts::12 7777 # Per bank write bursts +system.physmem.perBankWrBursts::10 7776 # Per bank write bursts +system.physmem.perBankWrBursts::11 7088 # Per bank write bursts +system.physmem.perBankWrBursts::12 7779 # Per bank write bursts system.physmem.perBankWrBursts::13 8428 # Per bank write bursts -system.physmem.perBankWrBursts::14 7463 # Per bank write bursts -system.physmem.perBankWrBursts::15 7236 # Per bank write bursts +system.physmem.perBankWrBursts::14 7464 # Per bank write bursts +system.physmem.perBankWrBursts::15 7238 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 64 # Number of times write queue was full causing retry -system.physmem.totGap 2829116038500 # Total gap between requests +system.physmem.numWrRetry 67 # Number of times write queue was full causing retry +system.physmem.totGap 2829111664000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 3002 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 167827 # Read request sizes (log2) +system.physmem.readPktSize::6 167833 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 126425 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 150010 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 15012 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 860 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 126423 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 150076 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 14975 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -160,126 +160,125 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7868 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8603 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 176 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61274 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 311.408036 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.010622 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.226456 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22407 36.57% 36.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14885 24.29% 60.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6282 10.25% 71.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3692 6.03% 77.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2681 4.38% 81.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1694 2.76% 84.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1136 1.85% 86.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 990 1.62% 87.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7507 12.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61274 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6334 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.026050 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 535.405637 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6332 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 180 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61280 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 311.370235 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.627944 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.836836 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22555 36.81% 36.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14711 24.01% 60.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6399 10.44% 71.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3617 5.90% 77.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2643 4.31% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1730 2.82% 84.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1046 1.71% 86.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1020 1.66% 87.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7559 12.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61280 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6329 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.046295 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 535.582122 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6327 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6334 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6334 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.033944 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.251538 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.603630 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5594 88.32% 88.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 89 1.41% 89.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 43 0.68% 90.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 45 0.71% 91.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 260 4.10% 95.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 21 0.33% 95.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 22 0.35% 95.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 12 0.19% 96.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 10 0.16% 96.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 11 0.17% 96.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.09% 96.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.08% 96.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 137 2.16% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.09% 98.85% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6329 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6329 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.049455 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.259917 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.703816 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5592 88.36% 88.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 89 1.41% 89.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 39 0.62% 90.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 43 0.68% 91.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 270 4.27% 95.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 18 0.28% 95.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 20 0.32% 95.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 12 0.19% 96.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 11 0.17% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 6 0.09% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.03% 96.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.09% 96.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 144 2.28% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.06% 98.85% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-75 7 0.11% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 2 0.03% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 5 0.08% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 10 0.16% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 6 0.09% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.02% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 13 0.21% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.02% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 4 0.06% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.03% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.03% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.03% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 8 0.13% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 4 0.06% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.02% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 15 0.24% 99.62% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::132-135 4 0.06% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.05% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.03% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 4 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.03% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.03% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 5 0.08% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6334 # Writes before turning the bus around for reads -system.physmem.totQLat 4767396000 # Total ticks spent queuing -system.physmem.totMemAccLat 7978314750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 856245000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27838.81 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 6329 # Writes before turning the bus around for reads +system.physmem.totQLat 4759784250 # Total ticks spent queuing +system.physmem.totMemAccLat 7970609250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 856220000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27795.17 # Average queueing delay per DRAM burst system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46588.70 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 46545.06 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.87 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.87 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.81 # Average system read bandwidth in MiByte/s @@ -289,52 +288,52 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.69 # Average write queue length when enqueuing -system.physmem.readRowHits 141756 # Number of row buffer hits during reads -system.physmem.writeRowHits 95114 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.78 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.94 # Row buffer hit rate for writes -system.physmem.avgGap 9362012.89 # Average gap between requests +system.physmem.avgWrQLen 22.41 # Average write queue length when enqueuing +system.physmem.readRowHits 141725 # Number of row buffer hits during reads +system.physmem.writeRowHits 95132 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.76 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.96 # Row buffer hit rate for writes +system.physmem.avgGap 9361874.50 # Average gap between requests system.physmem.pageHitRate 79.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 228894120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 121660110 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 640657920 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 341716860 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5259474480.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4230417450 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 318207360 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 10873180350 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 7365080640 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 667265125080 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 696646226220 # Total energy per rank (pJ) -system.physmem_0.averagePower 246.241638 # Core power per rank (mW) -system.physmem_0.totalIdleTime 2818840383250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 582284750 # Time in different power states -system.physmem_0.memoryStateTime::REF 2236202000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 2775981781500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 19179858500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7291367000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 23844779750 # Time in different power states -system.physmem_1.actEnergy 208602240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 110874720 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 582059940 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 320675040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5116263360.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4098436230 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 317114880 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 10121131470 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 7324658880 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 667774632810 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 695976520350 # Total energy per rank (pJ) -system.physmem_1.averagePower 246.004919 # Core power per rank (mW) -system.physmem_1.totalIdleTime 2819298070500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 592691750 # Time in different power states -system.physmem_1.memoryStateTime::REF 2175820000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 2778027972250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 19074668750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7049691250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 22195429500 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.physmem_0.actEnergy 229315380 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 121884015 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 640486560 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 341680320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 5265620880.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4324767840 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 323323200 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 10830363660 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 7337789280 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 667252731645 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 696670151130 # Total energy per rank (pJ) +system.physmem_0.averagePower 246.250476 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2818571248250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 597049500 # Time in different power states +system.physmem_0.memoryStateTime::REF 2238844000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2775921295250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 19108902750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7495096250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 23750711250 # Time in different power states +system.physmem_1.actEnergy 208223820 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 110673585 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 582195600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 320701140 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 5120565840.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4126082940 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 330709920 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 10081531860 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 7328179680 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 667772142345 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 695983009200 # Total energy per rank (pJ) +system.physmem_1.averagePower 246.007593 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2819198005500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 626918750 # Time in different power states +system.physmem_1.memoryStateTime::REF 2177664000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2778005345250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 19083791250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7109310750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 22108869000 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory @@ -347,30 +346,30 @@ system.realview.nvmem.bw_inst_read::cpu.inst 40 system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46888279 # Number of BP lookups -system.cpu.branchPred.condPredicted 24003428 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1174058 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29505954 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13539674 # Number of BTB hits +system.cpu.branchPred.lookups 46861889 # Number of BP lookups +system.cpu.branchPred.condPredicted 23994211 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1178677 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29377087 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13527695 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 45.887938 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11754876 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 34853 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 7941192 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 7796111 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 145081 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 60202 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 46.048456 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11745847 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 34771 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 7932573 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 7787517 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 145056 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 60304 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -400,91 +399,91 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 71258 # Table walker walks requested -system.cpu.dtb.walker.walksShort 71258 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29064 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23380 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 18814 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 52444 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 391.093357 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 2302.538664 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-4095 50603 96.49% 96.49% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::4096-8191 703 1.34% 97.83% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::8192-12287 574 1.09% 98.92% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::12288-16383 328 0.63% 99.55% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::16384-20479 67 0.13% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::20480-24575 114 0.22% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::24576-28671 32 0.06% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::28672-32767 4 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 70988 # Table walker walks requested +system.cpu.dtb.walker.walksShort 70988 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 28945 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23300 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 18743 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 52245 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 398.564456 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 2327.323415 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-4095 50380 96.43% 96.43% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::4096-8191 694 1.33% 97.76% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::8192-12287 600 1.15% 98.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::12288-16383 333 0.64% 99.54% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::16384-20479 70 0.13% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::20480-24575 116 0.22% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::24576-28671 29 0.06% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::28672-32767 3 0.01% 99.96% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::32768-36863 3 0.01% 99.97% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::36864-40959 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::45056-49151 8 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::45056-49151 9 0.02% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 52444 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 16825 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 9444.665676 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 7665.862074 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 6497.692830 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-8191 8271 49.16% 49.16% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::8192-16383 6932 41.20% 90.36% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-24575 1364 8.11% 98.47% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::24576-32767 166 0.99% 99.45% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-40959 23 0.14% 99.59% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::40960-49151 60 0.36% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkWaitTime::total 52245 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 16835 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 9419.156519 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 7648.743457 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 6474.178852 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-8191 8274 49.15% 49.15% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::8192-16383 6961 41.35% 90.50% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-24575 1349 8.01% 98.51% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::24576-32767 164 0.97% 99.48% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-40959 19 0.11% 99.60% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::40960-49151 59 0.35% 99.95% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::49152-57343 1 0.01% 99.95% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.96% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::65536-73727 1 0.01% 99.96% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::90112-98303 2 0.01% 99.98% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::98304-106495 3 0.02% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::114688-122879 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 16825 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 118990825724 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.630270 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.488920 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 118944532224 99.96% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 32222000 0.03% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 6760000 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 4376000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 965500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 468000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 1159500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 331000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 11500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 118990825724 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6321 82.36% 82.36% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1354 17.64% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7675 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71258 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkCompletionTime::total 16835 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 118986443724 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.628139 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.489522 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 118939907724 99.96% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 32370000 0.03% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 6888500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 4293000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 974500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 505000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 1161500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 334500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 9000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 118986443724 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6321 82.34% 82.34% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1356 17.66% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7677 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 70988 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71258 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7675 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 70988 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7677 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7675 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 78933 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7677 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 78665 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25423698 # DTB read hits -system.cpu.dtb.read_misses 61603 # DTB read misses -system.cpu.dtb.write_hits 19869004 # DTB write hits +system.cpu.dtb.read_hits 25415823 # DTB read hits +system.cpu.dtb.read_misses 61333 # DTB read misses +system.cpu.dtb.write_hits 19865547 # DTB write hits system.cpu.dtb.write_misses 9655 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4259 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 365 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 2214 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4258 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 385 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2212 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1308 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25485301 # DTB read accesses -system.cpu.dtb.write_accesses 19878659 # DTB write accesses +system.cpu.dtb.perms_faults 1098 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25477156 # DTB read accesses +system.cpu.dtb.write_accesses 19875202 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45292702 # DTB hits -system.cpu.dtb.misses 71258 # DTB misses -system.cpu.dtb.accesses 45363960 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 45281370 # DTB hits +system.cpu.dtb.misses 70988 # DTB misses +system.cpu.dtb.accesses 45352358 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -514,51 +513,57 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 12656 # Table walker walks requested -system.cpu.itb.walker.walksShort 12656 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 3345 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 7740 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 1571 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 11085 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 575.732972 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 2511.318158 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-4095 10605 95.67% 95.67% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::4096-8191 108 0.97% 96.64% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::8192-12287 223 2.01% 98.66% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::12288-16383 110 0.99% 99.65% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::16384-20479 16 0.14% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::20480-24575 18 0.16% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::28672-32767 3 0.03% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 12746 # Table walker walks requested +system.cpu.itb.walker.walksShort 12746 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 3372 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 7811 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 1563 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 11183 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 675.266029 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 2802.587445 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-4095 10603 94.81% 94.81% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::4096-8191 140 1.25% 96.07% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::8192-12287 267 2.39% 98.45% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::12288-16383 112 1.00% 99.45% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::16384-20479 22 0.20% 99.65% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::20480-24575 26 0.23% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::24576-28671 5 0.04% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::28672-32767 4 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::36864-40959 2 0.02% 99.98% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::40960-45055 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 11085 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 4896 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 9060.763889 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 7035.829304 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 11150.467524 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 4894 99.96% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkWaitTime::total 11183 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 4880 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 9080.327869 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 7055.685836 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 11146.166993 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 4878 99.96% 99.96% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::65536-131071 1 0.02% 99.98% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 4896 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 24500602212 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.693564 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.461068 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 7508480500 30.65% 30.65% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 16991502712 69.35% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 619000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 24500602212 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2990 89.92% 89.92% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 335 10.08% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3325 # Table walker page sizes translated +system.cpu.itb.walker.walkCompletionTime::total 4880 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 24496220212 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.683787 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.465095 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 7747033500 31.63% 31.63% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 16748218212 68.37% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 952500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 3000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 3500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::5 3000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::6 6500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 24496220212 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2980 89.84% 89.84% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 337 10.16% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3317 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12656 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 12656 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12746 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 12746 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3325 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3325 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 15981 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 65983065 # ITB inst hits -system.cpu.itb.inst_misses 12656 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3317 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3317 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 16063 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 66035618 # ITB inst hits +system.cpu.itb.inst_misses 12746 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -567,21 +572,21 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3022 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3018 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2179 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2274 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 65995721 # ITB inst accesses -system.cpu.itb.hits 65983065 # DTB hits -system.cpu.itb.misses 12656 # DTB misses -system.cpu.itb.accesses 65995721 # DTB accesses +system.cpu.itb.inst_accesses 66048364 # ITB inst accesses +system.cpu.itb.hits 66035618 # DTB hits +system.cpu.itb.misses 12746 # DTB misses +system.cpu.itb.accesses 66048364 # DTB accesses system.cpu.numPwrStateTransitions 6078 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 3039 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 886806915.729845 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17417893662.159683 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 886809089.600197 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17417893131.253975 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 2967 97.63% 97.63% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 66 2.17% 99.80% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state @@ -589,91 +594,91 @@ system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 499972056544 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 499972215488 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 3039 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 134110056597 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2695006216903 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 268220171 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 134099075705 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2695012823295 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 268198207 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 105042564 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 183946336 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46888279 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33090661 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 151947545 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6066122 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 177459 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 8717 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 332750 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 861386 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 140 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 65981974 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 958405 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5944 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 261403622 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.858325 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.227883 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 105002772 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184114970 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46861889 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33061059 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 151938402 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6072000 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 175966 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 7979 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 334285 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 875612 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 143 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 66034467 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1042471 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6106 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 261371159 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.859042 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.228291 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 162493227 62.16% 62.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29157587 11.15% 73.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14046843 5.37% 78.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55705965 21.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 162416335 62.14% 62.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29147387 11.15% 73.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14040939 5.37% 78.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55766498 21.34% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 261403622 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.174813 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.685804 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 78158537 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 112446013 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64386093 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3839619 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2573360 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3404101 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 467760 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157070559 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3511367 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2573360 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83910500 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11255138 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 76381178 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62476128 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24807318 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146500137 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 914744 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 477372 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 65897 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 19059 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 22053744 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150295383 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 677299800 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164022340 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 11055 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141831816 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8463561 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2844179 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2649010 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13862871 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26349559 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21216979 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1695969 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2055276 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143294681 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2116741 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143114526 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 260917 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8140881 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14283010 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 121741 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 261403622 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.547485 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.874392 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 261371159 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.174729 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.686488 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 78127678 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 112458141 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64373777 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3837716 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2573847 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 10211840 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 470330 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157024104 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3522922 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2573847 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83881832 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11236308 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 76411931 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62459889 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24807352 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146462333 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 915339 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 473585 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 65974 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 19134 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 22055359 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150259400 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 677124866 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 163984739 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 11050 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 141797655 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8461739 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2842470 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2647297 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13853647 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26344198 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21214401 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1696128 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2146370 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143256850 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2116673 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143077391 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 262359 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8135583 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14293372 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 121607 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 261371159 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.547411 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.874705 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 173098069 66.22% 66.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45413284 17.37% 83.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 31798683 12.16% 95.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10270501 3.93% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 823052 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 173167745 66.25% 66.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45242575 17.31% 83.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31871715 12.19% 95.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10265143 3.93% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 823948 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -681,9 +686,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 261403622 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 261371159 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7334511 32.77% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7332033 32.77% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 32 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available @@ -714,135 +719,135 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5619720 25.11% 57.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9419018 42.08% 99.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 2403 0.01% 99.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 8747 0.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5621223 25.12% 57.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9411536 42.06% 99.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 2405 0.01% 99.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 8745 0.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 95906474 67.01% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 114332 0.08% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8541 0.01% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 95878441 67.01% 67.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 114347 0.08% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8549 0.01% 67.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26136950 18.26% 85.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 20933494 14.63% 99.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26131013 18.26% 85.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 20930310 14.63% 99.99% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 2708 0.00% 99.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 9690 0.01% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 9686 0.01% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143114526 # Type of FU issued -system.cpu.iq.rate 0.533571 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22384431 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.156409 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 570242068 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 153557534 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140061190 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35954 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13312 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 11500 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165473068 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23552 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 325058 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 143077391 # Type of FU issued +system.cpu.iq.rate 0.533476 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22375974 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.156391 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 570128328 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 153514376 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140022897 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35946 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13304 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 11498 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 165427480 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23548 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 325201 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1430930 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 739 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18590 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 619959 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1431545 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 741 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18622 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 620213 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 88583 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6407 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 88247 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6406 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2573360 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1161160 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 410961 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145591536 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2573847 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1145032 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 405376 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145553638 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26349559 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21216979 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1093729 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17740 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 375076 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18590 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 276726 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471114 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 747840 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142217911 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25746602 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 825466 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26344198 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21214401 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1093740 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17692 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 369492 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18622 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 275358 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 475095 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 750453 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142177506 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25738555 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 828985 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 180114 # number of nop insts executed -system.cpu.iew.exec_refs 46577390 # number of memory reference insts executed -system.cpu.iew.exec_branches 26518344 # Number of branches executed -system.cpu.iew.exec_stores 20830788 # Number of stores executed -system.cpu.iew.exec_rate 0.530228 # Inst execution rate -system.cpu.iew.wb_sent 141848584 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140072690 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63277897 # num instructions producing a value -system.cpu.iew.wb_consumers 95827474 # num instructions consuming a value -system.cpu.iew.wb_rate 0.522230 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660331 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 7357031 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1995000 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 714357 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 258509266 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.531607 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.132560 # Number of insts commited each cycle +system.cpu.iew.exec_nop 180115 # number of nop insts executed +system.cpu.iew.exec_refs 46565887 # number of memory reference insts executed +system.cpu.iew.exec_branches 26507471 # Number of branches executed +system.cpu.iew.exec_stores 20827332 # Number of stores executed +system.cpu.iew.exec_rate 0.530121 # Inst execution rate +system.cpu.iew.wb_sent 141808684 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140034395 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63259988 # num instructions producing a value +system.cpu.iew.wb_consumers 95801132 # num instructions consuming a value +system.cpu.iew.wb_rate 0.522130 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660326 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 7349911 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1995066 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 716524 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 258476519 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.531549 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.133767 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 184931767 71.54% 71.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43412717 16.79% 88.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15465745 5.98% 94.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4363425 1.69% 96.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6516677 2.52% 98.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1538620 0.60% 99.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 797794 0.31% 99.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 415780 0.16% 99.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1066741 0.41% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 185006238 71.58% 71.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43313968 16.76% 88.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15459084 5.98% 94.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4363700 1.69% 96.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6431569 2.49% 98.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1619656 0.63% 99.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 798464 0.31% 99.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 416455 0.16% 99.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1067385 0.41% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 258509266 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113326226 # Number of instructions committed -system.cpu.commit.committedOps 137425442 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 258476519 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113299811 # Number of instructions committed +system.cpu.commit.committedOps 137392841 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45515649 # Number of memory references committed -system.cpu.commit.loads 24918629 # Number of loads committed -system.cpu.commit.membars 814537 # Number of memory barriers committed -system.cpu.commit.branches 26054301 # Number of branches committed +system.cpu.commit.refs 45506841 # Number of memory references committed +system.cpu.commit.loads 24912653 # Number of loads committed +system.cpu.commit.membars 814563 # Number of memory barriers committed +system.cpu.commit.branches 26044441 # Number of branches committed system.cpu.commit.fp_insts 11492 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120244809 # Number of committed integer instructions. -system.cpu.commit.function_calls 4895095 # Number of function calls committed. +system.cpu.commit.int_insts 120215331 # Number of committed integer instructions. +system.cpu.commit.function_calls 4891729 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91788341 66.79% 66.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 112911 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91764545 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 112906 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction @@ -868,43 +873,43 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 8541 0.01% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 8549 0.01% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24915921 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20588240 14.98% 99.99% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24909945 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20585408 14.98% 99.99% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemRead 2708 0.00% 99.99% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemWrite 8780 0.01% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137425442 # Class of committed instruction -system.cpu.commit.bw_lim_events 1066741 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 379966373 # The number of ROB reads -system.cpu.rob.rob_writes 292446245 # The number of ROB writes -system.cpu.timesIdled 894795 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6816549 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5390012377 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113171321 # Number of Instructions Simulated -system.cpu.committedOps 137270537 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.370037 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.370037 # CPI: Total CPI of All Threads -system.cpu.ipc 0.421934 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.421934 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155596425 # number of integer regfile reads -system.cpu.int_regfile_writes 88542209 # number of integer regfile writes -system.cpu.fp_regfile_reads 9690 # number of floating regfile reads +system.cpu.commit.op_class_0::total 137392841 # Class of committed instruction +system.cpu.commit.bw_lim_events 1067385 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 379915503 # The number of ROB reads +system.cpu.rob.rob_writes 292367166 # The number of ROB writes +system.cpu.timesIdled 894415 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6827048 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5390025592 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113144906 # Number of Instructions Simulated +system.cpu.committedOps 137237936 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.370396 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.370396 # CPI: Total CPI of All Threads +system.cpu.ipc 0.421870 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.421870 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155555257 # number of integer regfile reads +system.cpu.int_regfile_writes 88513526 # number of integer regfile writes +system.cpu.fp_regfile_reads 9686 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 502428467 # number of cc regfile reads -system.cpu.cc_regfile_writes 53152553 # number of cc regfile writes -system.cpu.misc_regfile_reads 455632805 # number of misc regfile reads -system.cpu.misc_regfile_writes 1521018 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 835071 # number of replacements +system.cpu.cc_regfile_reads 502284717 # number of cc regfile reads +system.cpu.cc_regfile_writes 53144427 # number of cc regfile writes +system.cpu.misc_regfile_reads 455456531 # number of misc regfile reads +system.cpu.misc_regfile_writes 1521074 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 834899 # number of replacements system.cpu.dcache.tags.tagsinuse 511.950856 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40080644 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 835583 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.967280 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 40072104 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 835411 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.966934 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 291735500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.950856 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999904 # Average percentage of cache occupancy @@ -914,463 +919,463 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 123 system.cpu.dcache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179195359 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179195359 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 23277723 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23277723 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15551809 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15551809 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 346190 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 346190 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 441882 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 441882 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460162 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460162 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38829532 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38829532 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39175722 # number of overall hits -system.cpu.dcache.overall_hits::total 39175722 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 703752 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 703752 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3604950 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3604950 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 176883 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 176883 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 26584 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 26584 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 179153223 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179153223 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 23270451 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23270451 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15550335 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15550335 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 346358 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 346358 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 441909 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 441909 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460176 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460176 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 38820786 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 38820786 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 39167144 # number of overall hits +system.cpu.dcache.overall_hits::total 39167144 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 703305 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 703305 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3603558 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3603558 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 176816 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 176816 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 26536 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 26536 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 4308702 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4308702 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4485585 # number of overall misses -system.cpu.dcache.overall_misses::total 4485585 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11028419500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11028419500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 167321691201 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 167321691201 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 369201500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 369201500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 4306863 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4306863 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4483679 # number of overall misses +system.cpu.dcache.overall_misses::total 4483679 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11004555500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11004555500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 167287466703 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 167287466703 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 367903000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 367903000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 196000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 196000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 178350110701 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 178350110701 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 178350110701 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 178350110701 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23981475 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23981475 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19156759 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19156759 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 523073 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 523073 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468466 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 468466 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460166 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460166 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43138234 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43138234 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43661307 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43661307 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029346 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.029346 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188182 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.188182 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338161 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.338161 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.056747 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.056747 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 178292022203 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 178292022203 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 178292022203 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 178292022203 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23973756 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23973756 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19153893 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19153893 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 523174 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 523174 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468445 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 468445 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460180 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460180 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 43127649 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43127649 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43650823 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43650823 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029336 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.029336 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188137 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.188137 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.337968 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.337968 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.056647 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.056647 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.099881 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.099881 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.102736 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.102736 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15670.889035 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15670.889035 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46414.427718 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46414.427718 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13888.109389 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13888.109389 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.099863 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.099863 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.102717 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.102717 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15646.917767 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15646.917767 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46422.859491 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46422.859491 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13864.297558 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13864.297558 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 49000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 49000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41393.002046 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41393.002046 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39760.724789 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39760.724789 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 631534 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41397.189138 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41397.189138 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39764.671423 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39764.671423 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 631960 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 7012 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7043 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 90.064746 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 89.728809 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 693853 # number of writebacks -system.cpu.dcache.writebacks::total 693853 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291952 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 291952 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3305716 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3305716 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18287 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 18287 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3597668 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3597668 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3597668 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3597668 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 411800 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 411800 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299234 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 299234 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119070 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 119070 # number of SoftPFReq MSHR misses +system.cpu.dcache.writebacks::writebacks 693774 # number of writebacks +system.cpu.dcache.writebacks::total 693774 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291761 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 291761 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3304379 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3304379 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18239 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 18239 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3596140 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3596140 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3596140 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3596140 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 411544 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 411544 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299179 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 299179 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119204 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 119204 # number of SoftPFReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8297 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 8297 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 711034 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 711034 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 830104 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 830104 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 710723 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 710723 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 829927 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 829927 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6169785000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6169785000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14920252482 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14920252482 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1648301500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1648301500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 125755000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 125755000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6158767500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6158767500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14913404483 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14913404483 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1645609500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1645609500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 125434500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 125434500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 192000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 192000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21090037482 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21090037482 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22738338982 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22738338982 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6281915000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6281915000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6281915000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6281915000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017172 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017172 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21072171983 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21072171983 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22717781483 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22717781483 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6282018000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6282018000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6282018000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6282018000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017166 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017166 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015620 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015620 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227636 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227636 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017711 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017711 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227848 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227848 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017712 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017712 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016483 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016483 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019012 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019012 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14982.479359 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14982.479359 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49861.487939 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49861.487939 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13843.130092 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13843.130092 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15156.683138 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15156.683138 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016480 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016480 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019013 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019013 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14965.028041 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14965.028041 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49847.764994 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49847.764994 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13804.985571 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13804.985571 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15118.054719 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15118.054719 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 48000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 48000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29661.081583 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29661.081583 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27392.156865 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27392.156865 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201815.626305 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201815.626305 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106997.240722 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106997.240722 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1888135 # number of replacements -system.cpu.icache.tags.tagsinuse 511.315248 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 63998090 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1888647 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 33.885681 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 14109342500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.315248 # Average occupied blocks per requestor +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29648.923678 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29648.923678 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27373.228589 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27373.228589 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201818.935329 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201818.935329 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106998.995078 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106998.995078 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1887711 # number of replacements +system.cpu.icache.tags.tagsinuse 511.315276 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 64050692 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1888223 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 33.921148 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 14108989500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.315276 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998663 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998663 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 67867650 # Number of tag accesses -system.cpu.icache.tags.data_accesses 67867650 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 63998090 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 63998090 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 63998090 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 63998090 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 63998090 # number of overall hits -system.cpu.icache.overall_hits::total 63998090 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1980875 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1980875 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1980875 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1980875 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1980875 # number of overall misses -system.cpu.icache.overall_misses::total 1980875 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 27580080995 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 27580080995 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 27580080995 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 27580080995 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 27580080995 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 27580080995 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 65978965 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 65978965 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 65978965 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 65978965 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 65978965 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 65978965 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.030023 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.030023 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.030023 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.030023 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.030023 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.030023 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13923.180915 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13923.180915 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13923.180915 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13923.180915 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13923.180915 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13923.180915 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2871 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 67919712 # Number of tag accesses +system.cpu.icache.tags.data_accesses 67919712 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 64050692 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 64050692 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 64050692 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 64050692 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 64050692 # number of overall hits +system.cpu.icache.overall_hits::total 64050692 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1980765 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1980765 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1980765 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1980765 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1980765 # number of overall misses +system.cpu.icache.overall_misses::total 1980765 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 27590430995 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 27590430995 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 27590430995 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 27590430995 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 27590430995 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 27590430995 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66031457 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66031457 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66031457 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66031457 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66031457 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66031457 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029997 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.029997 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.029997 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.029997 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.029997 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.029997 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13929.179380 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13929.179380 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13929.179380 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13929.179380 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13929.179380 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13929.179380 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2703 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 143 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 141 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 20.076923 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 19.170213 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1888135 # number of writebacks -system.cpu.icache.writebacks::total 1888135 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92189 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 92189 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 92189 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 92189 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 92189 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 92189 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1888686 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1888686 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1888686 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1888686 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1888686 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1888686 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 1887711 # number of writebacks +system.cpu.icache.writebacks::total 1887711 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92509 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 92509 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 92509 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 92509 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 92509 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 92509 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1888256 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1888256 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1888256 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1888256 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1888256 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1888256 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3009 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 3009 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3009 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 3009 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24710647497 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24710647497 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24710647497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24710647497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24710647497 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24710647497 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24716064497 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24716064497 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24716064497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24716064497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24716064497 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24716064497 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 246809500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 246809500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 246809500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 246809500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028626 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028626 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028626 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.028626 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028626 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.028626 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13083.512822 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13083.512822 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13083.512822 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13083.512822 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13083.512822 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13083.512822 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028596 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028596 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028596 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.028596 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028596 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.028596 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13089.361028 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13089.361028 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13089.361028 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13089.361028 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13089.361028 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13089.361028 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82023.762047 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82023.762047 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82023.762047 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82023.762047 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 98088 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65152.227961 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5296727 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 163476 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 32.400640 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 91191447000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 8.773365 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 3.748453 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 10408.912220 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 54730.793923 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000134 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000057 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.158827 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.835126 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994144 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65374 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5393 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59670 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000214 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997528 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 43909448 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 43909448 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52450 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 9977 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 62427 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 693853 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 693853 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1850220 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1850220 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 2793 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 2793 # number of UpgradeReq hits +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 98094 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65152.111665 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5295433 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 163482 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 32.391535 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 91189489000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 7.957155 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 4.692905 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 10411.783860 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 54727.677744 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000121 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000072 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.158871 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.835078 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994142 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65376 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 313 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5395 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59668 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000183 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997559 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 43899166 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 43899166 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52220 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10081 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 62301 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 693774 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 693774 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1849835 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1849835 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 2788 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 2788 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 161466 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 161466 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1868784 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1868784 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 525651 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 525651 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 52450 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 9977 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1868784 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 687117 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2618328 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 52450 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 9977 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1868784 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 687117 # number of overall hits -system.cpu.l2cache.overall_hits::total 2618328 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 161417 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 161417 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1868356 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1868356 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 525524 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 525524 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 52220 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10081 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1868356 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 686941 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2617598 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 52220 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10081 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1868356 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 686941 # number of overall hits +system.cpu.l2cache.overall_hits::total 2617598 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 15 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 22 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 21 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 135099 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 135099 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19840 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 19840 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 13387 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 13387 # number of ReadSharedReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 135097 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 135097 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19843 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 19843 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 13393 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 13393 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 15 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 19840 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 148486 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 168348 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 19843 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 148490 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 168354 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 15 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 19840 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 148486 # number of overall misses -system.cpu.l2cache.overall_misses::total 168348 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4526000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 1704000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 6230000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 143500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 143500 # number of UpgradeReq miss cycles +system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 19843 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 148490 # number of overall misses +system.cpu.l2cache.overall_misses::total 168354 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4534500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 2124500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 6659000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 144500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 144500 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 164000 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 164000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12744525000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12744525000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2137683500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 2137683500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1563782000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1563782000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4526000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 1704000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 2137683500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 14308307000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16452220500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4526000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 1704000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2137683500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 14308307000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16452220500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52465 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 9984 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 62449 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 693853 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 693853 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1850220 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1850220 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2798 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2798 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12738264500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12738264500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2148357000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 2148357000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1551011500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1551011500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4534500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 2124500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 2148357000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 14289276000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16444292000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4534500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 2124500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 2148357000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 14289276000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16444292000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52235 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10087 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 62322 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 693774 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 693774 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1849835 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1849835 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2793 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2793 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 4 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 296565 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 296565 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1888624 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1888624 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 539038 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 539038 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52465 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 9984 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1888624 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 835603 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2786676 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52465 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 9984 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1888624 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 835603 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2786676 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000286 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000701 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000352 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.001787 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.001787 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 296514 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 296514 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1888199 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1888199 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 538917 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 538917 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52235 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10087 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1888199 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 835431 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2785952 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52235 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10087 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1888199 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 835431 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2785952 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000287 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000595 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000337 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.001790 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.001790 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.455546 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.455546 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010505 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010505 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024835 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024835 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000286 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000701 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010505 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.177699 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.060412 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000286 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000701 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010505 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.177699 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.060412 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 301733.333333 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 243428.571429 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 283181.818182 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 28700 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 28700 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.455618 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.455618 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010509 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010509 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024852 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024852 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000287 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000595 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010509 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.177741 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.060430 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000287 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000595 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010509 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.177741 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.060430 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 302300 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 354083.333333 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 317095.238095 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 28900 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 28900 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82000 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82000 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 94334.710101 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 94334.710101 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107746.144153 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107746.144153 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 116813.475760 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 116813.475760 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 301733.333333 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 243428.571429 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107746.144153 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96361.320259 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 97727.448500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 301733.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 243428.571429 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107746.144153 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96361.320259 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 97727.448500 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 94289.765872 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 94289.765872 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 108267.751852 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 108267.751852 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115807.623385 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115807.623385 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 302300 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 354083.333333 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 108267.751852 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96230.560981 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 97676.871354 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 302300 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 354083.333333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 108267.751852 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96230.560981 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 97676.871354 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 90235 # number of writebacks -system.cpu.l2cache.writebacks::total 90235 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 90233 # number of writebacks +system.cpu.l2cache.writebacks::total 90233 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 25 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 25 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 113 # number of ReadSharedReq MSHR hits @@ -1382,28 +1387,28 @@ system.cpu.l2cache.overall_mshr_hits::cpu.inst 25 system.cpu.l2cache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 138 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 15 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 22 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 21 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 135099 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 135099 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19815 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19815 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 13274 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 13274 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 135097 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 135097 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19818 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19818 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 13280 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 13280 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 15 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 19815 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 148373 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 168210 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 19818 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 148377 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 168216 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 15 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 19815 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 148373 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 168210 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 19818 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 148377 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 168216 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3009 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34136 # number of ReadReq MSHR uncacheable @@ -1412,146 +1417,146 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3009 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61720 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4376000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 1634000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6010000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 93500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 93500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4384500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 2064500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6449000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 94500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 94500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 144000 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 144000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11393535000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11393535000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1937570500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1937570500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1419751500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1419751500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4376000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 1634000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1937570500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12813286500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14756867000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4376000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 1634000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1937570500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12813286500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14756867000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11387294500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11387294500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1948311000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1948311000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1407408500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1407408500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4384500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 2064500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1948311000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12794703000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14749463000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4384500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 2064500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1948311000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12794703000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14749463000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 209196500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5892817000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6102013500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5892920500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6102117000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 209196500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5892817000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6102013500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000286 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000701 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000352 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.001787 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.001787 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5892920500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6102117000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000287 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000595 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000337 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.001790 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.001790 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455546 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455546 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010492 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010492 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024625 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024625 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000286 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000701 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010492 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177564 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060362 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000286 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000701 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010492 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177564 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060362 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 291733.333333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 233428.571429 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 273181.818182 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18700 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18700 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455618 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455618 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010496 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010496 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024642 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024642 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000287 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000595 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010496 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177605 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060380 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000287 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000595 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010496 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177605 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060380 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 292300 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 344083.333333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 307095.238095 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18900 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18900 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 72000 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 72000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84334.710101 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84334.710101 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97783.017916 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97783.017916 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 106957.322586 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 106957.322586 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 291733.333333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 233428.571429 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97783.017916 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86358.613090 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87728.833006 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 291733.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 233428.571429 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97783.017916 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86358.613090 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87728.833006 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84289.765872 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84289.765872 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 98310.172570 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 98310.172570 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105979.555723 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105979.555723 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 292300 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 344083.333333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 98310.172570 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86231.039851 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87681.689019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 292300 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 344083.333333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 98310.172570 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86231.039851 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87681.689019 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69523.595879 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189315.288977 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 178755.961448 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189318.614065 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 178758.993438 # average ReadReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69523.595879 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100369.896612 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98866.064485 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5482504 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758205 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 46081 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 189 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 189 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100371.659485 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98867.741413 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5481318 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2757626 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 46311 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 188 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 188 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 128785 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2556664 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 128675 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2556003 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 784088 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1888135 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 149071 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2798 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 784007 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1887711 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 148986 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2793 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2802 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1888686 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 539247 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2797 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296514 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296514 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1888256 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 539126 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 4612 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateResp 4 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5671462 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2629463 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 28809 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128289 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8458023 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241760656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98078237 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 39936 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 209860 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 340088689 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 135331 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5917792 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2986371 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.026284 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.159980 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5670183 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2628937 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 29081 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 127780 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8455981 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241706320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98062173 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40348 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 208940 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 340017781 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 135349 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5917412 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2985660 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.026373 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.160242 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2907876 97.37% 97.37% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 78495 2.63% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2906919 97.36% 97.36% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 78741 2.64% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2986371 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5399114998 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2985660 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5397955498 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 298125 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2836925219 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2836300178 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1299904639 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1299640147 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 18830489 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19000487 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 75878391 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 75596896 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30169 # Transaction distribution system.iobus.trans_dist::ReadResp 30169 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1602,11 +1607,11 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480117 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 43091000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 43091500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 100000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 327500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 325500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1636,32 +1641,32 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6161000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6160500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33823000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 33869500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187589137 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187578393 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36712000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36410 # number of replacements -system.iocache.tags.tagsinuse 1.001834 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.001800 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 253684759000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.001834 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062615 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062615 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 253685816000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.001800 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062613 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062613 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 327996 # Number of tag accesses system.iocache.tags.data_accesses 327996 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses system.iocache.ReadReq_misses::total 220 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -1670,14 +1675,14 @@ system.iocache.demand_misses::realview.ide 36444 # system.iocache.demand_misses::total 36444 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36444 # number of overall misses system.iocache.overall_misses::total 36444 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 35729875 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 35729875 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4377211262 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4377211262 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4412941137 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4412941137 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4412941137 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4412941137 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 35734875 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 35734875 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4362724518 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4362724518 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4398459393 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4398459393 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4398459393 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4398459393 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1694,19 +1699,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 162408.522727 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 162408.522727 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120837.325033 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120837.325033 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 121088.276177 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 121088.276177 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 121088.276177 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 121088.276177 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 444 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 162431.250000 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 162431.250000 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120437.403876 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120437.403876 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120690.906404 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120690.906404 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120690.906404 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120690.906404 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 222 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks @@ -1718,14 +1723,14 @@ system.iocache.demand_mshr_misses::realview.ide 36444 system.iocache.demand_mshr_misses::total 36444 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36444 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36444 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 24729875 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 24729875 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2564234451 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2564234451 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2588964326 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2588964326 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2588964326 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2588964326 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 24734875 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 24734875 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2549742484 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2549742484 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2574477359 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2574477359 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2574477359 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2574477359 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1734,91 +1739,91 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112408.522727 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 112408.522727 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70788.274376 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70788.274376 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 71039.521622 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 71039.521622 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 71039.521622 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 71039.521622 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 339223 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 139296 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112431.250000 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 112431.250000 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70388.209033 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70388.209033 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70642.008534 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70642.008534 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70642.008534 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70642.008534 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 339238 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 139305 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 511 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 34136 # Transaction distribution -system.membus.trans_dist::ReadResp 67466 # Transaction distribution +system.membus.trans_dist::ReadResp 67474 # Transaction distribution system.membus.trans_dist::WriteReq 27584 # Transaction distribution system.membus.trans_dist::WriteResp 27584 # Transaction distribution -system.membus.trans_dist::WritebackDirty 126425 # Transaction distribution -system.membus.trans_dist::CleanEvict 8073 # Transaction distribution +system.membus.trans_dist::WritebackDirty 126423 # Transaction distribution +system.membus.trans_dist::CleanEvict 8081 # Transaction distribution system.membus.trans_dist::UpgradeReq 126 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 134978 # Transaction distribution -system.membus.trans_dist::ReadExResp 134978 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 33331 # Transaction distribution +system.membus.trans_dist::ReadExReq 134976 # Transaction distribution +system.membus.trans_dist::ReadExResp 134976 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 33339 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 4572 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 449994 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 557556 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450012 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 557574 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72869 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72869 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 630425 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 630443 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16582780 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16746157 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16583036 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16746413 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19063277 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19063533 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 5056 # Total snoops (count) system.membus.snoopTraffic 30848 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 266381 # Request fanout histogram +system.membus.snoop_fanout::samples 266387 # Request fanout histogram system.membus.snoop_fanout::mean 0.019149 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.137050 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.137048 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 261280 98.09% 98.09% # Request fanout histogram +system.membus.snoop_fanout::0 261286 98.09% 98.09% # Request fanout histogram system.membus.snoop_fanout::1 5101 1.91% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 266381 # Request fanout histogram -system.membus.reqLayer0.occupancy 84417000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 266387 # Request fanout histogram +system.membus.reqLayer0.occupancy 84461000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1728499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1733999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 876893413 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 877020942 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 984678000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 984714000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 5966654 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 5968652 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1850,29 +1855,29 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2829116273500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2829111899000 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3039 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index 2db3ee4aa..ec1d5e30b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,171 +1,171 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.356210 # Number of seconds simulated -sim_ticks 47356210126000 # Number of ticks simulated -final_tick 47356210126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.310816 # Number of seconds simulated +sim_ticks 47310816168000 # Number of ticks simulated +final_tick 47310816168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 269105 # Simulator instruction rate (inst/s) -host_op_rate 316551 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14489745940 # Simulator tick rate (ticks/s) -host_mem_usage 771556 # Number of bytes of host memory used -host_seconds 3268.26 # Real time elapsed on the host -sim_insts 879504495 # Number of instructions simulated -sim_ops 1034569807 # Number of ops (including micro ops) simulated +host_inst_rate 279196 # Simulator instruction rate (inst/s) +host_op_rate 332505 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15871048208 # Simulator tick rate (ticks/s) +host_mem_usage 770320 # Number of bytes of host memory used +host_seconds 2980.95 # Real time elapsed on the host +sim_insts 832269934 # Number of instructions simulated +sim_ops 991180133 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 139968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 127936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 7960960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 14481160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 15033920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 105216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 97088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3386304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 9267600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 11152448 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 451392 # Number of bytes read from this memory -system.physmem.bytes_read::total 62203992 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 7960960 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3386304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11347264 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 74964928 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 133120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 103552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 5351360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 14671112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 17389824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 166080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 153792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3559616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 12274128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 15128448 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 452672 # Number of bytes read from this memory +system.physmem.bytes_read::total 69383704 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 5351360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3559616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 8910976 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 84006336 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 74985512 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2187 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1999 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 124390 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 226281 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 234905 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1644 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1517 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 52911 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 144819 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 174257 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 7053 # Number of read requests responded to by this memory -system.physmem.num_reads::total 971963 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1171327 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 84026920 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2080 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1618 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 83615 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 229249 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 271716 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2595 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2403 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 55619 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 191796 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 236382 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 7073 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1084146 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1312599 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1173901 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 168108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 305792 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 317465 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2222 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 71507 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 195700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 235501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9532 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1313534 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 168108 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 71507 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 239615 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1583001 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1315173 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2189 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 113111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 310101 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 367566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3251 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 75239 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 259436 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 319767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9568 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1466551 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 113111 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 75239 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 188350 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1775626 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1583436 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1583001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 168108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 306227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 317465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 71507 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 195700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 235501 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9532 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2896970 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 971963 # Number of read requests accepted -system.physmem.writeReqs 1173901 # Number of write requests accepted -system.physmem.readBursts 971963 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1173901 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 62180096 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 25536 # Total number of bytes read from write queue -system.physmem.bytesWritten 74984000 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62203992 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 74985512 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 399 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1776062 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1775626 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2189 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 113111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 310536 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 367566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3251 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 75239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 259436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 319767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3242612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1084146 # Number of read requests accepted +system.physmem.writeReqs 1315173 # Number of write requests accepted +system.physmem.readBursts 1084146 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1315173 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 69357696 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 27648 # Total number of bytes read from write queue +system.physmem.bytesWritten 84025344 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 69383704 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 84026920 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 432 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 55033 # Per bank write bursts -system.physmem.perBankRdBursts::1 62597 # Per bank write bursts -system.physmem.perBankRdBursts::2 50092 # Per bank write bursts -system.physmem.perBankRdBursts::3 57292 # Per bank write bursts -system.physmem.perBankRdBursts::4 55886 # Per bank write bursts -system.physmem.perBankRdBursts::5 65305 # Per bank write bursts -system.physmem.perBankRdBursts::6 62171 # Per bank write bursts -system.physmem.perBankRdBursts::7 60911 # Per bank write bursts -system.physmem.perBankRdBursts::8 55564 # Per bank write bursts -system.physmem.perBankRdBursts::9 110087 # Per bank write bursts -system.physmem.perBankRdBursts::10 50665 # Per bank write bursts -system.physmem.perBankRdBursts::11 58731 # Per bank write bursts -system.physmem.perBankRdBursts::12 55379 # Per bank write bursts -system.physmem.perBankRdBursts::13 59204 # Per bank write bursts -system.physmem.perBankRdBursts::14 58833 # Per bank write bursts -system.physmem.perBankRdBursts::15 53814 # Per bank write bursts -system.physmem.perBankWrBursts::0 70729 # Per bank write bursts -system.physmem.perBankWrBursts::1 73923 # Per bank write bursts -system.physmem.perBankWrBursts::2 67641 # Per bank write bursts -system.physmem.perBankWrBursts::3 73309 # Per bank write bursts -system.physmem.perBankWrBursts::4 73460 # Per bank write bursts -system.physmem.perBankWrBursts::5 77994 # Per bank write bursts -system.physmem.perBankWrBursts::6 75119 # Per bank write bursts -system.physmem.perBankWrBursts::7 77047 # Per bank write bursts -system.physmem.perBankWrBursts::8 72172 # Per bank write bursts -system.physmem.perBankWrBursts::9 76177 # Per bank write bursts -system.physmem.perBankWrBursts::10 69310 # Per bank write bursts -system.physmem.perBankWrBursts::11 74055 # Per bank write bursts -system.physmem.perBankWrBursts::12 71196 # Per bank write bursts -system.physmem.perBankWrBursts::13 73730 # Per bank write bursts -system.physmem.perBankWrBursts::14 72781 # Per bank write bursts -system.physmem.perBankWrBursts::15 72982 # Per bank write bursts +system.physmem.perBankRdBursts::0 69238 # Per bank write bursts +system.physmem.perBankRdBursts::1 72128 # Per bank write bursts +system.physmem.perBankRdBursts::2 62859 # Per bank write bursts +system.physmem.perBankRdBursts::3 64909 # Per bank write bursts +system.physmem.perBankRdBursts::4 64833 # Per bank write bursts +system.physmem.perBankRdBursts::5 74280 # Per bank write bursts +system.physmem.perBankRdBursts::6 68552 # Per bank write bursts +system.physmem.perBankRdBursts::7 74109 # Per bank write bursts +system.physmem.perBankRdBursts::8 62269 # Per bank write bursts +system.physmem.perBankRdBursts::9 70311 # Per bank write bursts +system.physmem.perBankRdBursts::10 59842 # Per bank write bursts +system.physmem.perBankRdBursts::11 70232 # Per bank write bursts +system.physmem.perBankRdBursts::12 64744 # Per bank write bursts +system.physmem.perBankRdBursts::13 72876 # Per bank write bursts +system.physmem.perBankRdBursts::14 66012 # Per bank write bursts +system.physmem.perBankRdBursts::15 66520 # Per bank write bursts +system.physmem.perBankWrBursts::0 83559 # Per bank write bursts +system.physmem.perBankWrBursts::1 83793 # Per bank write bursts +system.physmem.perBankWrBursts::2 79464 # Per bank write bursts +system.physmem.perBankWrBursts::3 82775 # Per bank write bursts +system.physmem.perBankWrBursts::4 80648 # Per bank write bursts +system.physmem.perBankWrBursts::5 87124 # Per bank write bursts +system.physmem.perBankWrBursts::6 80406 # Per bank write bursts +system.physmem.perBankWrBursts::7 83854 # Per bank write bursts +system.physmem.perBankWrBursts::8 77300 # Per bank write bursts +system.physmem.perBankWrBursts::9 82321 # Per bank write bursts +system.physmem.perBankWrBursts::10 78447 # Per bank write bursts +system.physmem.perBankWrBursts::11 84798 # Per bank write bursts +system.physmem.perBankWrBursts::12 79286 # Per bank write bursts +system.physmem.perBankWrBursts::13 85569 # Per bank write bursts +system.physmem.perBankWrBursts::14 81705 # Per bank write bursts +system.physmem.perBankWrBursts::15 81847 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 338 # Number of times write queue was full causing retry -system.physmem.totGap 47356208030500 # Total gap between requests +system.physmem.numWrRetry 404 # Number of times write queue was full causing retry +system.physmem.totGap 47310814104000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 971933 # Read request sizes (log2) +system.physmem.readPktSize::6 1084116 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1171327 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 599542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 159109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46981 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 36741 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 28369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 25953 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 23819 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 21360 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 18806 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1833 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1239 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 994 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 286 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 244 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 93 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1312599 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 617903 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 194931 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 61099 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 46691 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 35439 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 32251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 29577 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 26712 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 23659 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 6340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1816 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1051 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 661 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 562 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 366 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 150 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 96 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -189,187 +189,187 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 24305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 32346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 48833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 64343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 66279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 68229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 71242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 71432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 74216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 76183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 73010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 71262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 72325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 75575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 67464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 63552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 894 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 423 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 769 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 927860 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 147.827612 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 99.770435 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 195.442358 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 609464 65.68% 65.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 190800 20.56% 86.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 46263 4.99% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21195 2.28% 93.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15500 1.67% 95.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9774 1.05% 96.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7067 0.76% 97.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5586 0.60% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22211 2.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 927860 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 57099 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 17.014939 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 164.898277 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 57097 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 57099 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 57099 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.519186 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.696547 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.054604 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 49168 86.11% 86.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 2307 4.04% 90.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 623 1.09% 91.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 607 1.06% 92.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 970 1.70% 94.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 377 0.66% 94.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 342 0.60% 95.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 248 0.43% 95.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 171 0.30% 96.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 147 0.26% 96.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 125 0.22% 96.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 141 0.25% 96.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 491 0.86% 97.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 181 0.32% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 140 0.25% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 149 0.26% 98.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 103 0.18% 98.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 79 0.14% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 87 0.15% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 90 0.16% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 76 0.13% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 61 0.11% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 62 0.11% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 70 0.12% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 41 0.07% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 40 0.07% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 42 0.07% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 34 0.06% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 42 0.07% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 20 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 12 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 13 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 6 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 4 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 5 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::15 25826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 51697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 60223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 67549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 71954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 74550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 77056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 80172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 80848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 83842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 85747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 82598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 81110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 82972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 86524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 78237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 73594 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 917 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1043685 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 146.962350 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 99.815605 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 191.425821 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 685015 65.63% 65.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 212974 20.41% 86.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53995 5.17% 91.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 24749 2.37% 93.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18577 1.78% 95.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11845 1.13% 96.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7907 0.76% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6706 0.64% 97.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21917 2.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1043685 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 65638 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.510147 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 26.150337 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 65626 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 8 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5632-5887 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 65638 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 65638 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.002072 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.384137 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.246607 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 57560 87.69% 87.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 2491 3.80% 91.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 689 1.05% 92.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 564 0.86% 93.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 947 1.44% 94.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 301 0.46% 95.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 320 0.49% 95.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 211 0.32% 96.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 208 0.32% 96.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 135 0.21% 96.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 147 0.22% 96.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 134 0.20% 97.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 619 0.94% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 144 0.22% 98.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 133 0.20% 98.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 128 0.20% 98.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 93 0.14% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 63 0.10% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 64 0.10% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 96 0.15% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 75 0.11% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 71 0.11% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 89 0.14% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 57 0.09% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 53 0.08% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 43 0.07% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 44 0.07% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 41 0.06% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 43 0.07% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 17 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 9 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 14 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 4 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::184-187 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 57099 # Writes before turning the bus around for reads -system.physmem.totQLat 49354955217 # Total ticks spent queuing -system.physmem.totMemAccLat 67571780217 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4857820000 # Total ticks spent in databus transfers -system.physmem.avgQLat 50799.49 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::188-191 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 7 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 65638 # Writes before turning the bus around for reads +system.physmem.totQLat 57570179828 # Total ticks spent queuing +system.physmem.totMemAccLat 77889817328 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5418570000 # Total ticks spent in databus transfers +system.physmem.avgQLat 53123.04 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 69549.49 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.31 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 71873.04 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.47 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.78 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.47 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.78 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.53 # Average write queue length when enqueuing -system.physmem.readRowHits 725116 # Number of row buffer hits during reads -system.physmem.writeRowHits 490210 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.84 # Row buffer hit rate for writes -system.physmem.avgGap 22068597.09 # Average gap between requests -system.physmem.pageHitRate 56.71 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3347988840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1779490680 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3350709180 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3075738840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 40224500160.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 43885079760 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2109996960 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 79595636190 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 56472597600 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 11270458828185 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 11504320668105 # Total energy per rank (pJ) -system.physmem_0.averagePower 242.931616 # Core power per rank (mW) -system.physmem_0.totalIdleTime 47254429054365 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 3740889550 # Time in different power states -system.physmem_0.memoryStateTime::REF 17088544000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 46932815651000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 147063936092 # Time in different power states -system.physmem_0.memoryStateTime::ACT 80948731835 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 174552373523 # Time in different power states -system.physmem_1.actEnergy 3276952980 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1741738020 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3586257780 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3040143660 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 38004420480.000008 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 43585213590 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1995622560 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 72860280210 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 53203975680 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 11275978868760 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 11497290812280 # Total energy per rank (pJ) -system.physmem_1.averagePower 242.783170 # Core power per rank (mW) -system.physmem_1.totalIdleTime 47255392508641 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3486165610 # Time in different power states -system.physmem_1.memoryStateTime::REF 16146094000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 46957059679500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 138551420004 # Time in different power states -system.physmem_1.memoryStateTime::ACT 81185307499 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 159781459387 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.92 # Average write queue length when enqueuing +system.physmem.readRowHits 798943 # Number of row buffer hits during reads +system.physmem.writeRowHits 553978 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.72 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 42.19 # Row buffer hit rate for writes +system.physmem.avgGap 19718434.32 # Average gap between requests +system.physmem.pageHitRate 56.45 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3802085700 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2020848885 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3933483120 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3453672060 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 39277339920.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 44911710750 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1916970240 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 82436275650 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 52427154240 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 11259457849125 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 11493654896520 # Total energy per rank (pJ) +system.physmem_0.averagePower 242.939265 # Core power per rank (mW) +system.physmem_0.totalIdleTime 47207292873414 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3245693994 # Time in different power states +system.physmem_0.memoryStateTime::REF 16679736000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 46889984158000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 136529047983 # Time in different power states +system.physmem_0.memoryStateTime::ACT 83596561092 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 180780970931 # Time in different power states +system.physmem_1.actEnergy 3649853760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1939935690 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3804234840 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3399645060 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 37874116800.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 45213068040 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1883953920 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 76352255250 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 50620183680 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 11263627504680 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 11488379615340 # Total energy per rank (pJ) +system.physmem_1.averagePower 242.827762 # Core power per rank (mW) +system.physmem_1.totalIdleTime 47206725446684 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3212291316 # Time in different power states +system.physmem_1.memoryStateTime::REF 16085928000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 46907462906500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 131823013391 # Time in different power states +system.physmem_1.memoryStateTime::ACT 84792497000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 167439531793 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory @@ -396,30 +396,30 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 14 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 29 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 135721275 # Number of BP lookups -system.cpu0.branchPred.condPredicted 95221356 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6297780 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 101561419 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 70514394 # Number of BTB hits +system.cpu0.branchPred.lookups 116746639 # Number of BP lookups +system.cpu0.branchPred.condPredicted 74661681 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6562912 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 81659728 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 48398116 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 69.430296 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 16061922 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1062204 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 3676908 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 2416966 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 1259942 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 447333 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 59.268035 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 16692830 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1123660 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 3717417 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2487467 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 1229950 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 447789 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -449,64 +449,64 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 280305 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 280305 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9673 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 80745 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 280305 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 280305 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 280305 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 90418 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 24557.682099 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 22462.475848 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 18823.909973 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 89075 98.51% 98.51% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1011 1.12% 99.63% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 175 0.19% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 66 0.07% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 41 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 17 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 5 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 21 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 90418 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 1049600704 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 1049600704 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 1049600704 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 80745 89.30% 89.30% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 9673 10.70% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 90418 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 280305 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 291933 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 291933 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10456 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84439 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 291933 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 291933 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 291933 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 94895 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 24023.404816 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 22175.510022 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 15850.715577 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 93828 98.88% 98.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 782 0.82% 99.70% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 167 0.18% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 53 0.06% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 36 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 9 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 94895 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 490774000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 490774000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 490774000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 84439 88.98% 88.98% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10456 11.02% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 94895 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 291933 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 280305 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 90418 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 291933 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 94895 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 90418 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 370723 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 94895 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 386828 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 85620412 # DTB read hits -system.cpu0.dtb.read_misses 232360 # DTB read misses -system.cpu0.dtb.write_hits 76323418 # DTB write hits -system.cpu0.dtb.write_misses 47945 # DTB write misses +system.cpu0.dtb.read_hits 91107490 # DTB read hits +system.cpu0.dtb.read_misses 238663 # DTB read misses +system.cpu0.dtb.write_hits 81148084 # DTB write hits +system.cpu0.dtb.write_misses 53270 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 40720 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 37568 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 2099 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 10030 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 37379 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 2076 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9352 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 11718 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 85852772 # DTB read accesses -system.cpu0.dtb.write_accesses 76371363 # DTB write accesses +system.cpu0.dtb.perms_faults 11764 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 91346153 # DTB read accesses +system.cpu0.dtb.write_accesses 81201354 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 161943830 # DTB hits -system.cpu0.dtb.misses 280305 # DTB misses -system.cpu0.dtb.accesses 162224135 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 172255574 # DTB hits +system.cpu0.dtb.misses 291933 # DTB misses +system.cpu0.dtb.accesses 172547507 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -536,767 +536,773 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 68220 # Table walker walks requested -system.cpu0.itb.walker.walksLong 68220 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 613 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59689 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 68220 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 68220 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 68220 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 60302 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 26595.826009 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 24233.258451 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 21809.844701 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 58891 97.66% 97.66% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 1009 1.67% 99.33% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 274 0.45% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 71 0.12% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 14 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 15 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 3 0.00% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 21 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 60302 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 1048830204 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 1048830204 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 1048830204 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 59689 98.98% 98.98% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 613 1.02% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 60302 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 65131 # Table walker walks requested +system.cpu0.itb.walker.walksLong 65131 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 651 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 56721 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 65131 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 65131 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 65131 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 57372 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 26035.845012 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23914.977730 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 19217.419826 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 56364 98.24% 98.24% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 674 1.17% 99.42% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 235 0.41% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 63 0.11% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 11 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 6 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 15 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 57372 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 490003500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 490003500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 490003500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 56721 98.87% 98.87% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 651 1.13% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 57372 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 68220 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 68220 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 65131 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 65131 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60302 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60302 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 128522 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 240780512 # ITB inst hits -system.cpu0.itb.inst_misses 68220 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57372 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57372 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 122503 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 201165320 # ITB inst hits +system.cpu0.itb.inst_misses 65131 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 40720 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 26473 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 26201 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 160298 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 173484 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 240848732 # ITB inst accesses -system.cpu0.itb.hits 240780512 # DTB hits -system.cpu0.itb.misses 68220 # DTB misses -system.cpu0.itb.accesses 240848732 # DTB accesses -system.cpu0.numPwrStateTransitions 27604 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 13802 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 3395512179.708375 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 87569621243.897629 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3847 27.87% 27.87% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 9929 71.94% 99.81% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 201230451 # ITB inst accesses +system.cpu0.itb.hits 201165320 # DTB hits +system.cpu0.itb.misses 65131 # DTB misses +system.cpu0.itb.accesses 201230451 # DTB accesses +system.cpu0.numPwrStateTransitions 27066 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 13533 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 3461850354.100126 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 88555833572.600677 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3597 26.58% 26.58% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 9910 73.23% 99.81% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 7470353787292 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 13802 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 491351021665 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 46864859104335 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 982743358 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 7470353817972 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 13533 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 461595325963 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46849220842037 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 923231946 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 443442317 # Number of instructions committed -system.cpu0.committedOps 521139520 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 46171758 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 4942 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93730487058 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.216170 # CPI: cycles per instruction -system.cpu0.ipc 0.451229 # IPC: instructions per cycle -system.cpu0.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.op_class_0::IntAlu 361587453 69.38% 69.38% # Class of committed instruction -system.cpu0.op_class_0::IntMult 1073144 0.21% 69.59% # Class of committed instruction -system.cpu0.op_class_0::IntDiv 57197 0.01% 69.60% # Class of committed instruction -system.cpu0.op_class_0::FloatAdd 8 0.00% 69.60% # Class of committed instruction -system.cpu0.op_class_0::FloatCmp 13 0.00% 69.60% # Class of committed instruction -system.cpu0.op_class_0::FloatCvt 21 0.00% 69.60% # Class of committed instruction -system.cpu0.op_class_0::FloatMult 0 0.00% 69.60% # Class of committed instruction -system.cpu0.op_class_0::FloatMultAcc 0 0.00% 69.60% # Class of committed instruction -system.cpu0.op_class_0::FloatDiv 0 0.00% 69.60% # Class of committed instruction -system.cpu0.op_class_0::FloatMisc 48874 0.01% 69.61% # Class of committed instruction -system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMisc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.op_class_0::MemRead 82336787 15.80% 85.41% # Class of committed instruction -system.cpu0.op_class_0::MemWrite 75604792 14.51% 99.92% # Class of committed instruction -system.cpu0.op_class_0::FloatMemRead 54276 0.01% 99.93% # Class of committed instruction -system.cpu0.op_class_0::FloatMemWrite 376955 0.07% 100.00% # Class of committed instruction +system.cpu0.committedInsts 433947137 # Number of instructions committed +system.cpu0.committedOps 516803462 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 22098859 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 4673 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93699151861 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.127522 # CPI: cycles per instruction +system.cpu0.ipc 0.470030 # IPC: instructions per cycle +system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction +system.cpu0.op_class_0::IntAlu 346907240 67.13% 67.13% # Class of committed instruction +system.cpu0.op_class_0::IntMult 1217129 0.24% 67.36% # Class of committed instruction +system.cpu0.op_class_0::IntDiv 58486 0.01% 67.37% # Class of committed instruction +system.cpu0.op_class_0::FloatAdd 8 0.00% 67.37% # Class of committed instruction +system.cpu0.op_class_0::FloatCmp 13 0.00% 67.37% # Class of committed instruction +system.cpu0.op_class_0::FloatCvt 21 0.00% 67.37% # Class of committed instruction +system.cpu0.op_class_0::FloatMult 0 0.00% 67.37% # Class of committed instruction +system.cpu0.op_class_0::FloatMultAcc 0 0.00% 67.37% # Class of committed instruction +system.cpu0.op_class_0::FloatDiv 0 0.00% 67.37% # Class of committed instruction +system.cpu0.op_class_0::FloatMisc 70436 0.01% 67.39% # Class of committed instruction +system.cpu0.op_class_0::FloatSqrt 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdAdd 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdAddAcc 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdAlu 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdCmp 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdCvt 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdMisc 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdMult 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdMultAcc 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdShift 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdSqrt 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMisc 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMult 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 67.39% # Class of committed instruction +system.cpu0.op_class_0::MemRead 87685666 16.97% 84.35% # Class of committed instruction +system.cpu0.op_class_0::MemWrite 80429583 15.56% 99.92% # Class of committed instruction +system.cpu0.op_class_0::FloatMemRead 59649 0.01% 99.93% # Class of committed instruction +system.cpu0.op_class_0::FloatMemWrite 375230 0.07% 100.00% # Class of committed instruction system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.op_class_0::total 521139520 # Class of committed instruction +system.cpu0.op_class_0::total 516803462 # Class of committed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13802 # number of quiesce instructions executed -system.cpu0.tickCycles 716804238 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 265939120 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 5714630 # number of replacements -system.cpu0.dcache.tags.tagsinuse 503.374360 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 153605175 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5715141 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 26.876883 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 5354308000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.374360 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983153 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.983153 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 326958988 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 326958988 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 78624149 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 78624149 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 70655306 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 70655306 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 268473 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 268473 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 172491 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 172491 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1691736 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1691736 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1666426 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1666426 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 149451946 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 149451946 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 149720419 # number of overall hits -system.cpu0.dcache.overall_hits::total 149720419 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3212821 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3212821 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2434459 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2434459 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 667240 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 667240 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 831306 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 831306 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 163515 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 163515 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 187633 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 187633 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 6478586 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 6478586 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 7145826 # number of overall misses -system.cpu0.dcache.overall_misses::total 7145826 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52300502500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 52300502500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52442906000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 52442906000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 26430842500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 26430842500 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2572412500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2572412500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4480220000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4480220000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2147000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2147000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 131174251000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 131174251000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 131174251000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 131174251000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 81836970 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 81836970 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 73089765 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 73089765 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 935713 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 935713 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1003797 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1003797 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1855251 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1855251 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1854059 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1854059 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 155930532 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 155930532 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 156866245 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 156866245 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039259 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.039259 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033308 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.033308 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.713082 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.713082 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.828161 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.828161 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088136 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088136 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.101201 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.101201 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.041548 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.041548 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.045554 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.045554 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16278.685461 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 16278.685461 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21541.913830 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 21541.913830 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 31794.360320 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 31794.360320 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15731.966486 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15731.966486 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23877.569511 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23877.569511 # average StoreCondReq miss latency +system.cpu0.kern.inst.quiesce 13533 # number of quiesce instructions executed +system.cpu0.tickCycles 653190940 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 270041006 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 6005277 # number of replacements +system.cpu0.dcache.tags.tagsinuse 502.540168 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 163513084 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6005789 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.225912 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 500703000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.540168 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.981524 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.981524 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 347779597 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 347779597 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 83636950 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 83636950 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 75142855 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 75142855 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 275029 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 275029 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 178111 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 178111 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1878303 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1878303 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1839620 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1839620 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 158957916 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 158957916 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 159232945 # number of overall hits +system.cpu0.dcache.overall_hits::total 159232945 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3392683 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3392683 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2596834 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2596834 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 729933 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 729933 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 807715 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 807715 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 164864 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 164864 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 202355 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 202355 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 6797232 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 6797232 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 7527165 # number of overall misses +system.cpu0.dcache.overall_misses::total 7527165 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 55240233000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 55240233000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 55000663500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 55000663500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 26000939500 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 26000939500 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2528136500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2528136500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4851897500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4851897500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2304500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2304500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 136241836000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 136241836000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 136241836000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 136241836000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 87029633 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 87029633 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 77739689 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 77739689 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1004962 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1004962 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 985826 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 985826 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2043167 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2043167 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2041975 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2041975 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 165755148 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 165755148 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 166760110 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 166760110 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038983 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.038983 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033404 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.033404 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.726329 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.726329 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.819328 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.819328 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.080690 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.080690 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.099098 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099098 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.041008 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.041008 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.045138 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.045138 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16282.167535 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 16282.167535 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21179.891938 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 21179.891938 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32190.734975 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32190.734975 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15334.678887 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15334.678887 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23977.156482 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23977.156482 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20247.358143 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 20247.358143 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18356.765334 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18356.765334 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20043.723092 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 20043.723092 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18100.019861 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18100.019861 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 5714633 # number of writebacks -system.cpu0.dcache.writebacks::total 5714633 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202792 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 202792 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1014502 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1014502 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 93 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 93 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43372 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43372 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 49 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 49 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1217387 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1217387 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1217387 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1217387 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3010029 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3010029 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1419957 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1419957 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 664995 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 664995 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 831213 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 831213 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 120143 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 120143 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 187584 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 187584 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5261199 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5261199 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5926194 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5926194 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31550 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31550 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31201 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31201 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62751 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62751 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44196910500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 44196910500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29509664500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29509664500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16065417000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16065417000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 25593186000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 25593186000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1671520500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1671520500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4291457000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4291457000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1958500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1958500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99299761000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 99299761000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 115365178000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 115365178000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6087891000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6087891000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6087891000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6087891000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036781 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036781 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019428 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019428 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.710683 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.710683 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.828069 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.828069 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064758 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064758 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.101175 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.101175 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033741 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.033741 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037779 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.037779 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14683.217504 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14683.217504 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20782.083190 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20782.083190 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24158.703449 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24158.703449 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 30790.165698 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 30790.165698 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13912.758130 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13912.758130 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22877.521537 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22877.521537 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 6005280 # number of writebacks +system.cpu0.dcache.writebacks::total 6005280 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 217816 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 217816 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1084214 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1084214 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 111 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 111 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44378 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44378 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 58 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 58 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1302141 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1302141 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1302141 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1302141 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3174867 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3174867 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1512620 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1512620 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 727670 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 727670 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 807604 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 807604 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 120486 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 120486 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 202297 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 202297 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5495091 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5495091 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 6222761 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 6222761 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32770 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32770 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32733 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32733 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 65503 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 65503 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 46331358000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 46331358000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30906822000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 30906822000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18329110000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18329110000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 25186211500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 25186211500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1650103500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1650103500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4648318000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4648318000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1886000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1886000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 102424391500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 102424391500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 120753501500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 120753501500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6287102500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6287102500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6287102500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6287102500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036480 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036480 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019458 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019458 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.724077 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.724077 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.819216 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.819216 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058970 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058970 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099069 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099069 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033152 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033152 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037316 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.037316 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14593.165005 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14593.165005 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20432.641377 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20432.641377 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25188.766886 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25188.766886 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31186.338230 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31186.338230 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13695.396146 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13695.396146 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22977.691216 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22977.691216 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18873.979296 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18873.979296 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19466.993149 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19466.993149 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 192960.095087 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192960.095087 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97016.637185 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97016.637185 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 9611464 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.928699 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 231001616 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 9611976 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 24.032688 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 22883257000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.928699 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999861 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999861 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18639.253017 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18639.253017 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19405.132465 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19405.132465 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191855.431797 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191855.431797 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95981.901592 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95981.901592 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 9998472 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.981180 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 190986664 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 9998984 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 19.100607 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 18008070000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.981180 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999963 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999963 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 426 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 490839190 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 490839190 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 231001616 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 231001616 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 231001616 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 231001616 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 231001616 # number of overall hits -system.cpu0.icache.overall_hits::total 231001616 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 9611986 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 9611986 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 9611986 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 9611986 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 9611986 # number of overall misses -system.cpu0.icache.overall_misses::total 9611986 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 98657772000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 98657772000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 98657772000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 98657772000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 98657772000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 98657772000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 240613602 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 240613602 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 240613602 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 240613602 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 240613602 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 240613602 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039948 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.039948 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039948 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.039948 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039948 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.039948 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10264.036173 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10264.036173 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10264.036173 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10264.036173 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10264.036173 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10264.036173 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 411970312 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 411970312 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 190986664 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 190986664 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 190986664 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 190986664 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 190986664 # number of overall hits +system.cpu0.icache.overall_hits::total 190986664 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 9998995 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 9998995 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 9998995 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 9998995 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 9998995 # number of overall misses +system.cpu0.icache.overall_misses::total 9998995 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 104315202000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 104315202000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 104315202000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 104315202000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 104315202000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 104315202000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 200985659 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 200985659 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 200985659 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 200985659 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 200985659 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 200985659 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.049750 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.049750 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.049750 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.049750 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.049750 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.049750 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10432.568673 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10432.568673 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10432.568673 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10432.568673 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10432.568673 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10432.568673 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 9611464 # number of writebacks -system.cpu0.icache.writebacks::total 9611464 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9611986 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 9611986 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 9611986 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 9611986 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 9611986 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 9611986 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52284 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 52284 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52284 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 52284 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 93851779000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 93851779000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 93851779000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 93851779000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 93851779000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 93851779000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5161606000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5161606000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 5161606000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 5161606000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039948 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039948 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039948 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.039948 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039948 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.039948 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9764.036173 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9764.036173 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9764.036173 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9764.036173 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9764.036173 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9764.036173 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98722.477240 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98722.477240 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98722.477240 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98722.477240 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7434042 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7435434 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 1234 # number of redundant prefetches already in prefetch queue +system.cpu0.icache.writebacks::writebacks 9998472 # number of writebacks +system.cpu0.icache.writebacks::total 9998472 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9998995 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 9998995 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 9998995 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 9998995 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 9998995 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 9998995 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 4283 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 4283 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 4283 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 4283 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 99315705000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 99315705000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 99315705000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 99315705000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 99315705000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 99315705000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 427814500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 427814500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 427814500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 427814500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.049750 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.049750 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.049750 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.049750 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.049750 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.049750 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9932.568723 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9932.568723 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9932.568723 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9932.568723 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9932.568723 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9932.568723 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 99886.644875 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 99886.644875 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 99886.644875 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 99886.644875 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8169933 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8171403 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 1304 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 974582 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2611270 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15687.218696 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 13797239 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2627042 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.252005 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 5985886000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15319.283860 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 42.805682 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 26.313962 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 298.815192 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.935015 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002613 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001606 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.018238 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.957472 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 263 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 99 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15410 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 82 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 89 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 92 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 19 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 19 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 35 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2136 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5462 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5455 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2257 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.016052 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006042 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.940552 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 526460646 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 526460646 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 522971 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 177971 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 700942 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 3820006 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 3820006 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 11503050 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 11503050 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 900259 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 900259 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8923530 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 8923530 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2824509 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 2824509 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 229490 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 229490 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 522971 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 177971 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 8923530 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3724768 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 13349240 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 522971 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 177971 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 8923530 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3724768 # number of overall hits -system.cpu0.l2cache.overall_hits::total 13349240 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 20616 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9971 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 30587 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 242554 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 242554 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 187582 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 187582 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 283527 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 283527 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 688455 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 688455 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 970291 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 970291 # number of ReadSharedReq misses -system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 601723 # number of InvalidateReq misses -system.cpu0.l2cache.InvalidateReq_misses::total 601723 # number of InvalidateReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 20616 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9971 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 688455 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1253818 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1972860 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 20616 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9971 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 688455 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1253818 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1972860 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 693953500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 416737500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 1110691000 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 877430000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 877430000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 285529500 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 285529500 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1883000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1883000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 15417318498 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 15417318498 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 25525674000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 25525674000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 37603567991 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 37603567991 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.prefetcher.pfSpanPage 1047741 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 2932551 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15705.924224 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 14272950 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2948325 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 4.841037 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 1130072000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 15376.526197 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 37.361518 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 20.248621 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 271.787888 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.938509 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002280 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001236 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.016589 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.958614 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 362 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 46 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15366 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 176 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 107 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 73 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 218 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2130 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6262 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5229 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1527 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.022095 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.002808 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.937866 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 549297414 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 549297414 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 539317 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 165054 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 704371 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 3976191 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 3976191 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 12024318 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 12024318 # number of WritebackClean hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 971762 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 971762 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 9224160 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 9224160 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2947596 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 2947596 # number of ReadSharedReq hits +system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 209682 # number of InvalidateReq hits +system.cpu0.l2cache.InvalidateReq_hits::total 209682 # number of InvalidateReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 539317 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 165054 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 9224160 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3919358 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 13847889 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 539317 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 165054 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 9224160 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3919358 # number of overall hits +system.cpu0.l2cache.overall_hits::total 13847889 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 21966 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10468 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 32434 # number of ReadReq misses +system.cpu0.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses +system.cpu0.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 257791 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 257791 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 202293 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 202293 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 289245 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 289245 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 774834 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 774834 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1075153 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 1075153 # number of ReadSharedReq misses +system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 597922 # number of InvalidateReq misses +system.cpu0.l2cache.InvalidateReq_misses::total 597922 # number of InvalidateReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 21966 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10468 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 774834 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1364398 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 2171666 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 21966 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10468 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 774834 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1364398 # number of overall misses +system.cpu0.l2cache.overall_misses::total 2171666 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 715984000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 391759500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 1107743500 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 860565000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 860565000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 334549500 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 334549500 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1814999 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1814999 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 15808379497 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 15808379497 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 28621690500 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 28621690500 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 40818686990 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 40818686990 # number of ReadSharedReq miss cycles system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 104000 # number of InvalidateReq miss cycles system.cpu0.l2cache.InvalidateReq_miss_latency::total 104000 # number of InvalidateReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 693953500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 416737500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 25525674000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 53020886489 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 79657251489 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 693953500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 416737500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 25525674000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 53020886489 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 79657251489 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 543587 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 187942 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 731529 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3820006 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 3820006 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 11503050 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 11503050 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 242554 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 242554 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 187582 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 187582 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1183786 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1183786 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9611985 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 9611985 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3794800 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 3794800 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 831213 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::total 831213 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 543587 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 187942 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 9611985 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 4978586 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 15322100 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 543587 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 187942 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 9611985 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 4978586 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 15322100 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037926 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.053054 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.041812 # miss rate for ReadReq accesses +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 715984000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 391759500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 28621690500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 56627066487 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 86356500487 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 715984000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 391759500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 28621690500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 56627066487 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 86356500487 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 561283 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 175522 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 736805 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3976191 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 3976191 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 12024319 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 12024319 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 257791 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 257791 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 202293 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 202293 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1261007 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1261007 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9998994 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 9998994 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4022749 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 4022749 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 807604 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::total 807604 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 561283 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 175522 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 9998994 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 5283756 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 16019555 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 561283 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 175522 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 9998994 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 5283756 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 16019555 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.039135 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.059639 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.044020 # miss rate for ReadReq accesses +system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses +system.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.239509 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.239509 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.071625 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.071625 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.255690 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.255690 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.723910 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.723910 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037926 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.053054 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.071625 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.251842 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.128759 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037926 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.053054 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.071625 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.251842 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.128759 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33660.918704 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 41794.955371 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36312.518390 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3617.462503 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3617.462503 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1522.158309 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1522.158309 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 941500 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 941500 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 54376.897079 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 54376.897079 # average ReadExReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37076.750114 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37076.750114 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 38754.938458 # average ReadSharedReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 38754.938458 # average ReadSharedReq miss latency -system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 0.172837 # average InvalidateReq miss latency -system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 0.172837 # average InvalidateReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33660.918704 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 41794.955371 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37076.750114 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42287.546110 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 40376.535329 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33660.918704 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 41794.955371 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37076.750114 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42287.546110 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 40376.535329 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.229376 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.229376 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.077491 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.077491 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.267268 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.267268 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.740365 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.740365 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.039135 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.059639 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.077491 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.258225 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.135563 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.039135 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.059639 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.077491 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.258225 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.135563 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32595.101521 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 37424.484142 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34153.773818 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3338.227479 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3338.227479 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1653.786834 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1653.786834 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 453749.750000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 453749.750000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 54653.942149 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 54653.942149 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 36939.125671 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 36939.125671 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37965.468161 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37965.468161 # average ReadSharedReq miss latency +system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 0.173936 # average InvalidateReq miss latency +system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 0.173936 # average InvalidateReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32595.101521 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 37424.484142 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 36939.125671 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41503.334428 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 39765.093015 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32595.101521 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 37424.484142 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 36939.125671 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41503.334428 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 39765.093015 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 92 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 25 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 92 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.unused_prefetches 44451 # number of HardPF blocks evicted w/o reference -system.cpu0.l2cache.writebacks::writebacks 1620068 # number of writebacks -system.cpu0.l2cache.writebacks::total 1620068 # number of writebacks +system.cpu0.l2cache.unused_prefetches 48917 # number of HardPF blocks evicted w/o reference +system.cpu0.l2cache.writebacks::writebacks 1795601 # number of writebacks +system.cpu0.l2cache.writebacks::total 1795601 # number of writebacks system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 23 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 98 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 121 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8857 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 8857 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 6 # number of ReadCleanReq MSHR hits -system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 6 # number of ReadCleanReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 996 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 996 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 90 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 113 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 10129 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 10129 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 11 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 992 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 992 # number of ReadSharedReq MSHR hits system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 2 # number of InvalidateReq MSHR hits system.cpu0.l2cache.InvalidateReq_mshr_hits::total 2 # number of InvalidateReq MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 23 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 98 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 6 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 9853 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 9980 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 90 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 11 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 11121 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 11245 # number of demand (read+write) MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 23 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 98 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 6 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 9853 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 9980 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 20593 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9873 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 30466 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 782341 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 782341 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 242554 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 242554 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 187582 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 187582 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 274670 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 274670 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 688449 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 688449 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 969295 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 969295 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 601721 # number of InvalidateReq MSHR misses -system.cpu0.l2cache.InvalidateReq_mshr_misses::total 601721 # number of InvalidateReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 20593 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9873 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 688449 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1243965 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 1962880 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 20593 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9873 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 688449 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1243965 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 782341 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 2745221 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52284 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31550 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 83834 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 31201 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 31201 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52284 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 62751 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 115035 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 569758000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 355875500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 925633500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 38599728272 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 38599728272 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4476827494 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4476827494 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2879854497 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2879854497 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1583000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1583000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 12562742498 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 12562742498 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 21394767500 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 21394767500 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 31646923991 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 31646923991 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 19132934000 # number of InvalidateReq MSHR miss cycles -system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 19132934000 # number of InvalidateReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 569758000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 355875500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 21394767500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 44209666489 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 66530067489 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 569758000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 355875500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 21394767500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 44209666489 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 38599728272 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 105129795761 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4743334000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5835246500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10578580500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4743334000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5835246500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10578580500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.037884 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052532 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.041647 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 90 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 11 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 11121 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 11245 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 21943 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10378 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 32321 # number of ReadReq MSHR misses +system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses +system.cpu0.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 836449 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 836449 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 257791 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 257791 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 202293 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 202293 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 279116 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 279116 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 774823 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 774823 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1074161 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1074161 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 597920 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::total 597920 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 21943 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10378 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 774823 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1353277 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 2160421 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 21943 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10378 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 774823 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1353277 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 836449 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 2996870 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 4283 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32770 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 37053 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 32733 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 32733 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 4283 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 65503 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69786 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 583778500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 328079000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 911857500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 44903675775 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 44903675775 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4788332493 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4788332493 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3126512997 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3126512997 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1538999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1538999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 12740129497 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 12740129497 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 23972456500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 23972456500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 34238693990 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 34238693990 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18919213000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18919213000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 583778500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 328079000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 23972456500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 46978823487 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 71863137487 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 583778500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 328079000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 23972456500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 46978823487 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 44903675775 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 116766813262 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 393550500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6024557000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6418107500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 393550500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6024557000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6418107500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.039094 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.059126 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.043866 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses +system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses @@ -1305,137 +1311,138 @@ system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.232027 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.232027 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.071624 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.071624 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.255427 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.255427 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.723907 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.723907 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.037884 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052532 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.071624 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.249863 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.128108 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.037884 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052532 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.071624 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.249863 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.221344 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.221344 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.077490 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.077490 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.267022 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.267022 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.740363 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.740363 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.039094 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.059126 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.077490 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256120 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.134861 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.039094 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.059126 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.077490 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256120 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.179167 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27667.556937 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36045.325636 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30382.508370 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49338.751608 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49338.751608 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18457.034285 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18457.034285 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15352.509820 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15352.509820 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 791500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 791500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45737.585095 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45737.585095 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31076.764582 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31076.764582 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 32649.424572 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32649.424572 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31797.018884 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31797.018884 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27667.556937 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36045.325636 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31076.764582 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35539.317014 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33894.108396 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27667.556937 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36045.325636 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31076.764582 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35539.317014 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49338.751608 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38295.567374 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90722.477240 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184952.345483 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126184.847437 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90722.477240 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 92990.494175 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 91959.668796 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 31463839 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16044170 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3048 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 652134 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 652077 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 57 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 887708 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 14387458 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 31201 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 31200 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5457517 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 11506087 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1359708 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 999352 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 454749 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 343952 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 493156 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1220335 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1191280 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9611986 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4900402 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 909564 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 832554 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28940003 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18484921 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 391848 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1143553 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 48960325 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1233646912 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 690994144 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1503536 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4348696 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1930493288 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 5822948 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 111810824 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 22356517 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.042093 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.200815 # Request fanout histogram +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.187076 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28212.539835 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53683.698319 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53683.698319 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18574.475032 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18574.475032 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15455.369177 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15455.369177 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 384749.750000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 384749.750000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45644.568914 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45644.568914 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30939.268065 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31874.825087 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31874.825087 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31641.712938 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31641.712938 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34714.861397 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33263.487759 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34714.861397 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53683.698319 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38962.922403 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91886.644875 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183843.667989 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 173214.247159 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91886.644875 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91973.756927 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 91968.410569 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 32883708 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16795845 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3253 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 670544 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 670518 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 26 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 856926 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 14963454 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 32733 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 32733 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5790144 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 12027561 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1570458 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1077933 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 422877 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 361846 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 518769 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 52 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1292875 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1268569 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9998995 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5030713 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 860724 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 808588 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 30005026 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19391293 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 370102 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1186574 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 50952995 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1280111872 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 728610541 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1404176 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4490264 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 2014616853 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 6115163 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 122669856 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 23320085 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.043025 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.202918 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 21415512 95.79% 95.79% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 940948 4.21% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 57 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 22316772 95.70% 95.70% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 1003287 4.30% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 26 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 22356517 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 31390166976 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 23320085 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 32742058478 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 183129639 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 168693686 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 14498904485 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 15007733348 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8149348322 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8612588664 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 204016279 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 194673313 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 600088255 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 625412257 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 132997996 # Number of BP lookups -system.cpu1.branchPred.condPredicted 94215152 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6033479 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 99520242 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 69476937 # Number of BTB hits +system.cpu1.branchPred.lookups 106657949 # Number of BP lookups +system.cpu1.branchPred.condPredicted 68318136 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5862525 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 74400025 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 44246966 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 69.811865 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 15575496 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 1022946 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 3462102 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 2360825 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1101277 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 401735 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 59.471709 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 15290670 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 972922 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 3525874 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 2416919 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1108955 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 399586 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1465,63 +1472,63 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 271949 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 271949 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9428 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 76874 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 271949 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 271949 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 271949 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 86302 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 23685.366504 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21920.409810 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 15487.631024 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 85344 98.89% 98.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 718 0.83% 99.72% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 138 0.16% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 39 0.05% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 32 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 6 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 86302 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 114608944 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 114608944 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 114608944 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 76874 89.08% 89.08% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 9428 10.92% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 86302 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 271949 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 277975 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 277975 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11649 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 87046 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 277975 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 277975 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 277975 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 98695 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 24377.552054 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 22321.248739 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 18122.441336 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 97210 98.50% 98.50% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1115 1.13% 99.63% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 185 0.19% 99.81% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 71 0.07% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 61 0.06% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 31 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 10 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 98695 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -466757760 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -466757760 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -466757760 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 87046 88.20% 88.20% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 11649 11.80% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 98695 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 277975 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 271949 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 86302 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 277975 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 98695 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 86302 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 358251 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 98695 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 376670 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 86154833 # DTB read hits -system.cpu1.dtb.read_misses 225974 # DTB read misses -system.cpu1.dtb.write_hits 74805729 # DTB write hits -system.cpu1.dtb.write_misses 45975 # DTB write misses +system.cpu1.dtb.read_hits 85144665 # DTB read hits +system.cpu1.dtb.read_misses 232605 # DTB read misses +system.cpu1.dtb.write_hits 73861979 # DTB write hits +system.cpu1.dtb.write_misses 45370 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 40720 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 36571 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1221 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 7188 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 39387 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1059 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 7458 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10263 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 86380807 # DTB read accesses -system.cpu1.dtb.write_accesses 74851704 # DTB write accesses +system.cpu1.dtb.perms_faults 10689 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 85377270 # DTB read accesses +system.cpu1.dtb.write_accesses 73907349 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 160960562 # DTB hits -system.cpu1.dtb.misses 271949 # DTB misses -system.cpu1.dtb.accesses 161232511 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 159006644 # DTB hits +system.cpu1.dtb.misses 277975 # DTB misses +system.cpu1.dtb.accesses 159284619 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1551,908 +1558,889 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 60899 # Table walker walks requested -system.cpu1.itb.walker.walksLong 60899 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 513 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 50941 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 60899 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 60899 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 60899 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 51454 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 25618.018036 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 23516.416553 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 19409.340181 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 50489 98.12% 98.12% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 670 1.30% 99.43% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 212 0.41% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 46 0.09% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 12 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 7 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 13 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 51454 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 113972444 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 113972444 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 113972444 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 50941 99.00% 99.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 513 1.00% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 51454 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 63204 # Table walker walks requested +system.cpu1.itb.walker.walksLong 63204 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 495 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 53495 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 63204 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 63204 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 63204 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 53990 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 26610.918689 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23983.875694 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 21231.525332 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 52488 97.22% 97.22% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1070 1.98% 99.20% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 308 0.57% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 77 0.14% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 17 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 8 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 53990 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -467394260 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -467394260 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -467394260 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 53495 99.08% 99.08% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 495 0.92% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 53990 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60899 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60899 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 63204 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 63204 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 51454 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 51454 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 112353 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 236231380 # ITB inst hits -system.cpu1.itb.inst_misses 60899 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53990 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53990 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 117194 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 184175570 # ITB inst hits +system.cpu1.itb.inst_misses 63204 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 40720 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 26538 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 27907 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 178013 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 163451 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 236292279 # ITB inst accesses -system.cpu1.itb.hits 236231380 # DTB hits -system.cpu1.itb.misses 60899 # DTB misses -system.cpu1.itb.accesses 236292279 # DTB accesses -system.cpu1.numPwrStateTransitions 9440 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 4720 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 9937322156.794067 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 214697400239.899719 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3380 71.61% 71.61% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 1320 27.97% 99.58% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.11% 99.68% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.04% 99.75% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.77% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.79% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 10 0.21% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 184238774 # ITB inst accesses +system.cpu1.itb.hits 184175570 # DTB hits +system.cpu1.itb.misses 63204 # DTB misses +system.cpu1.itb.accesses 184238774 # DTB accesses +system.cpu1.numPwrStateTransitions 10058 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 5029 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 9328191006.192484 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 208028914614.416260 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3721 73.99% 73.99% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 1288 25.61% 99.60% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.10% 99.70% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.72% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.04% 99.76% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.78% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.80% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 10 0.20% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 11813594348000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 4720 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 452049545932 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 46904160580068 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 904105497 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 11813597602000 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 5029 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 399343597858 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 46911472570142 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 798693745 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 436062178 # Number of instructions committed -system.cpu1.committedOps 513430287 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 45590191 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 4720 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 93808990671 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.073341 # CPI: cycles per instruction -system.cpu1.ipc 0.482313 # IPC: instructions per cycle -system.cpu1.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction -system.cpu1.op_class_0::IntAlu 354600208 69.06% 69.06% # Class of committed instruction -system.cpu1.op_class_0::IntMult 1143323 0.22% 69.29% # Class of committed instruction -system.cpu1.op_class_0::IntDiv 59569 0.01% 69.30% # Class of committed instruction -system.cpu1.op_class_0::FloatAdd 0 0.00% 69.30% # Class of committed instruction -system.cpu1.op_class_0::FloatCmp 0 0.00% 69.30% # Class of committed instruction -system.cpu1.op_class_0::FloatCvt 0 0.00% 69.30% # Class of committed instruction -system.cpu1.op_class_0::FloatMult 0 0.00% 69.30% # Class of committed instruction -system.cpu1.op_class_0::FloatMultAcc 0 0.00% 69.30% # Class of committed instruction -system.cpu1.op_class_0::FloatDiv 0 0.00% 69.30% # Class of committed instruction -system.cpu1.op_class_0::FloatMisc 63096 0.01% 69.31% # Class of committed instruction -system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdAdd 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdAlu 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdCmp 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdCvt 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdMisc 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdMult 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdShift 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMisc 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.31% # Class of committed instruction -system.cpu1.op_class_0::MemRead 82989666 16.16% 85.48% # Class of committed instruction -system.cpu1.op_class_0::MemWrite 74191847 14.45% 99.93% # Class of committed instruction -system.cpu1.op_class_0::FloatMemRead 64253 0.01% 99.94% # Class of committed instruction -system.cpu1.op_class_0::FloatMemWrite 318324 0.06% 100.00% # Class of committed instruction +system.cpu1.committedInsts 398322797 # Number of instructions committed +system.cpu1.committedOps 474376671 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 19914789 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 5029 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 93823705865 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.005142 # CPI: cycles per instruction +system.cpu1.ipc 0.498718 # IPC: instructions per cycle +system.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu1.op_class_0::IntAlu 317550239 66.94% 66.94% # Class of committed instruction +system.cpu1.op_class_0::IntMult 1035693 0.22% 67.16% # Class of committed instruction +system.cpu1.op_class_0::IntDiv 58506 0.01% 67.17% # Class of committed instruction +system.cpu1.op_class_0::FloatAdd 0 0.00% 67.17% # Class of committed instruction +system.cpu1.op_class_0::FloatCmp 0 0.00% 67.17% # Class of committed instruction +system.cpu1.op_class_0::FloatCvt 0 0.00% 67.17% # Class of committed instruction +system.cpu1.op_class_0::FloatMult 0 0.00% 67.17% # Class of committed instruction +system.cpu1.op_class_0::FloatMultAcc 0 0.00% 67.17% # Class of committed instruction +system.cpu1.op_class_0::FloatDiv 0 0.00% 67.17% # Class of committed instruction +system.cpu1.op_class_0::FloatMisc 40875 0.01% 67.18% # Class of committed instruction +system.cpu1.op_class_0::FloatSqrt 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdAdd 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdAddAcc 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdAlu 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdCmp 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdCvt 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdMisc 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdMult 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdMultAcc 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdShift 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdSqrt 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMisc 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMult 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 67.18% # Class of committed instruction +system.cpu1.op_class_0::MemRead 82080782 17.30% 84.48% # Class of committed instruction +system.cpu1.op_class_0::MemWrite 73258893 15.44% 99.93% # Class of committed instruction +system.cpu1.op_class_0::FloatMemRead 48388 0.01% 99.94% # Class of committed instruction +system.cpu1.op_class_0::FloatMemWrite 303295 0.06% 100.00% # Class of committed instruction system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.op_class_0::total 513430287 # Class of committed instruction +system.cpu1.op_class_0::total 474376671 # Class of committed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 4720 # number of quiesce instructions executed -system.cpu1.tickCycles 704305988 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 199799509 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 5048947 # number of replacements -system.cpu1.dcache.tags.tagsinuse 416.228585 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 153590869 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5049459 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 30.417292 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8378525599500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 416.228585 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.812946 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.812946 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 5029 # number of quiesce instructions executed +system.cpu1.tickCycles 594788003 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 203905742 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 5132038 # number of replacements +system.cpu1.dcache.tags.tagsinuse 426.485512 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 151527650 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5132550 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.522878 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8373589022500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 426.485512 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.832980 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.832980 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 402 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 324622701 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 324622701 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 79356977 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 79356977 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 69837106 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 69837106 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 233112 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 233112 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 147127 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 147127 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1782955 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1782955 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1749534 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1749534 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 149341210 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 149341210 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 149574322 # number of overall hits -system.cpu1.dcache.overall_hits::total 149574322 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3104936 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3104936 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2154320 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2154320 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 600203 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 600203 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 416637 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 416637 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 162547 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 162547 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 194652 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 194652 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5675893 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5675893 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6276096 # number of overall misses -system.cpu1.dcache.overall_misses::total 6276096 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 47629871000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 47629871000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 40774475000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 40774475000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 9727566000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 9727566000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2415502000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2415502000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4643846000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4643846000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2158500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2158500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 98131912000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 98131912000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 98131912000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 98131912000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 82461913 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 82461913 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 71991426 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 71991426 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 833315 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 833315 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 563764 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 563764 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1945502 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1945502 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1944186 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1944186 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 155017103 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 155017103 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 155850418 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 155850418 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037653 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.037653 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029925 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.029925 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.720259 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.720259 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.739027 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.739027 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.083550 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.083550 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100120 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100120 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036615 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.036615 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040270 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.040270 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15340.049199 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15340.049199 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18926.842345 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18926.842345 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23347.820765 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23347.820765 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14860.329628 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14860.329628 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23857.170746 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23857.170746 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 320787282 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 320787282 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 78335043 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 78335043 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 68878259 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 68878259 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 235022 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 235022 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 144067 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 144067 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1753147 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1753147 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1717747 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1717747 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 147357369 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 147357369 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 147592391 # number of overall hits +system.cpu1.dcache.overall_hits::total 147592391 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3132424 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3132424 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2174513 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2174513 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 607658 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 607658 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 439275 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 439275 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 165234 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 165234 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199402 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 199402 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5746212 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5746212 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 6353870 # number of overall misses +system.cpu1.dcache.overall_misses::total 6353870 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 50822417500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 50822417500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 41404734500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 41404734500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10557419500 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 10557419500 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2612130500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2612130500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4773809500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4773809500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2292000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2292000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 102784571500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 102784571500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 102784571500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 102784571500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 81467467 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 81467467 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 71052772 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 71052772 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 842680 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 842680 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 583342 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 583342 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1918381 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1918381 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1917149 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1917149 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 153103581 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 153103581 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 153946261 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 153946261 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038450 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.038450 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030604 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030604 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.721102 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.721102 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.753032 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.753032 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086132 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086132 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104010 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104010 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.037532 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.037532 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041273 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.041273 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16224.629073 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16224.629073 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19040.922956 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 19040.922956 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24033.736270 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24033.736270 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15808.674365 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15808.674365 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23940.629984 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23940.629984 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17289.246291 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17289.246291 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15635.820740 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15635.820740 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17887.361535 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17887.361535 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16176.687830 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16176.687830 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 5048949 # number of writebacks -system.cpu1.dcache.writebacks::total 5048949 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 157294 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 157294 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 878635 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 878635 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 59 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 59 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39126 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39126 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 65 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 65 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1035988 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1035988 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1035988 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1035988 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2947642 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2947642 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1275685 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1275685 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 599894 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 599894 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 416578 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 416578 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 123421 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 123421 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 194587 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 194587 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4639905 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4639905 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5239799 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5239799 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6968 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6968 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7187 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7187 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14155 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14155 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41244047000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41244047000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23526690000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23526690000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13870615000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13870615000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9306680500 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9306680500 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1636714500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1636714500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4447799000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4447799000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1876000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1876000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 74077417500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 74077417500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 87948032500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 87948032500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 882714500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 882714500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 882714500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 882714500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035745 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035745 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017720 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017720 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.719889 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.719889 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.738923 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.738923 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063439 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063439 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100087 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100087 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029932 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029932 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033621 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033621 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13992.217169 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13992.217169 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18442.397614 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18442.397614 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23121.776514 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23121.776514 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22340.787320 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22340.787320 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13261.231881 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13261.231881 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22857.636944 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22857.636944 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 5132050 # number of writebacks +system.cpu1.dcache.writebacks::total 5132050 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 160382 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 160382 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 885255 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 885255 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 52 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 52 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 41570 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 41570 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 58 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 58 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1045689 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1045689 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1045689 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1045689 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2972042 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2972042 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1289258 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1289258 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 607473 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 607473 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 439223 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 439223 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 123664 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 123664 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 199344 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 199344 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4700523 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4700523 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5307996 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5307996 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5330 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5330 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5266 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5266 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10596 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10596 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 43920578500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 43920578500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24016685500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24016685500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14415408000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14415408000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10114952000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10114952000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1723729000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1723729000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4572940000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4572940000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2004000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2004000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 78052216000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 78052216000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 92467624000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 92467624000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 634565500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 634565500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 634565500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 634565500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036481 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036481 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018145 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018145 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.720882 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.720882 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.752943 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.752943 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064463 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064463 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103979 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103979 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030702 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030702 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034480 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034480 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14777.913132 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14777.913132 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18628.300542 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18628.300542 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23730.121339 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23730.121339 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23029.194737 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23029.194737 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13938.810001 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13938.810001 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22939.943013 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22939.943013 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15965.287544 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15965.287544 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16784.619505 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16784.619505 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 126681.185419 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 126681.185419 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 62360.614624 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 62360.614624 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 9106015 # number of replacements -system.cpu1.icache.tags.tagsinuse 507.214941 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 226941610 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 9106527 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 24.920764 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8368863514500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.214941 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990654 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.990654 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16605.006719 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16605.006719 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17420.439654 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17420.439654 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 119055.440901 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 119055.440901 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 59887.268781 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 59887.268781 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 8722673 # number of replacements +system.cpu1.icache.tags.tagsinuse 507.263120 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 175283400 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 8723185 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 20.093968 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8363988306000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.263120 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990748 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.990748 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 481202803 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 481202803 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 226941610 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 226941610 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 226941610 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 226941610 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 226941610 # number of overall hits -system.cpu1.icache.overall_hits::total 226941610 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 9106528 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 9106528 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 9106528 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 9106528 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 9106528 # number of overall misses -system.cpu1.icache.overall_misses::total 9106528 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 93334039500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 93334039500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 93334039500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 93334039500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 93334039500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 93334039500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 236048138 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 236048138 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 236048138 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 236048138 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 236048138 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 236048138 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038579 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.038579 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038579 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.038579 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038579 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.038579 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10249.135510 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10249.135510 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10249.135510 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10249.135510 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10249.135510 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10249.135510 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 376736355 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 376736355 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 175283400 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 175283400 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 175283400 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 175283400 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 175283400 # number of overall hits +system.cpu1.icache.overall_hits::total 175283400 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 8723185 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 8723185 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 8723185 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 8723185 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 8723185 # number of overall misses +system.cpu1.icache.overall_misses::total 8723185 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 89772651500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 89772651500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 89772651500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 89772651500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 89772651500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 89772651500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 184006585 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 184006585 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 184006585 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 184006585 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 184006585 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 184006585 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.047407 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.047407 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.047407 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.047407 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.047407 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.047407 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10291.269932 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10291.269932 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10291.269932 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10291.269932 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10291.269932 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10291.269932 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 9106015 # number of writebacks -system.cpu1.icache.writebacks::total 9106015 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9106528 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 9106528 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 9106528 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 9106528 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 9106528 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 9106528 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 8722673 # number of writebacks +system.cpu1.icache.writebacks::total 8722673 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8723185 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 8723185 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 8723185 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 8723185 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 8723185 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 8723185 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 95 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 95 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 88780776000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 88780776000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 88780776000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 88780776000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 88780776000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 88780776000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9602500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9602500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9602500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 9602500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038579 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038579 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038579 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.038579 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038579 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.038579 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9749.135565 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9749.135565 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9749.135565 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 9749.135565 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9749.135565 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 9749.135565 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101078.947368 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101078.947368 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101078.947368 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101078.947368 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7104941 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7105044 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 91 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 85411059000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 85411059000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 85411059000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 85411059000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 85411059000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 85411059000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9620500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9620500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9620500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 9620500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.047407 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.047407 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.047407 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.047407 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.047407 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.047407 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9791.269932 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9791.269932 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9791.269932 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9791.269932 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9791.269932 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9791.269932 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101268.421053 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101268.421053 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101268.421053 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101268.421053 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7056390 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7056554 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 145 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 891372 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 2193537 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13101.642441 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 12964075 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2209317 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 5.867911 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 902638 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 2217652 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13067.579403 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 12709221 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2233219 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 5.690987 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12819.727283 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 29.247108 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 16.647207 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 236.020843 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.782454 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001785 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001016 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014406 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.799661 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 358 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15375 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 152 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 121 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 74 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 36 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1753 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6630 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5167 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1593 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.021851 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002869 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.938416 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 486850576 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 486850576 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 506555 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 152150 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 658705 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 3098065 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 3098065 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 11055157 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 11055157 # number of WritebackClean hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 815552 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 815552 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8406399 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 8406399 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2722472 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 2722472 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 157346 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 157346 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 506555 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 152150 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 8406399 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3538024 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 12603128 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 506555 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 152150 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 8406399 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3538024 # number of overall hits -system.cpu1.l2cache.overall_hits::total 12603128 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 20442 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9977 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 30419 # number of ReadReq misses -system.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses -system.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 219088 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 219088 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 194583 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 194583 # number of SCUpgradeReq misses +system.cpu1.l2cache.tags.occ_blocks::writebacks 12703.923602 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 30.973948 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 15.153172 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 317.528681 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.775386 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001890 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000925 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.019380 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.797582 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 287 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 70 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15210 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 85 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 84 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 118 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 27 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 19 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 328 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1567 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5392 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5612 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2311 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017517 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004272 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.928345 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 477362276 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 477362276 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 532002 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 159372 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 691374 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 3201676 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 3201676 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 10651334 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 10651334 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 860878 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 860878 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8051210 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 8051210 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2757056 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 2757056 # number of ReadSharedReq hits +system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 173091 # number of InvalidateReq hits +system.cpu1.l2cache.InvalidateReq_hits::total 173091 # number of InvalidateReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 532002 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 159372 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 8051210 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3617934 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 12360518 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 532002 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 159372 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 8051210 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3617934 # number of overall hits +system.cpu1.l2cache.overall_hits::total 12360518 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 21589 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10425 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 32014 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 206575 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 206575 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 199341 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 199341 # number of SCUpgradeReq misses system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 241398 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 241398 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 700129 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 700129 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 948287 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 948287 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 259232 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 259232 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 20442 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9977 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 700129 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1189685 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1920233 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 20442 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9977 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 700129 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1189685 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1920233 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 617018000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 362407000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 979425000 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 937065000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 937065000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 273754000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 273754000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1804499 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1804499 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10806413996 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 10806413996 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 24362152500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 24362152500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 33291553995 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 33291553995 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 509000 # number of InvalidateReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::total 509000 # number of InvalidateReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 617018000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 362407000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 24362152500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 44097967991 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 69439545491 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 617018000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 362407000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 24362152500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 44097967991 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 69439545491 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 526997 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 162127 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 689124 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3098065 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 3098065 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 11055158 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 11055158 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 219089 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 219089 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 194584 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 194584 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 222346 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 222346 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 671975 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 671975 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 945788 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 945788 # number of ReadSharedReq misses +system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 266132 # number of InvalidateReq misses +system.cpu1.l2cache.InvalidateReq_misses::total 266132 # number of InvalidateReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 21589 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10425 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 671975 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1168134 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 1872123 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 21589 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10425 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 671975 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1168134 # number of overall misses +system.cpu1.l2cache.overall_misses::total 1872123 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 733662000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 446226000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 1179888000 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 870385500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 870385500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 311325000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 311325000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1930000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1930000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11310487497 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 11310487497 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 23715219500 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 23715219500 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 36332241992 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 36332241992 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 733662000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 446226000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 23715219500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 47642729489 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 72537836989 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 733662000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 446226000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 23715219500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 47642729489 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 72537836989 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 553591 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 169797 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 723388 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3201676 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 3201676 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 10651334 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 10651334 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 206575 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 206575 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 199341 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 199341 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1056950 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1056950 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9106528 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 9106528 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3670759 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 3670759 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 416578 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::total 416578 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 526997 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 162127 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 9106528 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4727709 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 14523361 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 526997 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 162127 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 9106528 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4727709 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 14523361 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.038790 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.061538 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.044142 # miss rate for ReadReq accesses -system.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses -system.cpu1.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999995 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999995 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999995 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999995 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1083224 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1083224 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 8723185 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 8723185 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3702844 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 3702844 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 439223 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::total 439223 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 553591 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 169797 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 8723185 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 4786068 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 14232641 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 553591 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 169797 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 8723185 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 4786068 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 14232641 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.038998 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.061397 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.044256 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.228391 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.228391 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.076882 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.076882 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.258335 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.258335 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.622289 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.622289 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.038790 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.061538 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.076882 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.251641 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.132217 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.038790 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.061538 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.076882 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.251641 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.132217 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 30183.837198 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 36324.245765 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32197.804004 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4277.116958 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4277.116958 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1406.875215 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1406.875215 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 601499.666667 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 601499.666667 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44765.963247 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44765.963247 # average ReadExReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 34796.662472 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 34796.662472 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35107.044592 # average ReadSharedReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35107.044592 # average ReadSharedReq miss latency -system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1.963492 # average InvalidateReq miss latency -system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1.963492 # average InvalidateReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 30183.837198 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 36324.245765 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34796.662472 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 37066.927793 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 36162.041529 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 30183.837198 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 36324.245765 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34796.662472 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 37066.927793 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 36162.041529 # average overall miss latency +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.205263 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.205263 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.077033 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.077033 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.255422 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.255422 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.605915 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.605915 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.038998 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.061397 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.077033 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.244070 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.131537 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.038998 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.061397 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.077033 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.244070 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.131537 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 33983.139562 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 42803.453237 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 36855.375773 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4213.411594 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4213.411594 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1561.771036 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1561.771036 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 643333.333333 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 643333.333333 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 50868.859782 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 50868.859782 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35291.818148 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35291.818148 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 38414.784277 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 38414.784277 # average ReadSharedReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 33983.139562 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 42803.453237 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35291.818148 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 40785.328985 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 38746.298715 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 33983.139562 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 42803.453237 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35291.818148 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 40785.328985 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 38746.298715 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.unused_prefetches 43998 # number of HardPF blocks evicted w/o reference -system.cpu1.l2cache.writebacks::writebacks 1082545 # number of writebacks -system.cpu1.l2cache.writebacks::total 1082545 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 17 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 90 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 6036 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 6036 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits -system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 724 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 724 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 3 # number of InvalidateReq MSHR hits -system.cpu1.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 17 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 90 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 6760 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 6871 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 17 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 90 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 6760 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 6871 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 20425 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9887 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 30312 # number of ReadReq MSHR misses -system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses -system.cpu1.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 721434 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 721434 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 219088 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 219088 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 194583 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 194583 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.unused_prefetches 44670 # number of HardPF blocks evicted w/o reference +system.cpu1.l2cache.writebacks::writebacks 1164875 # number of writebacks +system.cpu1.l2cache.writebacks::total 1164875 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 19 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 106 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 125 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 8703 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 8703 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits +system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 710 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 710 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 19 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 106 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 9413 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 9539 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 19 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 106 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 9413 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 9539 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 21570 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10319 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 31889 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 740053 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 740053 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 206575 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 206575 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 199341 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 199341 # number of SCUpgradeReq MSHR misses system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 235362 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 235362 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 700125 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 700125 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 947563 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 947563 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 259229 # number of InvalidateReq MSHR misses -system.cpu1.l2cache.InvalidateReq_mshr_misses::total 259229 # number of InvalidateReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 20425 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9887 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 700125 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1182925 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 1913362 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 20425 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9887 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 700125 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1182925 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 721434 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 2634796 # number of overall MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 213643 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 213643 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 671974 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 671974 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 945078 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 945078 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 266132 # number of InvalidateReq MSHR misses +system.cpu1.l2cache.InvalidateReq_mshr_misses::total 266132 # number of InvalidateReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 21570 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10319 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 671974 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1158721 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 1862584 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 21570 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10319 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 671974 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1158721 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 740053 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 2602637 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 6968 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 7063 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 7187 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 7187 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5330 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5425 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 5266 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 5266 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 14155 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 14250 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 494064000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 301606000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 795670000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 29780460685 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 29780460685 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4150846499 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4150846499 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2983943996 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2983943996 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1522499 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1522499 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8542642996 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8542642996 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 20161321500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 20161321500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 27488554995 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 27488554995 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6032275000 # number of InvalidateReq MSHR miss cycles -system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6032275000 # number of InvalidateReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 494064000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 301606000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 20161321500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 36031197991 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 56988189491 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 494064000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 301606000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 20161321500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 36031197991 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 29780460685 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 86768650176 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8842500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 826904500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 835747000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8842500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 826904500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 835747000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.038757 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.060983 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.043986 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses -system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10596 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10691 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 603790500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 382493500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 986284000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 37370954173 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 37370954173 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 3898631994 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 3898631994 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3073389997 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3073389997 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1642000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1642000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8857402997 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8857402997 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 19683346000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 19683346000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 30564768492 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 30564768492 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6658115000 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6658115000 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 603790500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 382493500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 19683346000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 39422171489 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 60091801489 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 603790500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 382493500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 19683346000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 39422171489 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 37370954173 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 97462755662 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8860500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 591855500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 600716000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8860500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 591855500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 600716000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.038964 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.060773 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.044083 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999995 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999995 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.222680 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.222680 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.076882 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.076882 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.258138 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.258138 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.622282 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.622282 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038757 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.060983 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.076882 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.250211 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.131744 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038757 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.060983 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.076882 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.250211 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.197229 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.197229 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.077033 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.077033 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.255230 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.255230 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.605915 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.605915 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038964 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.060773 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.077033 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.242103 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130867 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038964 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.060773 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.077033 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.242103 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181418 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24189.179927 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30505.310003 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26249.340195 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41279.535876 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41279.535876 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18946.023968 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18946.023968 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15335.070361 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15335.070361 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 507499.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 507499.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36295.761406 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36295.761406 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28796.745581 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28796.745581 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29009.738661 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29009.738661 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23270.062377 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23270.062377 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24189.179927 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30505.310003 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28796.745581 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 30459.410352 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29784.321781 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24189.179927 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30505.310003 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28796.745581 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 30459.410352 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41279.535876 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32931.828565 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93078.947368 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 118671.713548 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 118327.481240 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93078.947368 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 58417.838220 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 58648.912281 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 29139456 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14890637 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1736 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 592017 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 591980 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 37 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 780515 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 13649954 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 7187 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 7187 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4195318 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 11056894 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 1429217 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 912059 # Transaction distribution +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.182864 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30928.658785 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50497.672698 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50497.672698 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18872.719322 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18872.719322 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15417.751476 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15417.751476 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 547333.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 547333.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 41458.896369 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 41458.896369 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29291.826767 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32341.000946 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32341.000946 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 25018.092526 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 25018.092526 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34022.142939 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32262.599426 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34022.142939 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50497.672698 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37447.694650 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93268.421053 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 111042.307692 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 110731.059908 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93268.421053 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 55856.502454 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 56188.943972 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 28529787 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14583123 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1708 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 606717 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 606667 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 50 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 808882 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 13324164 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 5266 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 5266 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4382442 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 10653044 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 1404546 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 947399 # Transaction distribution system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 423433 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 346671 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 478761 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1089502 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1063784 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9106528 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4703864 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 480825 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 417736 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27319260 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16358508 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 344119 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1118457 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 45140344 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1165608768 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 632082996 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1297016 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4215976 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1803204756 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5174570 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 77236160 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 20377107 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.044844 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.206971 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::UpgradeReq 393688 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 362209 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 470974 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1116382 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1090257 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8723185 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4832581 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 501349 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 440463 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26169233 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16578335 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 358731 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1168114 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 44274413 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1116540992 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 640957756 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1358376 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4428728 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1763285852 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5350505 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 82373864 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 20276302 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.045824 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.209116 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 19463345 95.52% 95.52% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 913725 4.48% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 37 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 19347205 95.42% 95.42% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 929047 4.58% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 50 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 20377107 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 28962136490 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 20276302 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 28368994985 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 181919759 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 177802789 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 13662646557 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 13087773257 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7521057995 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7613339196 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 182080323 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 189022822 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 591562794 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 614644257 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40336 # Transaction distribution -system.iobus.trans_dist::ReadResp 40336 # Transaction distribution -system.iobus.trans_dist::WriteReq 136646 # Transaction distribution -system.iobus.trans_dist::WriteResp 136645 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47799 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40225 # Transaction distribution +system.iobus.trans_dist::ReadResp 40225 # Transaction distribution +system.iobus.trans_dist::WriteReq 136513 # Transaction distribution +system.iobus.trans_dist::WriteResp 136513 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47228 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2463,15 +2451,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122681 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231202 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231202 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122162 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231234 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231234 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353963 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47820 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353476 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2482,105 +2470,105 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155812 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338824 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338824 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155269 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338952 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338952 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496722 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42736003 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496307 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42338500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 316501 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 320000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 16500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25813003 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25881501 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 34441500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 34511002 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569849738 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 570151601 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92766000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92380000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147898000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147930000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115581 # number of replacements -system.iocache.tags.tagsinuse 11.283387 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115597 # number of replacements +system.iocache.tags.tagsinuse 11.280611 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115597 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115613 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9167357489000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.841167 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.442220 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240073 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.465139 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705212 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9162473233000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.844749 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.435862 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240297 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.464741 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705038 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040766 # Number of tag accesses -system.iocache.tags.data_accesses 1040766 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1040910 # Number of tag accesses +system.iocache.tags.data_accesses 1040910 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8873 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8910 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8889 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8926 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115601 # number of demand (read+write) misses -system.iocache.demand_misses::total 115641 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115617 # number of demand (read+write) misses +system.iocache.demand_misses::total 115657 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115601 # number of overall misses -system.iocache.overall_misses::total 115641 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5212500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1870801980 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1876014480 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115617 # number of overall misses +system.iocache.overall_misses::total 115657 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5196500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1980206431 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1985402931 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13212782258 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13212782258 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5581500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15083584238 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15089165738 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5581500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15083584238 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15089165738 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13190432670 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13190432670 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5565500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15170639101 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15176204601 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5565500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15170639101 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15176204601 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8873 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8910 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8889 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8926 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115601 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115641 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115617 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115657 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115601 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115641 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115617 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115657 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2594,53 +2582,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140878.378378 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 210842.103009 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 210551.569024 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140445.945946 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 222770.438857 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 222429.187878 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 123798.649445 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 123798.649445 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139537.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 130479.703791 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 130482.836866 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139537.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 130479.703791 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 130482.836866 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 43615 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 123589.242467 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 123589.242467 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139137.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 131214.605992 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 131217.346127 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139137.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 131214.605992 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 131217.346127 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 49271 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3535 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3583 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.338048 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.751326 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106693 # number of writebacks system.iocache.writebacks::total 106693 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8873 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8910 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8889 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8926 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115601 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115641 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115617 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115657 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115601 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115641 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3362500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1427151980 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1430514480 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115617 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115657 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3346500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1535756431 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1539102931 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7870696448 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7870696448 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3581500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9297848428 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9301429928 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3581500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9297848428 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9301429928 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7847855187 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7847855187 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3565500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9383611618 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9387177118 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3565500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9383611618 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9387177118 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2654,655 +2642,653 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90878.378378 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 160842.103009 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 160551.569024 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90445.945946 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 172770.438857 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 172429.187878 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 73745.375609 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 73745.375609 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89537.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 80430.519009 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 80433.669097 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89537.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 80430.519009 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 80433.669097 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1414426 # number of replacements -system.l2c.tags.tagsinuse 65137.583571 # Cycle average of tags in use -system.l2c.tags.total_refs 6994560 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1476169 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.738319 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8133240500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 11569.884492 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 195.527132 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 189.575172 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5571.537349 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 16752.169298 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 10126.474274 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 243.722413 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 247.067471 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3668.697792 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 7415.172357 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9157.755820 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.176542 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002984 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.002893 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.085015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.255618 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.154518 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003719 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003770 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.055980 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.113147 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.139736 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993921 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10627 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 250 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 50866 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 125 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 764 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9737 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 246 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1551 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4265 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 44783 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.162155 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003815 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.776154 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 76792424 # Number of tag accesses -system.l2c.tags.data_accesses 76792424 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2702608 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2702608 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 192434 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 150964 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 343398 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 50257 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 52778 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 103035 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 55782 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 52105 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 107887 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 13231 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5451 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 616225 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 581799 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 304510 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 10640 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4481 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 647147 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 570987 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 311044 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 3065515 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 124497 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 122676 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 247173 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 13231 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5451 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 616225 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 637581 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 304510 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 10640 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4481 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 647147 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 623092 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 311044 # number of demand (read+write) hits -system.l2c.demand_hits::total 3173402 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 13231 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5451 # number of overall hits -system.l2c.overall_hits::cpu0.inst 616225 # number of overall hits -system.l2c.overall_hits::cpu0.data 637581 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 304510 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 10640 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4481 # number of overall hits -system.l2c.overall_hits::cpu1.inst 647147 # number of overall hits -system.l2c.overall_hits::cpu1.data 623092 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 311044 # number of overall hits -system.l2c.overall_hits::total 3173402 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 19140 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 25859 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 44999 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 523 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 682 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1205 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 81279 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 45582 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 126861 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2187 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1999 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 72224 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 145719 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 234962 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1644 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1517 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 52978 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 99810 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 174436 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 787476 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 432248 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 85316 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 517564 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2187 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1999 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 72224 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 226998 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 234962 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1644 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1517 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 52978 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 145392 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 174436 # number of demand (read+write) misses -system.l2c.demand_misses::total 914337 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2187 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1999 # number of overall misses -system.l2c.overall_misses::cpu0.inst 72224 # number of overall misses -system.l2c.overall_misses::cpu0.data 226998 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 234962 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1644 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1517 # number of overall misses -system.l2c.overall_misses::cpu1.inst 52978 # number of overall misses -system.l2c.overall_misses::cpu1.data 145392 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 174436 # number of overall misses -system.l2c.overall_misses::total 914337 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 159938500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 143600000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 303538500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 6591000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 8923000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 15514000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 8642428000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4940577000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 13583005000 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 231505500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 211185500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 7798644500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 15829133000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 33053703122 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 165185000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 157137500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6014742000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 11671652500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 24159469102 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 99292357724 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 231505500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 211185500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 7798644500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 24471561000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 33053703122 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 165185000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 157137500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 6014742000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 16612229500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 24159469102 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 112875362724 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 231505500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 211185500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 7798644500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 24471561000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 33053703122 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 165185000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 157137500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 6014742000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 16612229500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 24159469102 # number of overall miss cycles -system.l2c.overall_miss_latency::total 112875362724 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 2702608 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 2702608 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 211574 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 176823 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 388397 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 50780 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 53460 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 104240 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 137061 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 97687 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 234748 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 15418 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7450 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 688449 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 727518 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 539472 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 12284 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5998 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 700125 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 670797 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 485480 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 3852991 # number of ReadSharedReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu0.data 556745 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu1.data 207992 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::total 764737 # number of InvalidateReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 15418 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 7450 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 688449 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 864579 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 539472 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 12284 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 5998 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 700125 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 768484 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 485480 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 4087739 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 15418 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 7450 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 688449 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 864579 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 539472 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 12284 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 5998 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 700125 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 768484 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 485480 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 4087739 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.090465 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.146242 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.115858 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.010299 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.012757 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.011560 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.593013 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.466613 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.540414 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.141847 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.268322 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.104908 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.200296 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.435541 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.133833 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.252918 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.075669 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.148793 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.359306 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.204380 # miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_miss_rate::cpu0.data 0.776384 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::cpu1.data 0.410189 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::total 0.676787 # miss rate for InvalidateReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.141847 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.268322 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.104908 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.262553 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.435541 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.133833 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.252918 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.075669 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.189193 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.359306 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.223678 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.141847 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.268322 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.104908 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.262553 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.435541 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.133833 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.252918 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.075669 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.189193 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.359306 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.223678 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 8356.243469 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5553.192312 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 6745.449899 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 12602.294455 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 13083.577713 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 12874.688797 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 106330.392844 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 108388.771884 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 107069.982106 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 105855.281207 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 105645.572786 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 107978.573604 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 108627.790473 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 140676.803577 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 100477.493917 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 103584.377060 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 113532.824946 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 116938.708546 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 138500.476404 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 126089.376342 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 105855.281207 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 105645.572786 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 107978.573604 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 107805.183306 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 140676.803577 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 100477.493917 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 103584.377060 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 113532.824946 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 114258.208842 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 138500.476404 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 123450.503178 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 105855.281207 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 105645.572786 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 107978.573604 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 107805.183306 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 140676.803577 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 100477.493917 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 103584.377060 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 113532.824946 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 114258.208842 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 138500.476404 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 123450.503178 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 159 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 73531.361845 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 73531.361845 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89137.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 81161.175415 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 81163.934029 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89137.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 81161.175415 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 81163.934029 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 1609900 # number of replacements +system.l2c.tags.tagsinuse 65157.020292 # Cycle average of tags in use +system.l2c.tags.total_refs 7484861 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1671770 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.477207 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 3329231500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 10396.250510 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 173.300313 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 163.171529 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4900.186700 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 12808.046984 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9631.875704 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 290.820455 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 308.484030 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3535.017429 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 11523.081214 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11426.785423 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.158634 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002644 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.002490 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074771 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.195435 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.146971 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004438 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.004707 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.053940 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.175828 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.174359 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994217 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 10593 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 251 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 51026 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 126 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 461 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 10006 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 251 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1785 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4614 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 44401 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.161636 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003830 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.778595 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 82772579 # Number of tag accesses +system.l2c.tags.data_accesses 82772579 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 2960473 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2960473 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 214775 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 151269 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 366044 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 56896 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 55474 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 112370 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 67148 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 51632 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 118780 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 14203 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 6226 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 695308 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 685955 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 328258 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 12341 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4684 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 616265 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 560248 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 290505 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 3213993 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 136732 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 122714 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 259446 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 14203 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 6226 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 695308 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 753103 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 328258 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 12341 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4684 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 616265 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 611880 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 290505 # number of demand (read+write) hits +system.l2c.demand_hits::total 3332773 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 14203 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 6226 # number of overall hits +system.l2c.overall_hits::cpu0.inst 695308 # number of overall hits +system.l2c.overall_hits::cpu0.data 753103 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 328258 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 12341 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 4684 # number of overall hits +system.l2c.overall_hits::cpu1.inst 616265 # number of overall hits +system.l2c.overall_hits::cpu1.data 611880 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 290505 # number of overall hits +system.l2c.overall_hits::total 3332773 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 20148 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 22532 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 42680 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 632 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 942 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1574 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 82382 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 53449 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 135831 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2080 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1618 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 79514 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 147489 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 271925 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2595 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2403 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 55709 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 138924 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 236410 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 938667 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 422083 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu1.data 110180 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 532263 # number of InvalidateReq misses +system.l2c.demand_misses::cpu0.dtb.walker 2080 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1618 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 79514 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 229871 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 271925 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 2595 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 2403 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 55709 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 192373 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 236410 # number of demand (read+write) misses +system.l2c.demand_misses::total 1074498 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 2080 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1618 # number of overall misses +system.l2c.overall_misses::cpu0.inst 79514 # number of overall misses +system.l2c.overall_misses::cpu0.data 229871 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 271925 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 2595 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 2403 # number of overall misses +system.l2c.overall_misses::cpu1.inst 55709 # number of overall misses +system.l2c.overall_misses::cpu1.data 192373 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 236410 # number of overall misses +system.l2c.overall_misses::total 1074498 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 146038500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 131790500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 277829000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 10352000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 8549500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 18901500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 8710976500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 5673543000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 14384519500 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 219387000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 170599500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 8581562500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 16399499000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 38998929895 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 257094000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 237286000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6184697999 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 15199077000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 32186234426 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 118434367320 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 219387000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 170599500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 8581562500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 25110475500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 38998929895 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 257094000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 237286000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 6184697999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 20872620000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 32186234426 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 132818886820 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 219387000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 170599500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 8581562500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 25110475500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 38998929895 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 257094000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 237286000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 6184697999 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 20872620000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 32186234426 # number of overall miss cycles +system.l2c.overall_miss_latency::total 132818886820 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 2960473 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 2960473 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 234923 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 173801 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 408724 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 57528 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 56416 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 113944 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 149530 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 105081 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 254611 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 16283 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7844 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 774822 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 833444 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 600183 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 14936 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7087 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 671974 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 699172 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 526915 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 4152660 # number of ReadSharedReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu0.data 558815 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu1.data 232894 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::total 791709 # number of InvalidateReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 16283 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 7844 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 774822 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 982974 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 600183 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 14936 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7087 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 671974 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 804253 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 526915 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 4407271 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 16283 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 7844 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 774822 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 982974 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 600183 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 14936 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7087 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 671974 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 804253 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 526915 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 4407271 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.085764 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.129643 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.104423 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.010986 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.016697 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.013814 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.550940 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.508646 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.533484 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.127741 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.206272 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.102622 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.176963 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.453070 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.173741 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.339072 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.082904 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.198698 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.448668 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.226040 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.755318 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu1.data 0.473091 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.672296 # miss rate for InvalidateReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.127741 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.206272 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.102622 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.233853 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.453070 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.173741 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.339072 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.082904 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.239195 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.448668 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.243801 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.127741 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.206272 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.102622 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.233853 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.453070 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.173741 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.339072 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.082904 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.239195 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.448668 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.243801 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 7248.287671 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5849.036925 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 6509.582943 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 16379.746835 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9075.902335 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 12008.576874 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 105738.832512 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 106148.721211 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 105900.122211 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 105474.519231 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 105438.504326 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 107925.176698 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 111191.336303 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 143417.964126 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 99072.832370 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 98745.734499 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 111017.932453 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 109405.696640 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 136145.824737 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 126172.931743 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 105474.519231 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 105438.504326 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 107925.176698 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 109237.248283 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 143417.964126 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 99072.832370 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 98745.734499 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 111017.932453 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 108500.777136 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 136145.824737 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 123610.175933 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 105474.519231 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 105438.504326 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 107925.176698 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 109237.248283 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 143417.964126 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 99072.832370 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 98745.734499 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 111017.932453 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 108500.777136 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 136145.824737 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 123610.175933 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 1362 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 6 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 13 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 26.500000 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 104.769231 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 1064634 # number of writebacks -system.l2c.writebacks::total 1064634 # number of writebacks -system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 107 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0.data 22 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 137 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.data 23 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 289 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 107 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 22 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 137 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 23 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 289 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 107 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 22 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 137 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 23 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 289 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 58693 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 58693 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 19140 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 25859 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 44999 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 523 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 682 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1205 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 81279 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 45582 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 126861 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2187 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1999 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 72117 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 145697 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 234962 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1644 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1517 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 52841 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 99787 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 174436 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 787187 # number of ReadSharedReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::cpu0.data 432248 # number of InvalidateReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::cpu1.data 85316 # number of InvalidateReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::total 517564 # number of InvalidateReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 2187 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 1999 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 72117 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 226976 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 234962 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 1644 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 1517 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 52841 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 145369 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 174436 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 914048 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 2187 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 1999 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 72117 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 226976 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 234962 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 1644 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 1517 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 52841 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 145369 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 174436 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 914048 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52284 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31550 # number of ReadReq MSHR uncacheable +system.l2c.writebacks::writebacks 1205906 # number of writebacks +system.l2c.writebacks::total 1205906 # number of writebacks +system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 171 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0.data 38 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 160 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.data 11 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 380 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 171 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 160 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 380 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 171 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 160 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 380 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 74973 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 74973 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 20148 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 22532 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 42680 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 632 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 942 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1574 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 82382 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 53449 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 135831 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2080 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1618 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 79343 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 147451 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 271925 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2595 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2403 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 55549 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 138913 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 236410 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 938287 # number of ReadSharedReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::cpu0.data 422083 # number of InvalidateReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::cpu1.data 110180 # number of InvalidateReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::total 532263 # number of InvalidateReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 2080 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 1618 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 79343 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 229833 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 271925 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 2595 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 2403 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 55549 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 192362 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 236410 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 1074118 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 2080 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 1618 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 79343 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 229833 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 271925 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 2595 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 2403 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 55549 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 192362 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 236410 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 1074118 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 4283 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32770 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 6966 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 90895 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 31201 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 7187 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 38388 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52284 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 62751 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5328 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 42476 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 32733 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5266 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 37999 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 4283 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 65503 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 14153 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 129283 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 389704500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 525466000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 915170500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 12566500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 16471000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 29037500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7829611555 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4484731054 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 12314342609 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 209631508 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 191194502 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 7068927036 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14369749705 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 30703963878 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 148744501 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 141966502 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5474322057 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 10671015209 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 22414941954 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 91394456852 # number of ReadSharedReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8929441001 # number of InvalidateReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1642247000 # number of InvalidateReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::total 10571688001 # number of InvalidateReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 209631508 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 191194502 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 7068927036 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 22199361260 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 30703963878 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 148744501 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 141966502 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 5474322057 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 15155746263 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 22414941954 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 103708799461 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 209631508 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 191194502 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 7068927036 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 22199361260 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 30703963878 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 148744501 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 141966502 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 5474322057 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 15155746263 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 22414941954 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 103708799461 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3645369500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5267143505 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6847500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 701418504 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 9620779009 # number of ReadReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3645369500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5267143505 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6847500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 701418504 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 9620779009 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10594 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 80475 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 406966500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 461692998 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 868659498 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 15287999 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 22938500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 38226499 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7887118579 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5139033541 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 13026152120 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 198586501 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 154419500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 7774295554 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14921316255 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 36279461370 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 231143002 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 213255501 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5614526528 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 13808714201 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 29821990735 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 109017709147 # number of ReadSharedReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8734501501 # number of InvalidateReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2122534500 # number of InvalidateReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::total 10857036001 # number of InvalidateReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 198586501 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 154419500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 7774295554 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 22808434834 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 36279461370 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 231143002 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 213255501 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 5614526528 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 18947747742 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 29821990735 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 122043861267 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 198586501 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 154419500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 7774295554 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 22808434834 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 36279461370 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 231143002 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 213255501 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 5614526528 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 18947747742 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 29821990735 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 122043861267 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 303607000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5434541500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6865000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 495854501 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6240868001 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 303607000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5434541500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6865000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 495854501 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 6240868001 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.090465 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.146242 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.115858 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.010299 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.012757 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.011560 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.593013 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.466613 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.540414 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.141847 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.268322 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.104753 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.200266 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.435541 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.133833 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.252918 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.075474 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.148759 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.359306 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.204305 # mshr miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.776384 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.410189 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::total 0.676787 # mshr miss rate for InvalidateReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.141847 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.268322 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.104753 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.262528 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.435541 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.133833 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.252918 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.075474 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.189163 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.359306 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.223607 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.141847 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.268322 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.104753 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.262528 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.435541 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.133833 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.252918 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.075474 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.189163 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.359306 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.223607 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20360.736677 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20320.430024 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20337.574168 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24027.724665 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24151.026393 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24097.510373 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 96330.067484 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 98388.202668 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 97069.569127 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 95853.455876 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 95645.073537 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 98020.259245 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 98627.629292 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130676.296073 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 90477.190389 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93583.719183 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 103599.895100 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 106937.929881 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128499.518184 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 116102.599321 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20658.143013 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19248.991983 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20425.856514 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 95853.455876 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 95645.073537 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 98020.259245 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 97804.883600 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130676.296073 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 90477.190389 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93583.719183 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 103599.895100 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 104257.071748 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128499.518184 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 113460.999270 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 95853.455876 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 95645.073537 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 98020.259245 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 97804.883600 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130676.296073 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 90477.190389 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93583.719183 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 103599.895100 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 104257.071748 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 128499.518184 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 113460.999270 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69722.467677 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166945.911410 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 72078.947368 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 100691.717485 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 105844.975070 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69722.467677 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83937.204268 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 72078.947368 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 49559.704939 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 74416.427597 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 3622014 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2135906 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 2993 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.085764 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.129643 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.104423 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.010986 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.016697 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.013814 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.550940 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.508646 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.533484 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.127741 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.206272 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.102402 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.176918 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.453070 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.173741 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.339072 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.082665 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.198682 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448668 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.225948 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.755318 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.473091 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.672296 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.127741 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.206272 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.102402 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.233814 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.453070 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.173741 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.339072 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.082665 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.239181 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448668 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.243715 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.127741 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.206272 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102402 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.233814 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.453070 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.173741 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.339072 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.082665 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.239181 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448668 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.243715 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20198.853484 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20490.546689 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20352.846720 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24189.871835 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24350.849257 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24286.212834 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 95738.372205 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 96148.357144 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 95899.699774 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 95474.279327 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 95438.504326 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 97983.382958 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 101195.083485 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133417.160504 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 89072.447784 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 88745.526841 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 101073.404166 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 99405.485455 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126145.216932 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 116188.020453 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20693.800748 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19264.244872 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20397.878494 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 95474.279327 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 95438.504326 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 97983.382958 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99239.164237 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133417.160504 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 89072.447784 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 88745.526841 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 101073.404166 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98500.471725 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126145.216932 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 113622.396484 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 95474.279327 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 95438.504326 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 97983.382958 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99239.164237 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133417.160504 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 89072.447784 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 88745.526841 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 101073.404166 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98500.471725 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126145.216932 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 113622.396484 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70886.528134 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165838.922795 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 72263.157895 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 93065.784722 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 146926.923463 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70886.528134 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82966.299253 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 72263.157895 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 46805.220030 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 77550.394545 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3927234 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2267569 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3039 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 90895 # Transaction distribution -system.membus.trans_dist::ReadResp 886992 # Transaction distribution -system.membus.trans_dist::WriteReq 38388 # Transaction distribution -system.membus.trans_dist::WriteResp 38387 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1171327 # Transaction distribution -system.membus.trans_dist::CleanEvict 257625 # Transaction distribution -system.membus.trans_dist::UpgradeReq 339183 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 279038 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 42476 # Transaction distribution +system.membus.trans_dist::ReadResp 989688 # Transaction distribution +system.membus.trans_dist::WriteReq 37999 # Transaction distribution +system.membus.trans_dist::WriteResp 37999 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1312599 # Transaction distribution +system.membus.trans_dist::CleanEvict 291937 # Transaction distribution +system.membus.trans_dist::UpgradeReq 286456 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 289177 # Transaction distribution system.membus.trans_dist::UpgradeResp 24 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 141595 # Transaction distribution -system.membus.trans_dist::ReadExResp 126059 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 796097 # Transaction distribution -system.membus.trans_dist::InvalidateReq 636810 # Transaction distribution -system.membus.trans_dist::InvalidateResp 29788 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122681 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 150791 # Transaction distribution +system.membus.trans_dist::ReadExResp 135122 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 947213 # Transaction distribution +system.membus.trans_dist::InvalidateReq 648655 # Transaction distribution +system.membus.trans_dist::InvalidateResp 27962 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122162 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 54 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4412900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4561541 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238275 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238275 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4799816 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155812 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24812 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4782183 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4929211 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238327 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238327 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5167538 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155269 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1388 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51812 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 129909760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 130118772 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7279744 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7279744 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 137398516 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 631660 # Total snoops (count) -system.membus.snoopTraffic 165184 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2322011 # Request fanout histogram -system.membus.snoop_fanout::mean 0.014128 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.118018 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 146129536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 146335817 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7281024 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7281024 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 153616841 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 586564 # Total snoops (count) +system.membus.snoopTraffic 164864 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2402773 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012913 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.112899 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2289206 98.59% 98.59% # Request fanout histogram -system.membus.snoop_fanout::1 32805 1.41% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2371746 98.71% 98.71% # Request fanout histogram +system.membus.snoop_fanout::1 31027 1.29% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2322011 # Request fanout histogram -system.membus.reqLayer0.occupancy 103411493 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2402773 # Request fanout histogram +system.membus.reqLayer0.occupancy 103148497 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 34812 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21687499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 20826497 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8057234059 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8952131044 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5202386097 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5789704061 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 79808698 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 78011284 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3345,79 +3331,79 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 12161965 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6407928 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2357892 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 209457 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 187271 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 22186 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47356210126000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 90897 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4728170 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38388 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38387 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3767242 # Transaction distribution +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 12820673 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6781255 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2351025 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 247233 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 222755 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 24478 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 42478 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4925290 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 37999 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 37999 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 4166379 # Transaction distribution system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2958537 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 681779 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 382073 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1063852 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 97 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 289918 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 289918 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4637675 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 890912 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 871981 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9721848 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8056306 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17778154 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 242672912 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 195596708 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 438269620 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2964469 # Total snoops (count) -system.toL2Bus.snoopTraffic 121867728 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 8426211 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.390204 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.493164 # Request fanout histogram +system.toL2Bus.trans_dist::CleanEvict 3160031 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 651791 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 401547 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1053338 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 94 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 305355 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 305355 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4883226 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 892239 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 875311 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10573421 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8142599 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 18716020 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 267921245 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 204226604 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 472147849 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3035429 # Total snoops (count) +system.toL2Bus.snoopTraffic 127161424 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 8824674 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.367843 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.487937 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5160452 61.24% 61.24% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3243573 38.49% 99.74% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 22186 0.26% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5603059 63.49% 63.49% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3197137 36.23% 99.72% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 24478 0.28% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8426211 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9265268057 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8824674 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9845744502 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 8336972 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 8465131 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4478456950 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4808552711 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4027071928 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4013025600 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index 6bb63026a..0eefafc2a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.688741 # Number of seconds simulated -sim_ticks 51688741391000 # Number of ticks simulated -final_tick 51688741391000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.643658 # Number of seconds simulated +sim_ticks 51643657651000 # Number of ticks simulated +final_tick 51643657651000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 269524 # Simulator instruction rate (inst/s) -host_op_rate 316717 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14692427127 # Simulator tick rate (ticks/s) -host_mem_usage 686428 # Number of bytes of host memory used -host_seconds 3518.05 # Real time elapsed on the host -sim_insts 948199503 # Number of instructions simulated -sim_ops 1114227092 # Number of ops (including micro ops) simulated +host_inst_rate 290656 # Simulator instruction rate (inst/s) +host_op_rate 346501 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16573581112 # Simulator tick rate (ticks/s) +host_mem_usage 686852 # Number of bytes of host memory used +host_seconds 3116.02 # Real time elapsed on the host +sim_insts 905689769 # Number of instructions simulated +sim_ops 1079705427 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 396416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 330752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10254464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 65885128 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 402816 # Number of bytes read from this memory -system.physmem.bytes_read::total 77269576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10254464 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10254464 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 94159808 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 481856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 390720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 7301696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 78480968 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 396608 # Number of bytes read from this memory +system.physmem.bytes_read::total 87051848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 7301696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7301696 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 106840192 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 94180388 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 6194 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 160226 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1029468 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6294 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1207350 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1471247 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 106860772 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 7529 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6105 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 114089 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1226278 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6197 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1360198 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1669378 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1473820 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 7669 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 6399 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 198389 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1274651 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7793 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1494901 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 198389 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 198389 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1821670 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1822068 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1821670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 7669 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 6399 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 198389 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1275050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7793 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3316969 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1207350 # Number of read requests accepted -system.physmem.writeReqs 1473820 # Number of write requests accepted -system.physmem.readBursts 1207350 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1473820 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 77222592 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 47808 # Total number of bytes read from write queue -system.physmem.bytesWritten 94178368 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 77269576 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 94180388 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 747 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2262 # Number of DRAM write bursts merged with an existing one +system.physmem.num_writes::total 1671951 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 9330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 7566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 141386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1519663 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7680 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1685625 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 141386 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 141386 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2068796 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2069194 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2068796 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 9330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 7566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 141386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1520062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7680 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3754820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1360198 # Number of read requests accepted +system.physmem.writeReqs 1671951 # Number of write requests accepted +system.physmem.readBursts 1360198 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1671951 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 86990528 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 62144 # Total number of bytes read from write queue +system.physmem.bytesWritten 106858944 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 87051848 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 106860772 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 971 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2249 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 73856 # Per bank write bursts -system.physmem.perBankRdBursts::1 76732 # Per bank write bursts -system.physmem.perBankRdBursts::2 71137 # Per bank write bursts -system.physmem.perBankRdBursts::3 69219 # Per bank write bursts -system.physmem.perBankRdBursts::4 73839 # Per bank write bursts -system.physmem.perBankRdBursts::5 75948 # Per bank write bursts -system.physmem.perBankRdBursts::6 69505 # Per bank write bursts -system.physmem.perBankRdBursts::7 70913 # Per bank write bursts -system.physmem.perBankRdBursts::8 66486 # Per bank write bursts -system.physmem.perBankRdBursts::9 126372 # Per bank write bursts -system.physmem.perBankRdBursts::10 74130 # Per bank write bursts -system.physmem.perBankRdBursts::11 75275 # Per bank write bursts -system.physmem.perBankRdBursts::12 69111 # Per bank write bursts -system.physmem.perBankRdBursts::13 75650 # Per bank write bursts -system.physmem.perBankRdBursts::14 65166 # Per bank write bursts -system.physmem.perBankRdBursts::15 73264 # Per bank write bursts -system.physmem.perBankWrBursts::0 92929 # Per bank write bursts -system.physmem.perBankWrBursts::1 92717 # Per bank write bursts -system.physmem.perBankWrBursts::2 91280 # Per bank write bursts -system.physmem.perBankWrBursts::3 89601 # Per bank write bursts -system.physmem.perBankWrBursts::4 92792 # Per bank write bursts -system.physmem.perBankWrBursts::5 94531 # Per bank write bursts -system.physmem.perBankWrBursts::6 90574 # Per bank write bursts -system.physmem.perBankWrBursts::7 91937 # Per bank write bursts -system.physmem.perBankWrBursts::8 87601 # Per bank write bursts -system.physmem.perBankWrBursts::9 94297 # Per bank write bursts -system.physmem.perBankWrBursts::10 91232 # Per bank write bursts -system.physmem.perBankWrBursts::11 93669 # Per bank write bursts -system.physmem.perBankWrBursts::12 91213 # Per bank write bursts -system.physmem.perBankWrBursts::13 96164 # Per bank write bursts -system.physmem.perBankWrBursts::14 87189 # Per bank write bursts -system.physmem.perBankWrBursts::15 93811 # Per bank write bursts +system.physmem.perBankRdBursts::0 83237 # Per bank write bursts +system.physmem.perBankRdBursts::1 85225 # Per bank write bursts +system.physmem.perBankRdBursts::2 82489 # Per bank write bursts +system.physmem.perBankRdBursts::3 80125 # Per bank write bursts +system.physmem.perBankRdBursts::4 87648 # Per bank write bursts +system.physmem.perBankRdBursts::5 94125 # Per bank write bursts +system.physmem.perBankRdBursts::6 89556 # Per bank write bursts +system.physmem.perBankRdBursts::7 88166 # Per bank write bursts +system.physmem.perBankRdBursts::8 78937 # Per bank write bursts +system.physmem.perBankRdBursts::9 92012 # Per bank write bursts +system.physmem.perBankRdBursts::10 85547 # Per bank write bursts +system.physmem.perBankRdBursts::11 87304 # Per bank write bursts +system.physmem.perBankRdBursts::12 77322 # Per bank write bursts +system.physmem.perBankRdBursts::13 84061 # Per bank write bursts +system.physmem.perBankRdBursts::14 80795 # Per bank write bursts +system.physmem.perBankRdBursts::15 82678 # Per bank write bursts +system.physmem.perBankWrBursts::0 101181 # Per bank write bursts +system.physmem.perBankWrBursts::1 102649 # Per bank write bursts +system.physmem.perBankWrBursts::2 102280 # Per bank write bursts +system.physmem.perBankWrBursts::3 101626 # Per bank write bursts +system.physmem.perBankWrBursts::4 106705 # Per bank write bursts +system.physmem.perBankWrBursts::5 111943 # Per bank write bursts +system.physmem.perBankWrBursts::6 107546 # Per bank write bursts +system.physmem.perBankWrBursts::7 108809 # Per bank write bursts +system.physmem.perBankWrBursts::8 101631 # Per bank write bursts +system.physmem.perBankWrBursts::9 107791 # Per bank write bursts +system.physmem.perBankWrBursts::10 102979 # Per bank write bursts +system.physmem.perBankWrBursts::11 104017 # Per bank write bursts +system.physmem.perBankWrBursts::12 98121 # Per bank write bursts +system.physmem.perBankWrBursts::13 104909 # Per bank write bursts +system.physmem.perBankWrBursts::14 102656 # Per bank write bursts +system.physmem.perBankWrBursts::15 104828 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 476 # Number of times write queue was full causing retry -system.physmem.totGap 51688739531000 # Total gap between requests +system.physmem.numWrRetry 458 # Number of times write queue was full causing retry +system.physmem.totGap 51643655791000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1207335 # Read request sizes (log2) +system.physmem.readPktSize::6 1360183 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1471247 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1136082 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 64384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 447 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1669378 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1282957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 70161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 871 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 444 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 571 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 532 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 87 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 74 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 445 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 945 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 269 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 186 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 159 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 95 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 95 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 78 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -160,186 +160,171 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 29717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 37973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 79220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 85555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 88116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 84810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 88690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 87321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 89133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 85642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 88726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 90107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 87724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 84525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 83639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 82667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 80351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 80396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 1082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1031 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 665465 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 257.565125 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 154.597276 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 293.769616 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 284377 42.73% 42.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 171033 25.70% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 61820 9.29% 77.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 34355 5.16% 82.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 24207 3.64% 86.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 15228 2.29% 88.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 11511 1.73% 90.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9122 1.37% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 53812 8.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 665465 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 77525 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 15.563805 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 141.518145 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 77523 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 77525 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 77525 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.981451 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.132244 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.585951 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 65037 83.89% 83.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 3875 5.00% 88.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 3091 3.99% 92.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 2418 3.12% 96.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 1125 1.45% 97.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 202 0.26% 97.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 259 0.33% 98.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 156 0.20% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 148 0.19% 98.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 64 0.08% 98.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 86 0.11% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 78 0.10% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 560 0.72% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 82 0.11% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 101 0.13% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 77 0.10% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 43 0.06% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 5 0.01% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 4 0.01% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.00% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.00% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.00% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 4 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 18 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 5 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 7 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 20 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 6 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 10 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 6 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 8 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 77525 # Writes before turning the bus around for reads -system.physmem.totQLat 38963077638 # Total ticks spent queuing -system.physmem.totMemAccLat 61586883888 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6033015000 # Total ticks spent in databus transfers -system.physmem.avgQLat 32291.55 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 31821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 39955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 90821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 97628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 100256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 96883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 101095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 99439 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 101345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 97950 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 101005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 102593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 99923 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 96951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 96056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 95043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 92451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 92535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1009 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 752315 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 257.670024 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 155.219861 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 291.691185 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 319843 42.51% 42.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 192789 25.63% 68.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 70379 9.35% 77.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 39533 5.25% 82.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 27835 3.70% 86.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 18762 2.49% 88.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 14354 1.91% 90.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 11626 1.55% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 57194 7.60% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 752315 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 89671 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.157342 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 22.777727 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 89658 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 7 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1279 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5632-5887 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 89671 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 89671 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.619966 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.881543 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.948219 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 81046 90.38% 90.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 5562 6.20% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 1304 1.45% 98.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 395 0.44% 98.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 213 0.24% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 159 0.18% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 654 0.73% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 203 0.23% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 30 0.03% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 3 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 5 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 17 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 4 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 4 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 32 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 13 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 6 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 10 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 89671 # Writes before turning the bus around for reads +system.physmem.totQLat 40684785332 # Total ticks spent queuing +system.physmem.totMemAccLat 66170291582 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6796135000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29932.30 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51041.55 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.49 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.82 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.49 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.82 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 48682.30 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.68 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.07 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.69 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.07 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.17 # Average write queue length when enqueuing -system.physmem.readRowHits 937085 # Number of row buffer hits during reads -system.physmem.writeRowHits 1075589 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.66 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.09 # Row buffer hit rate for writes -system.physmem.avgGap 19278426.78 # Average gap between requests -system.physmem.pageHitRate 75.15 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2387508900 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1268991075 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4149403860 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3843804420 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 50777254320.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 43920274980 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 3215166720 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 97172465130 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 73954032000 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 12292934061825 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 12573646841220 # Total energy per rank (pJ) -system.physmem_0.averagePower 243.256974 # Core power per rank (mW) -system.physmem_0.totalIdleTime 51583978414040 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 5941628250 # Time in different power states -system.physmem_0.memoryStateTime::REF 21591460000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 51178312983500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 192588592528 # Time in different power states -system.physmem_0.memoryStateTime::ACT 77208837210 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 213097889512 # Time in different power states -system.physmem_1.actEnergy 2363918340 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1256448600 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4465741560 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3837618720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 51996700080.000015 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 45282427920 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 3208431840 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 99358559340 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 75199350240 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 12290630942340 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 12577622785650 # Total energy per rank (pJ) -system.physmem_1.averagePower 243.333895 # Core power per rank (mW) -system.physmem_1.totalIdleTime 51581032449783 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 5840657750 # Time in different power states -system.physmem_1.memoryStateTime::REF 22110720000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 51167308964000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 195831815407 # Time in different power states -system.physmem_1.memoryStateTime::ACT 79757518717 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 217891715126 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 24.41 # Average write queue length when enqueuing +system.physmem.readRowHits 1052962 # Number of row buffer hits during reads +system.physmem.writeRowHits 1223619 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.28 # Row buffer hit rate for writes +system.physmem.avgGap 17032031.01 # Average gap between requests +system.physmem.pageHitRate 75.16 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2732670780 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1452445170 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4930676940 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4399097580 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 51881762400.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47976087180 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 3104058720 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 109980529290 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 71485388640 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 12273611587950 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 12571576503750 # Total energy per rank (pJ) +system.physmem_0.averagePower 243.429243 # Core power per rank (mW) +system.physmem_0.totalIdleTime 51530314812756 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 5413929000 # Time in different power states +system.physmem_0.memoryStateTime::REF 22045432000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 51102968874750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 186159553736 # Time in different power states +system.physmem_0.memoryStateTime::ACT 85883432494 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 241186429020 # Time in different power states +system.physmem_1.actEnergy 2638872600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1402590255 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4774203840 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4316585040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 51214263360.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 48316306500 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3067085280 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 106463182980 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 70942598400 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 12275647651350 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 12568805141895 # Total energy per rank (pJ) +system.physmem_1.averagePower 243.375580 # Core power per rank (mW) +system.physmem_1.totalIdleTime 51529660585796 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 5336166484 # Time in different power states +system.physmem_1.memoryStateTime::REF 21762952000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 51111446865750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 184746715790 # Time in different power states +system.physmem_1.memoryStateTime::ACT 86892179220 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 233472771756 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory @@ -356,30 +341,30 @@ system.realview.nvmem.bw_inst_read::total 14 # I system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 261998834 # Number of BP lookups -system.cpu.branchPred.condPredicted 182856277 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12304668 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 193336179 # Number of BTB lookups -system.cpu.branchPred.BTBHits 130354436 # Number of BTB hits +system.cpu.branchPred.lookups 230671595 # Number of BP lookups +system.cpu.branchPred.condPredicted 148977251 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12591272 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 161205478 # Number of BTB lookups +system.cpu.branchPred.BTBHits 94166388 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 67.423716 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 31812925 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2139415 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 7174940 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 5106056 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2068884 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 846506 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 58.413888 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 32707519 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2199358 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 7428890 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 5357971 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2070919 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 851352 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -409,65 +394,66 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 578626 # Table walker walks requested -system.cpu.dtb.walker.walksLong 578626 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 22326 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 190823 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 578626 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 578626 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 578626 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 213149 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 25594.731854 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 21754.484647 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 18075.189624 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 210684 98.84% 98.84% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 2067 0.97% 99.81% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 93 0.04% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 125 0.06% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 100 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 32 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 7 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 34 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 213149 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 316311704 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 316311704 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 316311704 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 190824 89.53% 89.53% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 22326 10.47% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 213150 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 578626 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 612824 # Table walker walks requested +system.cpu.dtb.walker.walksLong 612824 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 25045 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 213625 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 612824 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 612824 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 612824 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 238670 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 26656.848368 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 22869.063207 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 18178.269726 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 235680 98.75% 98.75% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 2495 1.05% 99.79% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 126 0.05% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 157 0.07% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 125 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 32 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 14 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 28 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::917504-983039 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 238670 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 411876000 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 411876000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 411876000 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 213626 89.51% 89.51% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 25045 10.49% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 238671 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 612824 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 578626 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213150 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 612824 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 238671 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 213150 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 791776 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 238671 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 851495 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 182986827 # DTB read hits -system.cpu.dtb.read_misses 476580 # DTB read misses -system.cpu.dtb.write_hits 162437421 # DTB write hits -system.cpu.dtb.write_misses 102046 # DTB write misses +system.cpu.dtb.read_hits 191427667 # DTB read hits +system.cpu.dtb.read_misses 503751 # DTB read misses +system.cpu.dtb.write_hits 170371453 # DTB write hits +system.cpu.dtb.write_misses 109073 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 47208 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 80100 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1397 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 15136 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 50563 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1145 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 82805 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 891 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 16210 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 23302 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 183463407 # DTB read accesses -system.cpu.dtb.write_accesses 162539467 # DTB write accesses +system.cpu.dtb.perms_faults 24062 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 191931418 # DTB read accesses +system.cpu.dtb.write_accesses 170480526 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 345424248 # DTB hits -system.cpu.dtb.misses 578626 # DTB misses -system.cpu.dtb.accesses 346002874 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 361799120 # DTB hits +system.cpu.dtb.misses 612824 # DTB misses +system.cpu.dtb.accesses 362411944 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -497,834 +483,833 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 136092 # Table walker walks requested -system.cpu.itb.walker.walksLong 136092 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1064 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 118204 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 136092 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 136092 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 136092 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 119268 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 28638.176208 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 24049.001367 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 28797.920728 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 116455 97.64% 97.64% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 2388 2.00% 99.64% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 112 0.09% 99.74% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 99 0.08% 99.82% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 27 0.02% 99.84% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 23 0.02% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 4 0.00% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 153 0.13% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 119268 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 315425204 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 315425204 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 315425204 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 118204 99.11% 99.11% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1064 0.89% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 119268 # Table walker page sizes translated +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 137744 # Table walker walks requested +system.cpu.itb.walker.walksLong 137744 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1060 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 119122 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 137744 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 137744 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 137744 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 120182 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 28731.482252 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24330.551658 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 24049.037609 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 116919 97.28% 97.28% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 2876 2.39% 99.68% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 146 0.12% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 107 0.09% 99.89% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 36 0.03% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 28 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 3 0.00% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 64 0.05% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 120182 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 411203500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 411203500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 411203500 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 119122 99.12% 99.12% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1060 0.88% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 120182 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136092 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 136092 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 137744 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 137744 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119268 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 119268 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 255360 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 453450761 # ITB inst hits -system.cpu.itb.inst_misses 136092 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 120182 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 120182 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 257926 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 367199991 # ITB inst hits +system.cpu.itb.inst_misses 137744 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 47208 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1111 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 57496 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 50563 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1145 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 59110 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 333218 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 331525 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 453586853 # ITB inst accesses -system.cpu.itb.hits 453450761 # DTB hits -system.cpu.itb.misses 136092 # DTB misses -system.cpu.itb.accesses 453586853 # DTB accesses -system.cpu.numPwrStateTransitions 33202 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 16601 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3037201042.152340 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 59610606886.622597 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 7303 43.99% 43.99% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9263 55.80% 99.79% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 367337735 # ITB inst accesses +system.cpu.itb.hits 367199991 # DTB hits +system.cpu.itb.misses 137744 # DTB misses +system.cpu.itb.accesses 367337735 # DTB accesses +system.cpu.numPwrStateTransitions 33588 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 16794 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3006267839.468917 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 59370181603.459618 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 7493 44.62% 44.62% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9266 55.17% 99.79% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.84% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::8.5e+11-9e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 1988777738856 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 16601 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 1268166890229 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50420574500771 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2536387791 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::max_value 1988777658384 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 16794 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 1156395554959 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50487262096041 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2312845645 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 948199503 # Number of instructions committed -system.cpu.committedOps 1114227092 # Number of ops (including micro ops) committed -system.cpu.discardedOps 98303819 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 7741 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 100842203450 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.674952 # CPI: cycles per instruction -system.cpu.ipc 0.373839 # IPC: instructions per cycle +system.cpu.committedInsts 905689769 # Number of instructions committed +system.cpu.committedOps 1079705427 # Number of ops (including micro ops) committed +system.cpu.discardedOps 38872378 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7934 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100975614107 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.553684 # CPI: cycles per instruction +system.cpu.ipc 0.391591 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction -system.cpu.op_class_0::IntAlu 772296777 69.31% 69.31% # Class of committed instruction -system.cpu.op_class_0::IntMult 2306158 0.21% 69.52% # Class of committed instruction -system.cpu.op_class_0::IntDiv 98958 0.01% 69.53% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 8 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 13 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 21 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::FloatMult 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 69.53% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 108924 0.01% 69.54% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction -system.cpu.op_class_0::MemRead 177418599 15.92% 85.46% # Class of committed instruction -system.cpu.op_class_0::MemWrite 161212850 14.47% 99.93% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 115060 0.01% 99.94% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 669723 0.06% 100.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 721452382 66.82% 66.82% # Class of committed instruction +system.cpu.op_class_0::IntMult 2371003 0.22% 67.04% # Class of committed instruction +system.cpu.op_class_0::IntDiv 100622 0.01% 67.05% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 8 0.00% 67.05% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 13 0.00% 67.05% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 21 0.00% 67.05% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 67.05% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 67.05% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 67.05% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 107773 0.01% 67.06% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.06% # Class of committed instruction +system.cpu.op_class_0::MemRead 185747611 17.20% 84.26% # Class of committed instruction +system.cpu.op_class_0::MemWrite 169152555 15.67% 99.93% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 112557 0.01% 99.94% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 660881 0.06% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 1114227092 # Class of committed instruction +system.cpu.op_class_0::total 1079705427 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16601 # number of quiesce instructions executed -system.cpu.tickCycles 1794953387 # Number of cycles that the object actually ticked -system.cpu.idleCycles 741434404 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 11118153 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.954086 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 329643971 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11118665 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.647801 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4655908500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.954086 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999910 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999910 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 16794 # number of quiesce instructions executed +system.cpu.tickCycles 1555844114 # Number of cycles that the object actually ticked +system.cpu.idleCycles 757001531 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 11832637 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.995677 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 345046750 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11833149 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.159335 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 456752500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.995677 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999992 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999992 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 398 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1383364255 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1383364255 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 168779255 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 168779255 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 151620030 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 151620030 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 521599 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 521599 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 337919 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 337919 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4018497 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4018497 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4332994 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4332994 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 320737204 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 320737204 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 321258803 # number of overall hits -system.cpu.dcache.overall_hits::total 321258803 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6105244 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6105244 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4304073 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4304073 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1482683 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1482683 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1242865 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1242865 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 316228 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 316228 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1449239878 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1449239878 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 176307264 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 176307264 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 158900158 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158900158 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 537417 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 537417 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 337852 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 337852 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4300418 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4300418 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4627725 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4627725 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 335545274 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 335545274 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 336082691 # number of overall hits +system.cpu.dcache.overall_hits::total 336082691 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6490291 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6490291 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4646590 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4646590 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1620869 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1620869 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1254011 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1254011 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 329077 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 329077 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 11652182 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 11652182 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 13134865 # number of overall misses -system.cpu.dcache.overall_misses::total 13134865 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 107444842500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 107444842500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 170230992500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 170230992500 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 27308613500 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 27308613500 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5074922000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5074922000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 12390892 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 12390892 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 14011761 # number of overall misses +system.cpu.dcache.overall_misses::total 14011761 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 114759870500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 114759870500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 196713087999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 196713087999 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 27879484500 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 27879484500 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5348350500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5348350500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 83000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 83000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 304984448500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 304984448500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 304984448500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 304984448500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 174884499 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 174884499 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 155924103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 155924103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2004282 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2004282 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1580784 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1580784 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4334725 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4334725 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4332995 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4332995 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 332389386 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 332389386 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 334393668 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 334393668 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.034910 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.034910 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027604 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027604 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.739758 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.739758 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786233 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.786233 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.072952 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.072952 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 339352442999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 339352442999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 339352442999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 339352442999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 182797555 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 182797555 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 163546748 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 163546748 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2158286 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2158286 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1591863 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1591863 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4629495 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4629495 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4627726 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4627726 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 347936166 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 347936166 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 350094452 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 350094452 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035505 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035505 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.028411 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.028411 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.750998 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.750998 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787763 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.787763 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.071083 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.071083 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.035056 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.035056 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039280 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039280 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17598.779426 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17598.779426 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39551.139700 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39551.139700 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 21972.308738 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 21972.308738 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16048.300593 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16048.300593 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.035613 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.035613 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.040023 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.040023 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17681.775825 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17681.775825 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42334.935512 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42334.935512 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 22232.248760 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 22232.248760 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16252.580703 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16252.580703 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26174.020325 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26174.020325 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23219.458175 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23219.458175 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 27387.248876 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 27387.248876 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24219.114428 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24219.114428 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 135 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 67.500000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 8530547 # number of writebacks -system.cpu.dcache.writebacks::total 8530547 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 315482 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 315482 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1904891 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1904891 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 158 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 158 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70720 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 70720 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2220531 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2220531 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2220531 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2220531 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5789762 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5789762 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2399182 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2399182 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1475215 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1475215 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1242707 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1242707 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 245508 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 245508 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 9058668 # number of writebacks +system.cpu.dcache.writebacks::total 9058668 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 331345 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 331345 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2059664 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2059664 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 161 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 161 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 73138 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 73138 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2391170 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2391170 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2391170 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2391170 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 6158946 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 6158946 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2586926 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2586926 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1613436 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1613436 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1253850 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1253850 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 255939 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 255939 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9431651 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9431651 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 10906866 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 10906866 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33696 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 33696 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33707 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 33707 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 94938379000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 94938379000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 89047691000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 89047691000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 25686251500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 25686251500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 26061179000 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 26061179000 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3474287500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3474287500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9999722 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9999722 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 11613158 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 11613158 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33608 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 33608 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33620 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 33620 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67228 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 67228 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 101472833000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 101472833000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 102652778000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 102652778000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 27900020500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 27900020500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 26619580500 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 26619580500 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3678632000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3678632000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 82000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 82000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 210047249000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 210047249000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 235733500500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 235733500500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6230847500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6230847500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6230847500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6230847500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033106 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033106 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015387 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015387 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.736032 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.736032 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786133 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786133 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056638 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056638 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230745191500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 230745191500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 258645212000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 258645212000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6209488500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6209488500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6209488500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6209488500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033693 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033693 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015818 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015818 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.747554 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.747554 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787662 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787662 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.055284 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.055284 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028375 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028375 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032617 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032617 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16397.630680 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16397.630680 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37115.854904 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37115.854904 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17411.869795 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17411.869795 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 20971.298142 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 20971.298142 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14151.422764 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14151.422764 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028740 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028740 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.033171 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.033171 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16475.681553 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16475.681553 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39681.373955 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39681.373955 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17292.300717 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17292.300717 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 21230.275153 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 21230.275153 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14373.081086 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14373.081086 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22270.464524 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22270.464524 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21613.312248 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21613.312248 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184913.565408 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184913.565408 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92441.693990 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92441.693990 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 24600209 # number of replacements -system.cpu.icache.tags.tagsinuse 511.926335 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 428505873 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24600721 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.418427 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 21430954500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.926335 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999856 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999856 # Average percentage of cache occupancy +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23075.160639 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23075.160639 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22271.737972 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22271.737972 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184762.214354 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184762.214354 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92364.617421 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92364.617421 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 25121901 # number of replacements +system.cpu.icache.tags.tagsinuse 511.967924 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 341735076 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 25122413 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 13.602797 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 17226930500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.967924 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999937 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999937 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 118 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 477707334 # Number of tag accesses -system.cpu.icache.tags.data_accesses 477707334 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 428505873 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 428505873 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 428505873 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 428505873 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 428505873 # number of overall hits -system.cpu.icache.overall_hits::total 428505873 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 24600731 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 24600731 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 24600731 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 24600731 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 24600731 # number of overall misses -system.cpu.icache.overall_misses::total 24600731 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 330486746500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 330486746500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 330486746500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 330486746500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 330486746500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 330486746500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 453106604 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 453106604 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 453106604 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 453106604 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 453106604 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 453106604 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054293 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.054293 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.054293 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.054293 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.054293 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.054293 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13434.021391 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13434.021391 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13434.021391 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13434.021391 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13434.021391 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13434.021391 # average overall miss latency +system.cpu.icache.tags.tag_accesses 391979921 # Number of tag accesses +system.cpu.icache.tags.data_accesses 391979921 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 341735076 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 341735076 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 341735076 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 341735076 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 341735076 # number of overall hits +system.cpu.icache.overall_hits::total 341735076 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 25122423 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 25122423 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 25122423 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 25122423 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 25122423 # number of overall misses +system.cpu.icache.overall_misses::total 25122423 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 337360587000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 337360587000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 337360587000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 337360587000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 337360587000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 337360587000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 366857499 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 366857499 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 366857499 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 366857499 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 366857499 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 366857499 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.068480 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.068480 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.068480 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.068480 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.068480 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.068480 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13428.664385 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13428.664385 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13428.664385 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13428.664385 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13428.664385 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13428.664385 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 24600209 # number of writebacks -system.cpu.icache.writebacks::total 24600209 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24600731 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 24600731 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 24600731 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 24600731 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 24600731 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 24600731 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52291 # number of ReadReq MSHR uncacheable -system.cpu.icache.ReadReq_mshr_uncacheable::total 52291 # number of ReadReq MSHR uncacheable -system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52291 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses::total 52291 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 305886016500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 305886016500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 305886016500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 305886016500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 305886016500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 305886016500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 4421533000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 4421533000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 4421533000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 4421533000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054293 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054293 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054293 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.054293 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054293 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.054293 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12434.021432 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12434.021432 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12434.021432 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12434.021432 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12434.021432 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12434.021432 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 84556.290757 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 84556.290757 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 84556.290757 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 84556.290757 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1601564 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65405.294347 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 69675530 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1664947 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 41.848497 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6255171000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9201.337762 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 431.981496 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 403.879639 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8049.770162 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 47318.325288 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.140401 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006592 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006163 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.122830 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.722020 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998006 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 257 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 63126 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 257 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 803 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5965 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56053 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003922 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.963226 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 583673795 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 583673795 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 921476 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 260236 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1181712 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 8530547 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 8530547 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 24596465 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 24596465 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 29651 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 29651 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1663600 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1663600 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24492767 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 24492767 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7181719 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 7181719 # number of ReadSharedReq hits -system.cpu.l2cache.InvalidateReq_hits::cpu.data 699060 # number of InvalidateReq hits -system.cpu.l2cache.InvalidateReq_hits::total 699060 # number of InvalidateReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 921476 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 260236 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 24492767 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 8845319 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 34519798 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 921476 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 260236 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 24492767 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 8845319 # number of overall hits -system.cpu.l2cache.overall_hits::total 34519798 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6194 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5168 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 11362 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 4020 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 4020 # number of UpgradeReq misses +system.cpu.icache.writebacks::writebacks 25121901 # number of writebacks +system.cpu.icache.writebacks::total 25121901 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25122423 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 25122423 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 25122423 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 25122423 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 25122423 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 25122423 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 4291 # number of ReadReq MSHR uncacheable +system.cpu.icache.ReadReq_mshr_uncacheable::total 4291 # number of ReadReq MSHR uncacheable +system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 4291 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::total 4291 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312238165000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 312238165000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312238165000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 312238165000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312238165000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 312238165000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 366344000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 366344000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 366344000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 366344000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.068480 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.068480 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.068480 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.068480 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.068480 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.068480 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12428.664425 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12428.664425 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12428.664425 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12428.664425 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12428.664425 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12428.664425 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 85374.970869 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 85374.970869 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 85374.970869 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 85374.970869 # average overall mshr uncacheable latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 1823253 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65445.001874 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 72021344 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1886697 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 38.173244 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2050526000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 9044.623983 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 456.585654 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 458.430752 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7955.769070 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 47529.592416 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.138010 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006967 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006995 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.121395 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.725244 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998611 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 236 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 63208 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 233 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 882 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5962 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56005 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003601 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.964478 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 604501194 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 604501194 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1016248 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 265268 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1281516 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 9058668 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 9058668 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 25118324 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 25118324 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 31922 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 31922 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1691397 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1691397 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 25012596 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 25012596 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7660453 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 7660453 # number of ReadSharedReq hits +system.cpu.l2cache.InvalidateReq_hits::cpu.data 687915 # number of InvalidateReq hits +system.cpu.l2cache.InvalidateReq_hits::total 687915 # number of InvalidateReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 1016248 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 265268 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 25012596 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 9351850 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 35645962 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 1016248 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 265268 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 25012596 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 9351850 # number of overall hits +system.cpu.l2cache.overall_hits::total 35645962 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7529 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6105 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 13634 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 3989 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 3989 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 702193 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 702193 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 107963 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 107963 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 328484 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 328484 # number of ReadSharedReq misses -system.cpu.l2cache.InvalidateReq_misses::cpu.data 543647 # number of InvalidateReq misses -system.cpu.l2cache.InvalidateReq_misses::total 543647 # number of InvalidateReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 6194 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5168 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 107963 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1030677 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1150002 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 6194 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 5168 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 107963 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1030677 # number of overall misses -system.cpu.l2cache.overall_misses::total 1150002 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 927255500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 692143500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1619399000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 72892500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 72892500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_misses::cpu.data 859845 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 859845 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 109826 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 109826 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 367641 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 367641 # number of ReadSharedReq misses +system.cpu.l2cache.InvalidateReq_misses::cpu.data 565935 # number of InvalidateReq misses +system.cpu.l2cache.InvalidateReq_misses::total 565935 # number of InvalidateReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 7529 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 6105 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 109826 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1227486 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1350946 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 7529 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 6105 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 109826 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1227486 # number of overall misses +system.cpu.l2cache.overall_misses::total 1350946 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 877005000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 644825000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1521830000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 72113000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 72113000 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 80500 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 80500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 67521066500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 67521066500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11586638500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 11586638500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 37187085000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 37187085000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 927255500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 692143500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11586638500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 104708151500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 117914189000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 927255500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 692143500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11586638500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 104708151500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 117914189000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 927670 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 265404 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1193074 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 8530547 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 8530547 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 24596465 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 24596465 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 33671 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 33671 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 80528268500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 80528268500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11692993000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 11692993000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 40327835000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 40327835000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 877005000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 644825000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11692993000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 120856103500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 134070926500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 877005000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 644825000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11692993000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 120856103500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 134070926500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 1023777 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 271373 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1295150 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 9058668 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 9058668 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 25118324 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 25118324 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 35911 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 35911 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2365793 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2365793 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 24600730 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 24600730 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7510203 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7510203 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1242707 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::total 1242707 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 927670 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 265404 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 24600730 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9875996 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 35669800 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 927670 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 265404 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 24600730 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9875996 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 35669800 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006677 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.019472 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.009523 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.119391 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.119391 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2551242 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2551242 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 25122422 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 25122422 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 8028094 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 8028094 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1253850 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::total 1253850 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 1023777 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 271373 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 25122422 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 10579336 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 36996908 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 1023777 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 271373 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 25122422 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 10579336 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 36996908 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.007354 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022497 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.010527 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.111080 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.111080 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.296811 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.296811 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004389 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004389 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043738 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043738 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.437470 # miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::total 0.437470 # miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006677 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.019472 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004389 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.104362 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.032240 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006677 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.019472 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004389 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.104362 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.032240 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 149702.211818 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 133928.695820 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 142527.635980 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 18132.462687 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 18132.462687 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.337030 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.337030 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004372 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004372 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.045794 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.045794 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.451358 # miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.451358 # miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.007354 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022497 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004372 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.116027 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.036515 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.007354 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022497 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004372 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.116027 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.036515 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 116483.596759 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 105622.440622 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 111620.214170 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 18077.964402 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 18077.964402 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80500 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80500 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96157.418972 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96157.418972 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107320.457008 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107320.457008 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 113208.208010 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 113208.208010 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 149702.211818 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 133928.695820 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107320.457008 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 101591.625213 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 102533.899071 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 149702.211818 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 133928.695820 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107320.457008 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 101591.625213 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 102533.899071 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 93654.401084 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 93654.401084 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 106468.349935 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 106468.349935 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 109693.518949 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 109693.518949 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 116483.596759 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 105622.440622 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 106468.349935 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98458.233740 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 99242.254317 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 116483.596759 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 105622.440622 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 106468.349935 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98458.233740 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 99242.254317 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1364616 # number of writebacks -system.cpu.l2cache.writebacks::total 1364616 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1562747 # number of writebacks +system.cpu.l2cache.writebacks::total 1562747 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 22 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 22 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 23 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 23 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 6194 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5168 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 11362 # number of ReadReq MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 3 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 3 # number of CleanEvict MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4020 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 4020 # number of UpgradeReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7529 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6105 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 13634 # number of ReadReq MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3989 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 3989 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 702193 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 702193 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 107961 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 107961 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 328463 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 328463 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 543647 # number of InvalidateReq MSHR misses -system.cpu.l2cache.InvalidateReq_mshr_misses::total 543647 # number of InvalidateReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 6194 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5168 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 107961 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1030656 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1149979 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 6194 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5168 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 107961 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1030656 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1149979 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 52291 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33696 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 85987 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33707 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33707 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 52291 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 119694 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 865315500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 640463500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1505779000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 76760000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 76760000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 859845 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 859845 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 109824 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 109824 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 367619 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 367619 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 565935 # number of InvalidateReq MSHR misses +system.cpu.l2cache.InvalidateReq_mshr_misses::total 565935 # number of InvalidateReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7529 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6105 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 109824 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1227464 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1350922 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7529 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6105 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 109824 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1227464 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1350922 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 4291 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33608 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 37899 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33620 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33620 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 4291 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67228 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 71519 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 801715000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 583775000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1385490000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 76139500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 76139500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 70500 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 70500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60499136001 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60499136001 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10506850003 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10506850003 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33899524045 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33899524045 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 11224464501 # number of InvalidateReq MSHR miss cycles -system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 11224464501 # number of InvalidateReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 865315500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 640463500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10506850003 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 94398660046 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 106411289049 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 865315500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 640463500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10506850003 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 94398660046 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 106411289049 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 3611009000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5809544500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 9420553500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3611009000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5809544500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9420553500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006677 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.019472 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.009523 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 71929817502 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 71929817502 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10594574503 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10594574503 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 36650353047 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 36650353047 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 11657372001 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 11657372001 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 801715000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 583775000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10594574503 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 108580170549 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 120560235052 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 801715000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 583775000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10594574503 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 108580170549 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 120560235052 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 299820000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5789264500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6089084500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 299820000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5789264500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6089084500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007354 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.022497 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010527 # mshr miss rate for ReadReq accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.119391 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.119391 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.111080 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.111080 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.296811 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.296811 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004389 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004389 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043736 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043736 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.437470 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.437470 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006677 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.019472 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004389 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.104360 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.032240 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006677 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.019472 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004389 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.104360 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.032240 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 139702.211818 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123928.695820 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 132527.635980 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19094.527363 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19094.527363 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.337030 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.337030 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004372 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004372 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.045792 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.045792 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.451358 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.451358 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007354 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.022497 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004372 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.116025 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.036514 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007354 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.022497 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004372 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.116025 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.036514 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 106483.596759 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 95622.440622 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 101620.214170 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19087.365254 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19087.365254 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86157.418261 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86157.418261 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97320.791795 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97320.791795 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 103206.522637 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 103206.522637 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20646.604324 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20646.604324 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 139702.211818 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123928.695820 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97320.791795 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91590.850920 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 92533.245432 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 139702.211818 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123928.695820 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97320.791795 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91590.850920 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 92533.245432 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69056.032587 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172410.508666 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 109557.880842 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69056.032587 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86191.185852 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 78705.311043 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 72189026 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 36469595 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4452 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1946 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1946 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83654.399923 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 83654.399923 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96468.663525 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96468.663525 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 99696.569130 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 99696.569130 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20598.429150 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20598.429150 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 106483.596759 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 95622.440622 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96468.663525 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88458.945068 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 89242.928202 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 106483.596759 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 95622.440622 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96468.663525 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88458.945068 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89242.928202 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69871.824749 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172258.524756 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 160666.099369 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69871.824749 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86113.888558 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 85139.396524 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 74678701 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 37723093 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4208 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1985 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1985 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1780354 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 33892071 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 9895163 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 24600209 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2824554 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 33674 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1826986 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 34978302 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33620 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33620 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 10621415 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 25121901 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 3034475 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 35914 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 33675 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2365793 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2365793 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 24600731 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7513010 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1271678 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1242738 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73906251 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 33558527 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 672286 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2215155 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 110352219 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3152206656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1178259346 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2123232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7421360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 4340010594 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2135457 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 91396008 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 39200512 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018468 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.134637 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 35915 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2551242 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2551242 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 25122423 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 8030982 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1284314 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1253880 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 75375327 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35706122 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 683214 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2401023 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 114165686 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3215911232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1257073518 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2170984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 8190216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 4483345950 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2351379 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 104018568 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 40708735 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018149 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.133491 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 38476553 98.15% 98.15% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 723959 1.85% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 39969899 98.19% 98.19% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 738836 1.81% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 39200512 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 69790374998 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 40708735 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 72100713496 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1501881 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1533365 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 36983722099 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 37694541038 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 15503705051 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 16565349400 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 406910942 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 411872936 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1287502964 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1377265960 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40334 # Transaction distribution -system.iobus.trans_dist::ReadResp 40334 # Transaction distribution -system.iobus.trans_dist::WriteReq 136571 # Transaction distribution -system.iobus.trans_dist::WriteResp 136571 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40237 # Transaction distribution +system.iobus.trans_dist::ReadResp 40237 # Transaction distribution +system.iobus.trans_dist::WriteReq 136485 # Transaction distribution +system.iobus.trans_dist::WriteResp 136485 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47478 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -1337,13 +1322,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231026 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231026 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122360 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231004 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231004 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353810 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353444 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47498 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1356,19 +1341,19 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155490 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334448 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492456 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 37695500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492024 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 37126500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 339500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 334500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1378,81 +1363,81 @@ system.iobus.reqLayer13.occupancy 11000 # La system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25148500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25225000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36444000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36490500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569308376 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569036756 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92542000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147786000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147764000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115495 # number of replacements -system.iocache.tags.tagsinuse 10.448162 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115484 # number of replacements +system.iocache.tags.tagsinuse 10.444243 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115511 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13141692173000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.519394 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.928768 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219962 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433048 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653010 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13137487927000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 5.867221 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 4.577022 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.366701 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.286064 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.652765 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039974 # Number of tag accesses -system.iocache.tags.data_accesses 1039974 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039875 # Number of tag accesses +system.iocache.tags.data_accesses 1039875 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8849 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8886 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8838 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8875 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115513 # number of demand (read+write) misses -system.iocache.demand_misses::total 115553 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115502 # number of demand (read+write) misses +system.iocache.demand_misses::total 115542 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115513 # number of overall misses -system.iocache.overall_misses::total 115553 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5085500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 2011459152 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 2016544652 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115502 # number of overall misses +system.iocache.overall_misses::total 115542 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 2014766150 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 2019852150 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13390572724 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13390572724 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5436500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15402031876 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15407468376 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5436500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15402031876 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15407468376 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13376583606 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13376583606 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15391349756 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15396786756 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15391349756 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15396786756 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8849 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8886 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8838 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8875 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115513 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115553 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115502 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115542 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115513 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115553 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115502 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115542 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1466,53 +1451,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 227309.204656 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 226935.027234 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 227966.298936 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 227588.974648 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125539.757781 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125539.757781 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 133335.917827 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 133336.809741 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 133335.917827 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 133336.809741 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 51202 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125408.606521 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125408.606521 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 133256.131980 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 133257.055928 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 133256.131980 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 133257.055928 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 51744 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3365 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3369 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 15.216048 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 15.358860 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8849 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8886 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8838 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8875 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115513 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115553 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115502 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115542 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115513 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115553 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3235500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1569009152 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1572244652 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115502 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115542 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1572866150 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1576102150 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8051866391 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8051866391 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3436500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9620875543 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9624312043 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3436500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9620875543 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9624312043 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8037847459 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8037847459 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9610713609 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9614150609 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9610713609 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9614150609 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1526,96 +1511,96 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87445.945946 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 177309.204656 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 176935.027234 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 177966.298936 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 177588.974648 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75488.134619 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75488.134619 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 83288.249314 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 83289.157728 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 83288.249314 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 83289.157728 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 3529625 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1749962 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3622 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75356.703846 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75356.703846 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 83208.200802 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 83209.141343 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 83208.200802 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 83209.141343 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 3974449 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1973040 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3773 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 85987 # Transaction distribution -system.membus.trans_dist::ReadResp 542659 # Transaction distribution -system.membus.trans_dist::WriteReq 33707 # Transaction distribution -system.membus.trans_dist::WriteResp 33707 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1471247 # Transaction distribution -system.membus.trans_dist::CleanEvict 244702 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4583 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 37899 # Transaction distribution +system.membus.trans_dist::ReadResp 537851 # Transaction distribution +system.membus.trans_dist::WriteReq 33620 # Transaction distribution +system.membus.trans_dist::WriteResp 33620 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1669378 # Transaction distribution +system.membus.trans_dist::CleanEvict 268224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4552 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 7 # Transaction distribution -system.membus.trans_dist::ReadExReq 701633 # Transaction distribution -system.membus.trans_dist::ReadExResp 701633 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 456672 # Transaction distribution -system.membus.trans_dist::InvalidateReq 650311 # Transaction distribution -system.membus.trans_dist::InvalidateResp 28814 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 859285 # Transaction distribution +system.membus.trans_dist::ReadExResp 859285 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 499952 # Transaction distribution +system.membus.trans_dist::InvalidateReq 672599 # Transaction distribution +system.membus.trans_dist::InvalidateResp 30234 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122360 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4556598 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4686250 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237342 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237342 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4923592 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5106407 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5235709 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237223 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237223 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5472932 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155490 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 164222764 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 164393170 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7227200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7227200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 171620370 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 32071 # Total snoops (count) -system.membus.snoopTraffic 208000 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1932895 # Request fanout histogram -system.membus.snoop_fanout::mean 0.016796 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.128505 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13820 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 186691628 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 186861678 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7220992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7220992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 194082670 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 33575 # Total snoops (count) +system.membus.snoopTraffic 213376 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2107909 # Request fanout histogram +system.membus.snoop_fanout::mean 0.016147 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.126040 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1900431 98.32% 98.32% # Request fanout histogram -system.membus.snoop_fanout::1 32464 1.68% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2073873 98.39% 98.39% # Request fanout histogram +system.membus.snoop_fanout::1 34036 1.61% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1932895 # Request fanout histogram -system.membus.reqLayer0.occupancy 99728500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2107909 # Request fanout histogram +system.membus.reqLayer0.occupancy 99276000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 18828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5568000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5601000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9720767792 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 10934593718 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6477610584 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 7287611424 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 75150025 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 76573457 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1658,28 +1643,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51688741391000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index 37952af83..6dc4ab397 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,172 +1,172 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.384940 # Number of seconds simulated -sim_ticks 47384940455000 # Number of ticks simulated -final_tick 47384940455000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.341923 # Number of seconds simulated +sim_ticks 47341923254000 # Number of ticks simulated +final_tick 47341923254000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 206357 # Simulator instruction rate (inst/s) -host_op_rate 242664 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10614318936 # Simulator tick rate (ticks/s) -host_mem_usage 793572 # Number of bytes of host memory used -host_seconds 4464.25 # Real time elapsed on the host -sim_insts 921230293 # Number of instructions simulated -sim_ops 1083311023 # Number of ops (including micro ops) simulated +host_inst_rate 198941 # Simulator instruction rate (inst/s) +host_op_rate 237233 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10723675807 # Simulator tick rate (ticks/s) +host_mem_usage 786956 # Number of bytes of host memory used +host_seconds 4414.71 # Real time elapsed on the host +sim_insts 878265186 # Number of instructions simulated +sim_ops 1047316960 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 222656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 215552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 4481312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 16941064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 21659840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 116096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 80000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2978912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 10395024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 12881984 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 421760 # Number of bytes read from this memory -system.physmem.bytes_read::total 70394200 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4481312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2978912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7460224 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 86479488 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 242176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 233728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4193568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 18888648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 25252160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 159808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 110720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3691360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 11578384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 16897024 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 434368 # Number of bytes read from this memory +system.physmem.bytes_read::total 81681944 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4193568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3691360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7884928 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 97721664 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 86500072 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 3479 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3368 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 85973 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 264717 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 338435 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1814 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1250 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 46589 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 162435 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 201281 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6590 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1115931 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1351242 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 97742248 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3784 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3652 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 67077 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 295148 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 394565 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2497 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1730 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 57721 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 180925 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 264016 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6787 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1277902 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1526901 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1353816 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 4699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 4549 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 94572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 357520 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 457104 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2450 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 62866 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 219374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 271858 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8901 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1485582 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 94572 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 62866 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 157439 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1825042 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1529475 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 5115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 4937 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 88580 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 398984 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 533400 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 77972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 244569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 356915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9175 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1725362 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 88580 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 77972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 166553 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2064168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1825476 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1825042 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 4699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 4549 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 94572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 357954 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 457104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2450 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 62866 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 219374 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 271858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8901 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3311058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1115931 # Number of read requests accepted -system.physmem.writeReqs 1353816 # Number of write requests accepted -system.physmem.readBursts 1115931 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1353816 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 71392384 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 27200 # Total number of bytes read from write queue -system.physmem.bytesWritten 86499392 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 70394200 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 86500072 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 425 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 2064602 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2064168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 5115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 4937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 88580 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 399418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 533400 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 77972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 244569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 356915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9175 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3789964 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1277902 # Number of read requests accepted +system.physmem.writeReqs 1529475 # Number of write requests accepted +system.physmem.readBursts 1277902 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1529475 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 81759232 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 26496 # Total number of bytes read from write queue +system.physmem.bytesWritten 97740224 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 81681944 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 97742248 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 414 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2256 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 66640 # Per bank write bursts -system.physmem.perBankRdBursts::1 69755 # Per bank write bursts -system.physmem.perBankRdBursts::2 65507 # Per bank write bursts -system.physmem.perBankRdBursts::3 67407 # Per bank write bursts -system.physmem.perBankRdBursts::4 65920 # Per bank write bursts -system.physmem.perBankRdBursts::5 70505 # Per bank write bursts -system.physmem.perBankRdBursts::6 65125 # Per bank write bursts -system.physmem.perBankRdBursts::7 71371 # Per bank write bursts -system.physmem.perBankRdBursts::8 68061 # Per bank write bursts -system.physmem.perBankRdBursts::9 95897 # Per bank write bursts -system.physmem.perBankRdBursts::10 65782 # Per bank write bursts -system.physmem.perBankRdBursts::11 68970 # Per bank write bursts -system.physmem.perBankRdBursts::12 60174 # Per bank write bursts -system.physmem.perBankRdBursts::13 71971 # Per bank write bursts -system.physmem.perBankRdBursts::14 71235 # Per bank write bursts -system.physmem.perBankRdBursts::15 71186 # Per bank write bursts -system.physmem.perBankWrBursts::0 81261 # Per bank write bursts -system.physmem.perBankWrBursts::1 86034 # Per bank write bursts -system.physmem.perBankWrBursts::2 81926 # Per bank write bursts -system.physmem.perBankWrBursts::3 83311 # Per bank write bursts -system.physmem.perBankWrBursts::4 82546 # Per bank write bursts -system.physmem.perBankWrBursts::5 86081 # Per bank write bursts -system.physmem.perBankWrBursts::6 81799 # Per bank write bursts -system.physmem.perBankWrBursts::7 86537 # Per bank write bursts -system.physmem.perBankWrBursts::8 86254 # Per bank write bursts -system.physmem.perBankWrBursts::9 89944 # Per bank write bursts -system.physmem.perBankWrBursts::10 82817 # Per bank write bursts -system.physmem.perBankWrBursts::11 84554 # Per bank write bursts -system.physmem.perBankWrBursts::12 78968 # Per bank write bursts -system.physmem.perBankWrBursts::13 86566 # Per bank write bursts -system.physmem.perBankWrBursts::14 86628 # Per bank write bursts -system.physmem.perBankWrBursts::15 86327 # Per bank write bursts +system.physmem.perBankRdBursts::0 74308 # Per bank write bursts +system.physmem.perBankRdBursts::1 87985 # Per bank write bursts +system.physmem.perBankRdBursts::2 79775 # Per bank write bursts +system.physmem.perBankRdBursts::3 80704 # Per bank write bursts +system.physmem.perBankRdBursts::4 79279 # Per bank write bursts +system.physmem.perBankRdBursts::5 87661 # Per bank write bursts +system.physmem.perBankRdBursts::6 78349 # Per bank write bursts +system.physmem.perBankRdBursts::7 78833 # Per bank write bursts +system.physmem.perBankRdBursts::8 69442 # Per bank write bursts +system.physmem.perBankRdBursts::9 78370 # Per bank write bursts +system.physmem.perBankRdBursts::10 69793 # Per bank write bursts +system.physmem.perBankRdBursts::11 81996 # Per bank write bursts +system.physmem.perBankRdBursts::12 80451 # Per bank write bursts +system.physmem.perBankRdBursts::13 82396 # Per bank write bursts +system.physmem.perBankRdBursts::14 80116 # Per bank write bursts +system.physmem.perBankRdBursts::15 88030 # Per bank write bursts +system.physmem.perBankWrBursts::0 92185 # Per bank write bursts +system.physmem.perBankWrBursts::1 101129 # Per bank write bursts +system.physmem.perBankWrBursts::2 94103 # Per bank write bursts +system.physmem.perBankWrBursts::3 97328 # Per bank write bursts +system.physmem.perBankWrBursts::4 94264 # Per bank write bursts +system.physmem.perBankWrBursts::5 99023 # Per bank write bursts +system.physmem.perBankWrBursts::6 94391 # Per bank write bursts +system.physmem.perBankWrBursts::7 95568 # Per bank write bursts +system.physmem.perBankWrBursts::8 90026 # Per bank write bursts +system.physmem.perBankWrBursts::9 95851 # Per bank write bursts +system.physmem.perBankWrBursts::10 88927 # Per bank write bursts +system.physmem.perBankWrBursts::11 96294 # Per bank write bursts +system.physmem.perBankWrBursts::12 94934 # Per bank write bursts +system.physmem.perBankWrBursts::13 97047 # Per bank write bursts +system.physmem.perBankWrBursts::14 95210 # Per bank write bursts +system.physmem.perBankWrBursts::15 100911 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 51513 # Number of times write queue was full causing retry -system.physmem.totGap 47384938876500 # Total gap between requests +system.physmem.numWrRetry 51774 # Number of times write queue was full causing retry +system.physmem.totGap 47341921675500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) -system.physmem.readPktSize::4 21333 # Read request sizes (log2) +system.physmem.readPktSize::4 2133 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1094573 # Read request sizes (log2) +system.physmem.readPktSize::6 1275744 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1351242 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 480312 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 254385 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 111988 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 68856 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 44885 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 37588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 34371 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 31850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28995 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 8446 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 4926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2904 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1783 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 820 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 687 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 582 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 476 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1526901 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 505708 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 298665 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 136731 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 85460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 55927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 46831 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 42547 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 39408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 35921 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 11095 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 6380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 3835 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2485 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1956 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1332 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 952 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 753 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see @@ -189,147 +189,147 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 22318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 26304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 36819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 42386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 51611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 56891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 62379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 68066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 69883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 74729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 78908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 77080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 78119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 84175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 91218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 81081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 75935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 8194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 3474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1885 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 2219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 2498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 2690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 2884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 3113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 3416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 5969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 24986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 120772 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1035166 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 152.526679 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 102.371009 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 198.170623 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 664281 64.17% 64.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 215041 20.77% 84.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 59106 5.71% 90.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 25397 2.45% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 20542 1.98% 95.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11502 1.11% 96.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7604 0.73% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6193 0.60% 97.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25500 2.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1035166 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 63814 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 17.480459 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 70.581857 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 63808 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 3 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 63814 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 63814 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.179569 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.530322 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 597.849869 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-4095 63812 100.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::15 24179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 28209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 39999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 46492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 52355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 57811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 64510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 71167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 77564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 80217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 85971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 89992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 89616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 91327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 98798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 107236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 96475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 90527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 10742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 6106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 4571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 2040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 2043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 2289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 2323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 2701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 3106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 3300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 3948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 4411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 6171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 25276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 121442 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1170396 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 153.366156 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.854296 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 197.868960 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 748847 63.98% 63.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 241823 20.66% 84.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 67607 5.78% 90.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 29756 2.54% 92.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 24374 2.08% 95.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 14066 1.20% 96.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9299 0.79% 97.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7338 0.63% 97.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 27286 2.33% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1170396 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 74463 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 17.155890 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 20.196232 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 74449 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 8 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 3 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 74463 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 74463 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.509394 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.370303 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 552.030208 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-4095 74461 100.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40960-45055 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::143360-147455 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 63814 # Writes before turning the bus around for reads -system.physmem.totQLat 67332860089 # Total ticks spent queuing -system.physmem.totMemAccLat 88248597589 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5577530000 # Total ticks spent in databus transfers -system.physmem.avgQLat 60360.82 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 74463 # Writes before turning the bus around for reads +system.physmem.totQLat 79629370316 # Total ticks spent queuing +system.physmem.totMemAccLat 103582270316 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6387440000 # Total ticks spent in databus transfers +system.physmem.avgQLat 62332.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 79110.82 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.51 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.83 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.49 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.83 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 81082.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.73 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.06 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.73 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.06 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing system.physmem.avgWrQLen 25.79 # Average write queue length when enqueuing -system.physmem.readRowHits 837889 # Number of row buffer hits during reads -system.physmem.writeRowHits 593994 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.11 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 43.95 # Row buffer hit rate for writes -system.physmem.avgGap 19186151.00 # Average gap between requests -system.physmem.pageHitRate 58.04 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3662384460 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1946584530 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3871522200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3494763900 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 31929318720.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 40834926540 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1598586240 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 62046559410 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 43455299520 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 11294770338285 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 11487626755995 # Total energy per rank (pJ) -system.physmem_0.averagePower 242.432018 # Core power per rank (mW) -system.physmem_0.totalIdleTime 47291190900816 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 2771331378 # Time in different power states -system.physmem_0.memoryStateTime::REF 13558872000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 47041958774500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 113164787559 # Time in different power states -system.physmem_0.memoryStateTime::ACT 77419210306 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 136067479257 # Time in different power states -system.physmem_1.actEnergy 3728772180 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1981870440 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4093190640 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3560342760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 33599910240.000008 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 42188393820 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1621939680 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 66725147910 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 45519792000 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 11290481164380 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 11493516343440 # Total energy per rank (pJ) -system.physmem_1.averagePower 242.556311 # Core power per rank (mW) -system.physmem_1.totalIdleTime 47288162727367 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 2732090205 # Time in different power states -system.physmem_1.memoryStateTime::REF 14267508000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 47023294872500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 118540781222 # Time in different power states -system.physmem_1.memoryStateTime::ACT 79778077178 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 146327125895 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.physmem.readRowHits 958718 # Number of row buffer hits during reads +system.physmem.writeRowHits 675564 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.05 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 44.23 # Row buffer hit rate for writes +system.physmem.avgGap 16863400.13 # Average gap between requests +system.physmem.pageHitRate 58.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4260723600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2264628300 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4618823160 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4008913020 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 30164687280.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 41855751510 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1419463680 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 63813765750 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 36794590560 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 11286440815140 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 11475654576000 # Total energy per rank (pJ) +system.physmem_0.averagePower 242.399417 # Core power per rank (mW) +system.physmem_0.totalIdleTime 47246408217619 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 2341242543 # Time in different power states +system.physmem_0.memoryStateTime::REF 12803196000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 47010648524500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 95818811721 # Time in different power states +system.physmem_0.memoryStateTime::ACT 80368685838 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 139942793398 # Time in different power states +system.physmem_1.actEnergy 4095910980 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2177024520 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4502441160 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3963024000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 30680370240.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 42163353720 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1422051360 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 64060335210 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 38109219360 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 11285470021935 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 11476656465255 # Total energy per rank (pJ) +system.physmem_1.averagePower 242.420579 # Core power per rank (mW) +system.physmem_1.totalIdleTime 47245728134436 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 2323672783 # Time in different power states +system.physmem_1.memoryStateTime::REF 13022950000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 47006002235750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 99242546502 # Time in different power states +system.physmem_1.memoryStateTime::ACT 80848444531 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 140483404434 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory @@ -356,30 +356,30 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 139151101 # Number of BP lookups -system.cpu0.branchPred.condPredicted 91634411 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6732234 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 97916993 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 61670085 # Number of BTB hits +system.cpu0.branchPred.lookups 135771616 # Number of BP lookups +system.cpu0.branchPred.condPredicted 86347947 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6838936 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 91129477 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 54316721 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 62.982005 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 19220371 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 194045 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4187621 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 2676103 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 1511518 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 384250 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 59.603899 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 20002366 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 187416 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 4394152 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2878401 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 1515751 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 382217 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -409,89 +409,88 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 608743 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 608743 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13705 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 96942 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 292908 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 315835 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2627.591939 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 15089.582893 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 312900 99.07% 99.07% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 2131 0.67% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 548 0.17% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 139 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 36 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 50 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 5 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::589824-655359 23 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 315835 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 324732 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22165.202382 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 18853.631715 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 18861.810606 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 320100 98.57% 98.57% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 3009 0.93% 99.50% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 694 0.21% 99.71% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 681 0.21% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 132 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 68 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 19 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 13 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 324732 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 522550016344 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.577122 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.559179 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 521035310844 99.71% 99.71% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 819753000 0.16% 99.87% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 323762500 0.06% 99.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 144297000 0.03% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 115791000 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 61783500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 19805000 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 28515500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 990500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 7500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 522550016344 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 96943 87.61% 87.61% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 13705 12.39% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 110648 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 608743 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 656993 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 656993 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 15295 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 109934 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 315620 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 341373 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2464.513889 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 14057.964276 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 338378 99.12% 99.12% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 2127 0.62% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 591 0.17% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 168 0.05% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 44 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 50 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::589824-655359 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 341373 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 358442 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 21996.103972 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18865.832829 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 18729.819330 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 353579 98.64% 98.64% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 3217 0.90% 99.54% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 596 0.17% 99.71% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 697 0.19% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 228 0.06% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 58 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 45 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 12 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 358442 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 470936013252 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.670912 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.545830 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 469324214752 99.66% 99.66% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 904884000 0.19% 99.85% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 330855500 0.07% 99.92% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 151555000 0.03% 99.95% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 116006500 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 57420000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 24613500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 25389500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 1013500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 61000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 470936013252 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 109934 87.79% 87.79% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 15295 12.21% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 125229 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 656993 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 608743 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 110648 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 656993 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 125229 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 110648 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 719391 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 125229 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 782222 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 101564011 # DTB read hits -system.cpu0.dtb.read_misses 439385 # DTB read misses -system.cpu0.dtb.write_hits 82403711 # DTB write hits -system.cpu0.dtb.write_misses 169358 # DTB write misses -system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 107772870 # DTB read hits +system.cpu0.dtb.read_misses 484010 # DTB read misses +system.cpu0.dtb.write_hits 87417439 # DTB write hits +system.cpu0.dtb.write_misses 172983 # DTB write misses +system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 44658 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 43119 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 431 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 7683 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 44511 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 282 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 7018 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 39881 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 102003396 # DTB read accesses -system.cpu0.dtb.write_accesses 82573069 # DTB write accesses +system.cpu0.dtb.perms_faults 39566 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 108256880 # DTB read accesses +system.cpu0.dtb.write_accesses 87590422 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 183967722 # DTB hits -system.cpu0.dtb.misses 608743 # DTB misses -system.cpu0.dtb.accesses 184576465 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 195190309 # DTB hits +system.cpu0.dtb.misses 656993 # DTB misses +system.cpu0.dtb.accesses 195847302 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -521,1187 +520,1194 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 85247 # Table walker walks requested -system.cpu0.itb.walker.walksLong 85247 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1031 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58619 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 10594 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 74653 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1640.215397 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 15358.310447 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-65535 74120 99.29% 99.29% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-131071 439 0.59% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-196607 37 0.05% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-262143 19 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-327679 10 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-393215 2 0.00% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::458752-524287 1 0.00% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::524288-589823 6 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::589824-655359 19 0.03% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 74653 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 70244 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 27495.914242 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23588.322709 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 27529.617952 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 67750 96.45% 96.45% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 1764 2.51% 98.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 417 0.59% 99.55% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 170 0.24% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 48 0.07% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 42 0.06% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 15 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 5 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 3 0.00% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 26 0.04% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 70244 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 419443065740 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.871284 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.335229 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 54034549916 12.88% 12.88% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 365365302324 87.11% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 40992500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 2004000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 217000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 419443065740 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 58619 98.27% 98.27% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 1031 1.73% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 59650 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 88518 # Table walker walks requested +system.cpu0.itb.walker.walksLong 88518 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 982 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 60760 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 10909 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 77609 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1509.006687 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 11301.495781 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-65535 77034 99.26% 99.26% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-131071 519 0.67% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-196607 33 0.04% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-262143 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-327679 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-393215 8 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 77609 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 72651 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 27149.240891 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23393.498423 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 24986.363412 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 70103 96.49% 96.49% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1723 2.37% 98.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 517 0.71% 99.58% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 199 0.27% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 51 0.07% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 35 0.05% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 6 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 72651 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 367854316648 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.912736 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.282646 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 32141827252 8.74% 8.74% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 335673383896 91.25% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 36841000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 2085000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 179500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 367854316648 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 60760 98.41% 98.41% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 982 1.59% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 61742 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 85247 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 85247 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 88518 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 88518 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 59650 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 59650 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 144897 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 219469803 # ITB inst hits -system.cpu0.itb.inst_misses 85247 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61742 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 61742 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 150260 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 209275517 # ITB inst hits +system.cpu0.itb.inst_misses 88518 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 44658 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 31398 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 31869 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 204530 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 214657 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 219555050 # ITB inst accesses -system.cpu0.itb.hits 219469803 # DTB hits -system.cpu0.itb.misses 85247 # DTB misses -system.cpu0.itb.accesses 219555050 # DTB accesses -system.cpu0.numPwrStateTransitions 27212 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 13606 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 3453780783.684036 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 93985708249.621262 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3589 26.38% 26.38% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 9986 73.39% 99.77% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 12 0.09% 99.86% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.88% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 13 0.10% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 6914083139000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 13606 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 392799112195 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 46992141342805 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 785608211 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 209364035 # ITB inst accesses +system.cpu0.itb.hits 209275517 # DTB hits +system.cpu0.itb.misses 88518 # DTB misses +system.cpu0.itb.accesses 209364035 # DTB accesses +system.cpu0.numPwrStateTransitions 11060 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 5530 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 8500198165.069259 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 152149510782.295166 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 4198 75.91% 75.91% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 1307 23.63% 99.55% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 6 0.11% 99.66% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.67% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.71% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.75% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.76% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.78% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 12 0.22% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 6914082541000 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 5530 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 335827401167 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 47006095852833 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 671656145 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 89154333 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 616347679 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 139151101 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 83566559 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 651741352 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 14592652 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2033431 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 298378 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 6056906 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 755254 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 834704 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 219265865 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1675112 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 28029 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 758170684 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.951385 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.212910 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 89746186 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 605326172 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 135771616 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 77197488 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 539879458 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 14767666 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2125862 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 314132 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 6298223 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 772099 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 851881 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 209041727 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1674502 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 29298 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 647371674 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.105525 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.248840 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 412487393 54.41% 54.41% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 134584185 17.75% 72.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 46569297 6.14% 78.30% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 164529809 21.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 308576951 47.67% 47.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 127594651 19.71% 67.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 45508982 7.03% 74.41% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 165691090 25.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 758170684 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.177125 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.784548 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 107249627 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 379334150 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 227390625 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 38947644 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5248638 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19981467 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2087891 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 636989334 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 23191131 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5248638 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 143394034 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 56142021 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 253850770 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 229681319 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 69853902 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 619319594 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 6178554 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 10862186 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 388792 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 930621 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 33162716 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 11693 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 591176589 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 957415604 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 731049781 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 649204 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 532948721 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 58227868 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 16256269 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 14199870 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 78279720 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 101593087 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 85666218 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 9630459 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 8075180 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 596126359 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 16460453 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 601474893 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2699291 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 54684336 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 35421563 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 283328 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 758170684 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.793324 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.057959 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 647371674 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.202145 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.901244 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 102332613 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 273941666 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 237936691 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 27831297 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5329407 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 50359670 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2095113 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 630187004 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 23557218 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5329407 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 133079950 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 61214716 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 153180346 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 234286149 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 60281106 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 612391061 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6345537 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 11623022 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 442390 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 950471 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 35105207 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 13004 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 561787552 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 866106072 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 720689595 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 706575 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 502207885 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 59579653 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 6816633 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 4684361 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 58564314 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 107690406 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 90791382 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 10221267 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 8541253 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 598417989 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 7027379 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 594218555 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2775784 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 55969109 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 36418491 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 281604 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 647371674 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.917894 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.123620 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 428799597 56.56% 56.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 139371286 18.38% 74.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 115828942 15.28% 90.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 66243104 8.74% 98.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 7922364 1.04% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 5391 0.00% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 341377364 52.73% 52.73% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 105270736 16.26% 68.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 121758490 18.81% 87.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 70435170 10.88% 98.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 8524242 1.32% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 5671 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 1 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 758170684 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 647371674 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 61955212 45.30% 45.30% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 62513 0.05% 45.34% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 16729 0.01% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMisc 21 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 36421436 26.63% 71.99% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 37996782 27.78% 99.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMemRead 31053 0.02% 99.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMemWrite 287360 0.21% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 65687551 45.22% 45.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 64582 0.04% 45.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 15638 0.01% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMisc 12 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 38738584 26.67% 71.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 40389693 27.81% 99.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemRead 34528 0.02% 99.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemWrite 315988 0.22% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 30 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 411361741 68.39% 68.39% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1567778 0.26% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 78948 0.01% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMisc 39915 0.01% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 104723474 17.41% 86.08% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 83352955 13.86% 99.94% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMemRead 49350 0.01% 99.95% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMemWrite 300687 0.05% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 70 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 392733469 66.09% 66.09% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1547002 0.26% 66.35% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 82083 0.01% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 53 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 15 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 25 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMisc 42153 0.01% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 2 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.37% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 111068257 18.69% 85.07% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 88363067 14.87% 99.94% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemRead 53874 0.01% 99.94% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemWrite 328485 0.06% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 601474893 # Type of FU issued -system.cpu0.iq.rate 0.765617 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 136771106 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.227393 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2099488112 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 667007258 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 583889559 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1102755 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 413748 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 385073 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 737537568 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 708401 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2768605 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 594218555 # Type of FU issued +system.cpu0.iq.rate 0.884706 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 145246576 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.244433 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1982627676 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 661129837 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 575942513 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1203467 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 445947 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 420205 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 738689926 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 775135 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2992085 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 12684669 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 17846 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 151274 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 5522197 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 13179956 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 18072 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 162311 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 5715015 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2796342 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4797484 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 3005258 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4976098 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5248638 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8055865 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1895421 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 612718172 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5329407 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8694006 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1907824 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 605581185 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 101593087 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 85666218 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13907446 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 58112 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1764578 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 151274 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 1949210 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 3085558 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5034768 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 593488019 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 101560351 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7385409 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 107690406 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 90791382 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 4430701 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 69738 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1753830 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 162311 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2018069 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 3124602 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5142671 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 586012257 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 107766715 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7557397 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 131360 # number of nop insts executed -system.cpu0.iew.exec_refs 183963466 # number of memory reference insts executed -system.cpu0.iew.exec_branches 111638269 # Number of branches executed -system.cpu0.iew.exec_stores 82403115 # Number of stores executed -system.cpu0.iew.exec_rate 0.755450 # Inst execution rate -system.cpu0.iew.wb_sent 585082868 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 584274632 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 284506732 # num instructions producing a value -system.cpu0.iew.wb_consumers 466304278 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.743723 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.610131 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 47796807 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 16177125 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4684546 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 749065087 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.744798 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.551758 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 135817 # number of nop insts executed +system.cpu0.iew.exec_refs 195183772 # number of memory reference insts executed +system.cpu0.iew.exec_branches 107644173 # Number of branches executed +system.cpu0.iew.exec_stores 87417057 # Number of stores executed +system.cpu0.iew.exec_rate 0.872488 # Inst execution rate +system.cpu0.iew.wb_sent 577164047 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 576362718 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 283557258 # num instructions producing a value +system.cpu0.iew.wb_consumers 461921851 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.858122 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.613864 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 48922079 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 6745775 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4784510 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 638061728 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.861165 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.699392 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 504468440 67.35% 67.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 127495809 17.02% 84.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 53846196 7.19% 91.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 17894232 2.39% 93.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 12874355 1.72% 95.66% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 8922431 1.19% 96.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 5996417 0.80% 97.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3594154 0.48% 98.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 13973053 1.87% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 421096864 66.00% 66.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 93116977 14.59% 80.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 56739989 8.89% 89.48% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 18882229 2.96% 92.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 13609968 2.13% 94.57% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 9457933 1.48% 96.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6466471 1.01% 97.07% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3826133 0.60% 97.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 14865164 2.33% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 749065087 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 475226157 # Number of instructions committed -system.cpu0.commit.committedOps 557902476 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 638061728 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 461890383 # Number of instructions committed +system.cpu0.commit.committedOps 549476248 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 169052439 # Number of memory references committed -system.cpu0.commit.loads 88908418 # Number of loads committed -system.cpu0.commit.membars 3969625 # Number of memory barriers committed -system.cpu0.commit.branches 106090436 # Number of branches committed -system.cpu0.commit.fp_insts 377224 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 511981133 # Number of committed integer instructions. -system.cpu0.commit.function_calls 14308761 # Number of function calls committed. +system.cpu0.commit.refs 179586814 # Number of memory references committed +system.cpu0.commit.loads 94510447 # Number of loads committed +system.cpu0.commit.membars 4189650 # Number of memory barriers committed +system.cpu0.commit.branches 102007560 # Number of branches committed +system.cpu0.commit.fp_insts 412941 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 511246578 # Number of committed integer instructions. +system.cpu0.commit.function_calls 15004572 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 387443640 69.45% 69.45% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1310567 0.23% 69.68% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 61901 0.01% 69.69% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.69% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.69% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.69% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.69% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 69.69% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.69% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMisc 33929 0.01% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.70% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 88862033 15.93% 85.63% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 79847111 14.31% 99.94% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMemRead 46385 0.01% 99.95% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMemWrite 296910 0.05% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 368489017 67.06% 67.06% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1298564 0.24% 67.30% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 64848 0.01% 67.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 8 0.00% 67.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 13 0.00% 67.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 21 0.00% 67.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 67.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMisc 36963 0.01% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.32% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 94459041 17.19% 84.51% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 84751837 15.42% 99.93% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMemRead 51406 0.01% 99.94% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMemWrite 324530 0.06% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 557902476 # Class of committed instruction -system.cpu0.commit.bw_lim_events 13973053 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1336174255 # The number of ROB reads -system.cpu0.rob.rob_writes 1220466867 # The number of ROB writes -system.cpu0.timesIdled 1005352 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27437527 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 93984272695 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 475226157 # Number of Instructions Simulated -system.cpu0.committedOps 557902476 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.653125 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.653125 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.604915 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.604915 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 700618930 # number of integer regfile reads -system.cpu0.int_regfile_writes 416450651 # number of integer regfile writes -system.cpu0.fp_regfile_reads 634669 # number of floating regfile reads -system.cpu0.fp_regfile_writes 293776 # number of floating regfile writes -system.cpu0.cc_regfile_reads 128889270 # number of cc regfile reads -system.cpu0.cc_regfile_writes 129563151 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1347671553 # number of misc regfile reads -system.cpu0.misc_regfile_writes 16172806 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 6286438 # number of replacements -system.cpu0.dcache.tags.tagsinuse 484.582319 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 156315528 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6286950 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 24.863492 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 2049282000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.582319 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.946450 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.946450 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 549476248 # Class of committed instruction +system.cpu0.commit.bw_lim_events 14865164 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1217272285 # The number of ROB reads +system.cpu0.rob.rob_writes 1206069871 # The number of ROB writes +system.cpu0.timesIdled 983506 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 24284471 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 94012190405 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 461890383 # Number of Instructions Simulated +system.cpu0.committedOps 549476248 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.454146 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.454146 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.687689 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.687689 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 689648120 # number of integer regfile reads +system.cpu0.int_regfile_writes 419367317 # number of integer regfile writes +system.cpu0.fp_regfile_reads 692130 # number of floating regfile reads +system.cpu0.fp_regfile_writes 320584 # number of floating regfile writes +system.cpu0.cc_regfile_reads 105285978 # number of cc regfile reads +system.cpu0.cc_regfile_writes 105978286 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1168751660 # number of misc regfile reads +system.cpu0.misc_regfile_writes 6863582 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 6620968 # number of replacements +system.cpu0.dcache.tags.tagsinuse 481.361219 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 165967454 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6621480 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 25.065009 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 204144000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.361219 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.940159 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.940159 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 433 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 351060755 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 351060755 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 82089512 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 82089512 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 69232216 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 69232216 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 209823 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 209823 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 173405 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 173405 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1868090 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1868090 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1930069 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1930069 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 151495133 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 151495133 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 151704956 # number of overall hits -system.cpu0.dcache.overall_hits::total 151704956 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 7010414 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7010414 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 7797174 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 7797174 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 751824 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 751824 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 805427 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 805427 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 284725 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 284725 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 186829 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 186829 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 15613015 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 15613015 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 16364839 # number of overall misses -system.cpu0.dcache.overall_misses::total 16364839 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 112159926000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 112159926000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 158052575270 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 158052575270 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 29573159898 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 29573159898 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4301491500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 4301491500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4484661500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4484661500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2134500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2134500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 299785661168 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 299785661168 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 299785661168 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 299785661168 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 89099926 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 89099926 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 77029390 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 77029390 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 961647 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 961647 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 978832 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 978832 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2152815 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2152815 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2116898 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2116898 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 167108148 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 167108148 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 168069795 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 168069795 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.078680 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.078680 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.101223 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.101223 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781809 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781809 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.822845 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.822845 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.132257 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.132257 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.088256 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.088256 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.093431 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.093431 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097369 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097369 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15999.044564 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15999.044564 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20270.494832 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20270.494832 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 36717.368424 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 36717.368424 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15107.530073 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15107.530073 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24004.097330 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24004.097330 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 372530825 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 372530825 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 87044023 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 87044023 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 73673205 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 73673205 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 219185 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 219185 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 153997 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 153997 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2008223 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 2008223 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2072988 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 2072988 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 160871225 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 160871225 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 161090410 # number of overall hits +system.cpu0.dcache.overall_hits::total 161090410 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 7470146 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 7470146 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 8166848 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 8166848 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 789396 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 789396 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 800299 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 800299 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 307874 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 307874 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 202740 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 202740 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 16437293 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 16437293 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 17226689 # number of overall misses +system.cpu0.dcache.overall_misses::total 17226689 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 120830384000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 120830384000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 166078687815 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 166078687815 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 29848601951 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 29848601951 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4689476000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 4689476000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4883927500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4883927500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2141000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2141000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 316757673766 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 316757673766 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 316757673766 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 316757673766 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 94514169 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 94514169 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 81840053 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 81840053 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1008581 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1008581 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 954296 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 954296 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2316097 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2316097 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2275728 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2275728 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 177308518 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 177308518 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 178317099 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 178317099 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.079037 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.079037 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.099790 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.099790 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.782680 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.782680 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.838628 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.838628 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.132928 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.132928 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.089088 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.089088 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092704 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.092704 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096607 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.096607 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16175.103405 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 16175.103405 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20335.714319 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20335.714319 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 37296.812755 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 37296.812755 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15231.802621 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15231.802621 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24089.609845 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24089.609845 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19201.010258 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19201.010258 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18318.888513 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18318.888513 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 8999058 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 24447381 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 751224 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 774000 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 11.979194 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 31.585764 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 6286527 # number of writebacks -system.cpu0.dcache.writebacks::total 6286527 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3589298 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3589298 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6265824 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 6265824 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4129 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 4129 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 147493 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 147493 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 9859251 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 9859251 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 9859251 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 9859251 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3421116 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3421116 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1531350 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1531350 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 745052 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 745052 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 801298 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 801298 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 137232 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 137232 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 186825 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 186825 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5753764 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5753764 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 6498816 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 6498816 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29615 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29615 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 29691 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 29691 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 59306 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 59306 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 51678055000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 51678055000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 34197879948 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 34197879948 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17704904500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17704904500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 28602356899 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 28602356899 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1885182000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1885182000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4297888500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4297888500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2082500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2082500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 114478291847 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 114478291847 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 132183196347 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 132183196347 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5594868000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5594868000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5594868000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5594868000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.038396 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038396 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019880 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019880 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.774767 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.774767 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.818627 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.818627 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063745 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063745 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.088254 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.088254 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.034431 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.034431 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.038667 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.038667 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15105.613198 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15105.613198 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22331.850947 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22331.850947 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23763.313836 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23763.313836 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 35695.030936 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 35695.030936 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13737.189577 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13737.189577 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23004.889603 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23004.889603 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19270.671501 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19270.671501 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18387.612023 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18387.612023 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9058407 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 25757393 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 741437 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 811492 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.217366 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 31.740785 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 6621095 # number of writebacks +system.cpu0.dcache.writebacks::total 6621095 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3832878 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3832878 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6557291 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 6557291 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4455 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 4455 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 156975 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 156975 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 10394624 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 10394624 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 10394624 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 10394624 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3637268 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3637268 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1609557 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1609557 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 782554 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 782554 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 795844 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 795844 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 150899 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 150899 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 202732 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 202732 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 6042669 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 6042669 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 6825223 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 6825223 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15843 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 15843 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 17283 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 17283 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 33126 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 33126 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 55872486000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 55872486000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 35889720367 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 35889720367 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18736140000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18736140000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 28877247951 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 28877247951 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 2069296000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2069296000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4681247500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4681247500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2089000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2089000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 120639454318 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 120639454318 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 139375594318 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 139375594318 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2897214000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2897214000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2897214000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2897214000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.038484 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038484 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019667 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019667 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.775896 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.775896 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.833959 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.833959 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065152 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065152 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.089084 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.089084 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.034080 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.034080 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.038276 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.038276 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15361.113341 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15361.113341 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22297.887162 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22297.887162 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23942.296634 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23942.296634 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 36285.060830 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36285.060830 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13713.119371 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13713.119371 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23090.816941 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23090.816941 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19896.243893 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19896.243893 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20339.581294 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20339.581294 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188920.074287 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 188920.074287 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 94338.987624 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 94338.987624 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 5974428 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.960293 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 212911456 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5974940 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 35.634074 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 13477910000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.960293 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999922 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999922 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19964.597485 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19964.597485 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20420.665276 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20420.665276 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182870.289718 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182870.289718 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87460.423836 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87460.423836 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 6024041 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.980173 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 202652654 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 6024553 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 33.637791 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 11640760000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.980173 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999961 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999961 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 293 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 444450377 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 444450377 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 212911456 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 212911456 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 212911456 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 212911456 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 212911456 # number of overall hits -system.cpu0.icache.overall_hits::total 212911456 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6326229 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6326229 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6326229 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6326229 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6326229 # number of overall misses -system.cpu0.icache.overall_misses::total 6326229 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 70930890398 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 70930890398 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 70930890398 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 70930890398 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 70930890398 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 70930890398 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 219237685 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 219237685 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 219237685 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 219237685 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 219237685 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 219237685 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028856 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.028856 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028856 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.028856 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028856 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.028856 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11212.191402 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 11212.191402 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11212.191402 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 11212.191402 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11212.191402 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 11212.191402 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 10513720 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 1665 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 740505 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.198041 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 128.076923 # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 5974428 # number of writebacks -system.cpu0.icache.writebacks::total 5974428 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 351221 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 351221 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 351221 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 351221 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 351221 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 351221 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5975008 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 5975008 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 5975008 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 5975008 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 5975008 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 5975008 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 63931230447 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 63931230447 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 63931230447 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 63931230447 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 63931230447 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 63931230447 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2027158498 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2027158498 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2027158498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 2027158498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027254 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027254 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027254 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.027254 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027254 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.027254 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10699.773196 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10699.773196 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10699.773196 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10699.773196 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10699.773196 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10699.773196 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95203.047856 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95203.047856 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95203.047856 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95203.047856 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 8714333 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8724211 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 8793 # number of redundant prefetches already in prefetch queue +system.cpu0.icache.tags.tag_accesses 424090067 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 424090067 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 202652654 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 202652654 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 202652654 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 202652654 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 202652654 # number of overall hits +system.cpu0.icache.overall_hits::total 202652654 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6379961 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 6379961 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6379961 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 6379961 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6379961 # number of overall misses +system.cpu0.icache.overall_misses::total 6379961 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 71606822648 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 71606822648 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 71606822648 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 71606822648 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 71606822648 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 71606822648 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 209032615 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 209032615 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 209032615 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 209032615 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 209032615 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 209032615 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.030521 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.030521 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.030521 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.030521 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.030521 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.030521 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11223.708522 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 11223.708522 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11223.708522 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 11223.708522 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11223.708522 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 11223.708522 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 10553176 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 2682 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 731110 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.434457 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 243.818182 # average number of cycles each access was blocked +system.cpu0.icache.writebacks::writebacks 6024041 # number of writebacks +system.cpu0.icache.writebacks::total 6024041 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 355124 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 355124 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 355124 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 355124 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 355124 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 355124 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6024837 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 6024837 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6024837 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 6024837 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6024837 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 6024837 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 2093 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 2093 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 2093 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 2093 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 64522792922 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 64522792922 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 64522792922 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 64522792922 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 64522792922 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 64522792922 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 201228498 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 201228498 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 201228498 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 201228498 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028822 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028822 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028822 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.028822 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028822 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.028822 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10709.466982 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10709.466982 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10709.466982 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10709.466982 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10709.466982 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10709.466982 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 96143.572862 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 96143.572862 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 96143.572862 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 96143.572862 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 9077732 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 9085476 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 6999 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1114037 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2711723 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15840.616895 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 10811538 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2727125 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 3.964445 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2357982000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15519.308256 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 33.621063 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 19.237059 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000001 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 268.450517 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.947223 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002052 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001174 # Average percentage of cache occupancy +system.cpu0.l2cache.prefetcher.pfSpanPage 1224644 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 2885626 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15865.684381 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 11160732 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2901096 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 3.847074 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 512573000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 15504.354139 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 30.001688 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 17.597153 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000007 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 313.731394 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.946311 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001831 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001074 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.016385 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.966835 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 381 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14929 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 75 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 118 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 93 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 95 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 69 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.019149 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.968365 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 318 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 111 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15041 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 120 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 81 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 114 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 37 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 43 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 499 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1082 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5719 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5657 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1972 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.023254 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005615 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.911194 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 427199165 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 427199165 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 602660 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 185799 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 788459 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 4096903 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 4096903 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 8161916 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 8161916 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 32 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 32 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 986017 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 986017 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5386829 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 5386829 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3255809 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 3255809 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 183461 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 183461 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 602660 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 185799 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 5386829 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 4241826 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 10417114 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 602660 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 185799 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 5386829 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 4241826 # number of overall hits -system.cpu0.l2cache.overall_hits::total 10417114 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 25200 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 12620 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 37820 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 257381 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 257381 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 186815 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 186815 # number of SCUpgradeReq misses +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2178 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7928 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2613 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2218 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.019409 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006775 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.918030 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 441303495 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 441303495 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 661323 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 192664 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 853987 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 4337132 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 4337132 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 8306124 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 8306124 # number of WritebackClean hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 35 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 35 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 3 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 1063752 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 1063752 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5420251 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 5420251 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3451457 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 3451457 # number of ReadSharedReq hits +system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 175529 # number of InvalidateReq hits +system.cpu0.l2cache.InvalidateReq_hits::total 175529 # number of InvalidateReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 661323 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 192664 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 5420251 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 4515209 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 10789447 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 661323 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 192664 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 5420251 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 4515209 # number of overall hits +system.cpu0.l2cache.overall_hits::total 10789447 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 24436 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 12223 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 36659 # number of ReadReq misses +system.cpu0.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses +system.cpu0.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 266353 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 266353 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 202724 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 202724 # number of SCUpgradeReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 295278 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 295278 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 588130 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 588130 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1045192 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 1045192 # number of ReadSharedReq misses -system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 617837 # number of InvalidateReq misses -system.cpu0.l2cache.InvalidateReq_misses::total 617837 # number of InvalidateReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 25200 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 12620 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 588130 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1340470 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1966420 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 25200 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 12620 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 588130 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1340470 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1966420 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 896455000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 597646500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 1494101500 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 982091000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 982091000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 295025000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 295025000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2003000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2003000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 18413910498 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 18413910498 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 22335302000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 22335302000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 43094995483 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 43094995483 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 882000 # number of InvalidateReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::total 882000 # number of InvalidateReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 896455000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 597646500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 22335302000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 61508905981 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 85338309481 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 896455000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 597646500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 22335302000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 61508905981 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 85338309481 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 627860 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 198419 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 826279 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4096903 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 4096903 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 8161916 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 8161916 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 257413 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 257413 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 186820 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 186820 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 288175 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 288175 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 604135 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 604135 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1115532 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 1115532 # number of ReadSharedReq misses +system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 620315 # number of InvalidateReq misses +system.cpu0.l2cache.InvalidateReq_misses::total 620315 # number of InvalidateReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 24436 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 12223 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 604135 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1403707 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 2044501 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 24436 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 12223 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 604135 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1403707 # number of overall misses +system.cpu0.l2cache.overall_misses::total 2044501 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 912274000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 596923500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 1509197500 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 951661000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 951661000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 365355500 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 365355500 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2010499 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2010499 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 19225466000 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 19225466000 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 22664217000 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 22664217000 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 46789999492 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 46789999492 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 209000 # number of InvalidateReq miss cycles +system.cpu0.l2cache.InvalidateReq_miss_latency::total 209000 # number of InvalidateReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 912274000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 596923500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 22664217000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 66015465492 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 90188879992 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 912274000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 596923500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 22664217000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 66015465492 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 90188879992 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 685759 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 204887 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 890646 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4337132 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 4337132 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 8306125 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 8306125 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 266388 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 266388 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 202727 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 202727 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1281295 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1281295 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5974959 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 5974959 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4301001 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 4301001 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 801298 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::total 801298 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 627860 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 198419 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 5974959 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5582296 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 12383534 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 627860 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 198419 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 5974959 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5582296 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 12383534 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.040136 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.063603 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.045771 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999876 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999876 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999973 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999973 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1351927 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1351927 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6024386 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 6024386 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4566989 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 4566989 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 795844 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::total 795844 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 685759 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 204887 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 6024386 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 5918916 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 12833948 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 685759 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 204887 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 6024386 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 5918916 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 12833948 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.035634 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.059657 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.041160 # miss rate for ReadReq accesses +system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses +system.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999869 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999869 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999985 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999985 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.230453 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.230453 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.098432 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.098432 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.243011 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.243011 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.771045 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.771045 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.040136 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.063603 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.098432 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.240129 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.158793 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.040136 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.063603 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.098432 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.240129 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.158793 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35573.611111 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 47357.091918 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 39505.592279 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3815.709007 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3815.709007 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1579.236143 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1579.236143 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 400600 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 400600 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 62361.268019 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 62361.268019 # average ReadExReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37976.811249 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37976.811249 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41231.654551 # average ReadSharedReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41231.654551 # average ReadSharedReq miss latency -system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 1.427561 # average InvalidateReq miss latency -system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 1.427561 # average InvalidateReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35573.611111 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 47357.091918 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37976.811249 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45886.074273 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 43397.803867 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35573.611111 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 47357.091918 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37976.811249 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45886.074273 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 43397.803867 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 1100 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.213159 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.213159 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.100282 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.100282 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.244260 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.244260 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.779443 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.779443 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.035634 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.059657 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.100282 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.237156 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.159304 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.035634 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.059657 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.100282 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.237156 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.159304 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 37333.196923 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 48836.087704 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 41168.539786 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3572.931411 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3572.931411 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1802.231112 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1802.231112 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 402099.800000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 402099.800000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 66714.551922 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 66714.551922 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37515.153070 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37515.153070 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41944.112309 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41944.112309 # average ReadSharedReq miss latency +system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 0.336926 # average InvalidateReq miss latency +system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 0.336926 # average InvalidateReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 37333.196923 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 48836.087704 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37515.153070 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 47029.376851 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 44112.905786 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 37333.196923 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 48836.087704 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37515.153070 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 47029.376851 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 44112.905786 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 1145 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 24 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 45.833333 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 57.250000 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.unused_prefetches 49027 # number of HardPF blocks evicted w/o reference -system.cpu0.l2cache.writebacks::writebacks 1747264 # number of writebacks -system.cpu0.l2cache.writebacks::total 1747264 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 192 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 348 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 540 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 21118 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 21118 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 4 # number of ReadCleanReq MSHR hits -system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 5796 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 5796 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 13 # number of InvalidateReq MSHR hits -system.cpu0.l2cache.InvalidateReq_mshr_hits::total 13 # number of InvalidateReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 192 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 348 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 26914 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 27458 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 192 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 348 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 26914 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 27458 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 25008 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 12272 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 37280 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 914694 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 914694 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 257381 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 257381 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 186815 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 186815 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.unused_prefetches 50024 # number of HardPF blocks evicted w/o reference +system.cpu0.l2cache.writebacks::writebacks 1896260 # number of writebacks +system.cpu0.l2cache.writebacks::total 1896260 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 178 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 367 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 545 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 23776 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 23776 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 3 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 5616 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 5616 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 3 # number of InvalidateReq MSHR hits +system.cpu0.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 178 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 367 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 29392 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 29940 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 178 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 367 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 29392 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 29940 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 24258 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 11856 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 36114 # number of ReadReq MSHR misses +system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses +system.cpu0.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 950932 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 950932 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 266353 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 266353 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 202724 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 202724 # number of SCUpgradeReq MSHR misses system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 274160 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 274160 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 588126 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 588126 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1039396 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1039396 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 617824 # number of InvalidateReq MSHR misses -system.cpu0.l2cache.InvalidateReq_mshr_misses::total 617824 # number of InvalidateReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 25008 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 12272 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 588126 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1313556 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 1938962 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 25008 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 12272 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 588126 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1313556 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 914694 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 2853656 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 29615 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 50908 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 29691 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 29691 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 59306 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 80599 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 742635500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 518427500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1261063000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 57180143123 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 57180143123 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4798228494 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4798228494 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2893409994 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2893409994 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1691000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1691000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 13686705498 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 13686705498 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 18806492000 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 18806492000 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 36387650483 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 36387650483 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 21673087497 # number of InvalidateReq MSHR miss cycles -system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 21673087497 # number of InvalidateReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 742635500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 518427500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 18806492000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 50074355981 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 70141910981 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 742635500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 518427500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 18806492000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 50074355981 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 57180143123 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 127322054104 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1867460000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5357476000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7224936000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1867460000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5357476000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7224936000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.039831 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.061849 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.045118 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 264399 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 264399 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 604132 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 604132 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1109916 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1109916 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 620312 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::total 620312 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 24258 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 11856 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 604132 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1374315 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 2014561 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 24258 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 11856 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 604132 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1374315 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 950932 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 2965493 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 2093 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 15843 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 17936 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 17283 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 17283 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 2093 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 33126 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 35219 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 763418000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 519315500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1282733500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 66266397744 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 66266397744 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4978129498 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4978129498 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3157260491 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3157260491 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1698499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1698499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 14042647500 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 14042647500 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 19039385000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 19039385000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 39727406492 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 39727406492 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 22010835496 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 22010835496 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 763418000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 519315500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 19039385000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 53770053992 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 74092172492 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 763418000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 519315500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 19039385000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 53770053992 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 66266397744 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 140358570236 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 185530000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2769951000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 2955481000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 185530000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 2769951000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 2955481000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.035374 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.057866 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.040548 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses +system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999876 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999876 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999973 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999973 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999869 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999869 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999985 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999985 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.213971 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.213971 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.098432 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098432 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.241664 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.241664 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.771029 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.771029 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.039831 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.061849 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.098432 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.235307 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.156576 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.039831 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.061849 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.098432 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.235307 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.195572 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.195572 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.100281 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.100281 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.243030 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.243030 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.779439 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.779439 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.035374 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.057866 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.100281 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.232190 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.156971 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.035374 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.057866 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.100281 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.232190 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230440 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29695.917306 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 42244.744133 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33826.797210 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 62512.865639 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 62512.865639 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18642.512439 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18642.512439 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15488.103172 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15488.103172 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 338200 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 338200 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 49922.328195 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 49922.328195 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31976.977722 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31976.977722 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35008.457299 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35008.457299 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 35079.711207 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 35079.711207 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29695.917306 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 42244.744133 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31976.977722 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38121.219028 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36174.979696 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29695.917306 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 42244.744133 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31976.977722 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38121.219028 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 62512.865639 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44617.169730 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87703.000986 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180904.136417 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 141921.426888 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87703.000986 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 90336.154858 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89640.516632 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 25418604 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13061865 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3409 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 690419 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 690321 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 98 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 966476 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 11336947 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 29691 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 29691 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5857040 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 8164049 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1344034 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1151380 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 469212 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 335795 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 509398 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 66 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 113 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1315239 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1289150 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5975008 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5298799 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 872203 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 802449 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 17966980 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20229549 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 416579 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1325266 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 39938374 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 765101392 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 766341777 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1587352 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5022880 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1538053401 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 5977120 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 119917960 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 19518051 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.053731 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.225509 # Request fanout histogram +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231066 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31470.772529 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 43801.914642 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 35519.009248 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69685.737512 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 69685.737512 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18689.969694 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18689.969694 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15574.182095 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15574.182095 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 339699.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 339699.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 53111.575687 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 53111.575687 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31515.273152 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31515.273152 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35793.164971 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35793.164971 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 35483.491366 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 35483.491366 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31470.772529 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 43801.914642 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31515.273152 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 39124.985169 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36778.321675 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31470.772529 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 43801.914642 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31515.273152 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 39124.985169 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69685.737512 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 47330.602445 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88643.096034 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174837.530771 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164779.270740 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88643.096034 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 83618.637928 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 83917.232176 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 26242800 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13504787 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 4079 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 709472 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 709425 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 47 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 1004788 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 11688716 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 17283 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 17283 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 6246434 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 8308001 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1424808 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1208828 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 455562 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 363537 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 533487 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1384860 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1359346 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6024837 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5574197 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 855548 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 797069 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18077450 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 21220350 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 431264 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1446232 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 41175296 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 771132816 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 809027527 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1639096 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5486072 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1587285511 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 6254740 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 129367088 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 20223636 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.054517 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.227045 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 18469421 94.63% 94.63% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 1048532 5.37% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 98 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 19121152 94.55% 94.55% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 1102437 5.45% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 47 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 19518051 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 25305808947 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 20223636 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 26091767715 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 186983903 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 182386585 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 8989974042 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 9045827975 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 9049403091 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 9544267214 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 218640527 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 226891962 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 698295209 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 761324284 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 130931248 # Number of BP lookups -system.cpu1.branchPred.condPredicted 87112041 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6567659 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 91792654 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 56129151 # Number of BTB hits +system.cpu1.branchPred.lookups 124325317 # Number of BP lookups +system.cpu1.branchPred.condPredicted 79272164 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6778632 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 83479161 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 47841396 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 61.147759 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17311793 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 174850 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 4346649 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 2655837 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1690812 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 417178 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 57.309388 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17874464 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 195085 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 4411145 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 2666966 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1744179 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 432386 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1731,88 +1737,88 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 551219 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 551219 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11436 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 86181 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 255688 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 295531 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2259.422869 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 13315.556253 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 293454 99.30% 99.30% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1395 0.47% 99.77% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 424 0.14% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 158 0.05% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 50 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 38 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-458751 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::458752-524287 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 295531 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 283173 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 21265.600887 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 18470.492322 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 14814.339876 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 281324 99.35% 99.35% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1404 0.50% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 195 0.07% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 146 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 42 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 27 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 13 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 9 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 283173 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 475307081088 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.614132 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.549956 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 474122952588 99.75% 99.75% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 603814500 0.13% 99.88% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 247441500 0.05% 99.93% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 130616500 0.03% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 93327500 0.02% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 62495500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 19627500 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 26354000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 445000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 6500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 475307081088 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 86181 88.28% 88.28% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 11436 11.72% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 97617 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 551219 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 580775 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 580775 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 12302 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 93041 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 266909 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 313866 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2454.023373 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 13953.006998 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 311371 99.21% 99.21% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1689 0.54% 99.74% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 507 0.16% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 189 0.06% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 54 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 44 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 313866 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 295327 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 21717.315044 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 18678.510143 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 17673.432878 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 292731 99.12% 99.12% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1780 0.60% 99.72% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 365 0.12% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 243 0.08% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 59 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 66 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 14 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 35 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 14 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 295327 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 389340230128 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.666551 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.555298 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 388038620628 99.67% 99.67% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 674944000 0.17% 99.84% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 273419500 0.07% 99.91% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 140502000 0.04% 99.95% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 100194000 0.03% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 59021000 0.02% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 22755500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 30241000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 482500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 50000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 389340230128 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 93042 88.32% 88.32% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 12302 11.68% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 105344 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 580775 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 551219 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97617 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 580775 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 105344 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97617 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 648836 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 105344 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 686119 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 95947338 # DTB read hits -system.cpu1.dtb.read_misses 376138 # DTB read misses -system.cpu1.dtb.write_hits 79464123 # DTB write hits -system.cpu1.dtb.write_misses 175081 # DTB write misses -system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 97816184 # DTB read hits +system.cpu1.dtb.read_misses 397931 # DTB read misses +system.cpu1.dtb.write_hits 81264416 # DTB write hits +system.cpu1.dtb.write_misses 182844 # DTB write misses +system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 44658 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 35142 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 372 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 6075 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 36337 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 714 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 7662 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 39563 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 96323476 # DTB read accesses -system.cpu1.dtb.write_accesses 79639204 # DTB write accesses +system.cpu1.dtb.perms_faults 41901 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 98214115 # DTB read accesses +system.cpu1.dtb.write_accesses 81447260 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 175411461 # DTB hits -system.cpu1.dtb.misses 551219 # DTB misses -system.cpu1.dtb.accesses 175962680 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 179080600 # DTB hits +system.cpu1.dtb.misses 580775 # DTB misses +system.cpu1.dtb.accesses 179661375 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1842,1180 +1848,1175 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 82567 # Table walker walks requested -system.cpu1.itb.walker.walksLong 82567 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 985 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 60088 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 9957 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 72610 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 937.467291 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 7808.036609 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-65535 72461 99.79% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-131071 121 0.17% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-196607 15 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-262143 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-327679 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 72610 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 71030 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 24890.468816 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 22675.930059 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 19295.215598 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 70173 98.79% 98.79% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 554 0.78% 99.57% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 204 0.29% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 35 0.05% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 20 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 8 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 25 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 71030 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 397994478260 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.871343 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.334985 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 51225264788 12.87% 12.87% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 346750110472 87.12% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 17741500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 1276000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 85500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 397994478260 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 60088 98.39% 98.39% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 985 1.61% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 61073 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 87135 # Table walker walks requested +system.cpu1.itb.walker.walksLong 87135 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1092 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 62581 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 10397 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 76738 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1034.422320 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 9201.232348 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-65535 76494 99.68% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-131071 186 0.24% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-196607 34 0.04% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-262143 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-327679 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-393215 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 76738 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 74070 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 25472.262724 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 22851.948587 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 20227.385308 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 72813 98.30% 98.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 775 1.05% 99.35% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 316 0.43% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 87 0.12% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 33 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 20 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 17 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 74070 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 329207699984 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.888226 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.315322 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 36820179964 11.18% 11.18% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 292365319520 88.81% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 21267000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 903500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 30000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 329207699984 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 62581 98.28% 98.28% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 1092 1.72% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 63673 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 82567 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 82567 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 87135 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 87135 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 61073 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 61073 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 143640 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 204871540 # ITB inst hits -system.cpu1.itb.inst_misses 82567 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63673 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63673 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 150808 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 190777093 # ITB inst hits +system.cpu1.itb.inst_misses 87135 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 44658 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 24862 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 25727 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 205327 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 222647 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 204954107 # ITB inst accesses -system.cpu1.itb.hits 204871540 # DTB hits -system.cpu1.itb.misses 82567 # DTB misses -system.cpu1.itb.accesses 204954107 # DTB accesses -system.cpu1.numPwrStateTransitions 10338 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 5169 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 9100042413.076223 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 142913287882.442078 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3563 68.93% 68.93% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 1580 30.57% 99.50% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.04% 99.54% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 5 0.10% 99.63% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 2 0.04% 99.67% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.69% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 14 0.27% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 190864228 # ITB inst accesses +system.cpu1.itb.hits 190777093 # DTB hits +system.cpu1.itb.misses 87135 # DTB misses +system.cpu1.itb.accesses 190864228 # DTB accesses +system.cpu1.numPwrStateTransitions 27368 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 13684 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 3437541610.585575 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 87855050570.390015 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3277 23.95% 23.95% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 10379 75.85% 99.80% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 4 0.03% 99.82% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 2 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::8.5e+11-9e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 7390880676264 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 5169 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 346821221809 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 47038119233191 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 693644050 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 7351150614736 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 13684 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 302603854747 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 47039319399253 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 605218102 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 87527745 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 578391241 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 130931248 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 76096781 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 569305331 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 14062296 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 1768387 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 291884 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 5735168 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 727906 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 800824 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 204645173 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1664411 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 27214 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 673188393 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.008077 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.227099 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 90677216 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 553360207 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 124325317 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 68382826 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 474472155 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 14605284 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1912826 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 316489 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 6235887 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 776312 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 869780 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 190532631 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1731041 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 28903 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 582563307 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.126942 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.253057 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 348457754 51.76% 51.76% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 126514971 18.79% 70.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 42536092 6.32% 76.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 155679576 23.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 272142185 46.71% 46.71% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 117259342 20.13% 66.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 40229436 6.91% 73.75% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 152932344 26.25% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 673188393 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.188759 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.833844 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 102787429 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 312284706 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 218180532 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 34930241 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5005485 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 18306368 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 2064498 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 600925596 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 22793962 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5005485 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 136395689 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 44912882 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 210797905 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 219085305 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 56991127 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 584399745 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 6001663 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 9489847 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 242679 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 273258 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 24369803 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 10662 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 555653486 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 898470064 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 689649249 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 841085 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 500004101 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 55649379 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 14907079 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13060204 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 70305418 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 96437745 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 82644936 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 8695524 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 7557089 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 562795340 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15022202 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 566786483 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2618124 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 52408988 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 33720273 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 259964 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 673188393 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.841943 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.073212 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 582563307 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.205422 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.914315 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 100710093 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 231252575 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 221227930 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 24164908 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5207801 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 44439760 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 2135059 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 575305987 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 23412205 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5207801 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 129334574 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 47434760 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 137391497 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 216168101 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 47026574 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 558184675 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 6143864 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 9881225 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 309237 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 251476 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 25589786 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 13193 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 510403185 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 786411891 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 655895321 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 811726 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 453487095 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 56916084 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 6219044 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 4304916 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 51458924 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 98128925 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 84474197 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8967706 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7764120 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 545083370 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 6336595 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 540345314 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2650065 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 53579246 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 34592760 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 257601 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 582563307 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.927531 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.122571 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 363862102 54.05% 54.05% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 129787759 19.28% 73.33% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 109122281 16.21% 89.54% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 62914886 9.35% 98.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7497321 1.11% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 4044 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 303220433 52.05% 52.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 97196070 16.68% 68.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 110913519 19.04% 87.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 63614426 10.92% 98.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7615367 1.31% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 3492 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 673188393 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 582563307 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 57388953 44.23% 44.23% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 51651 0.04% 44.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 16856 0.01% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMisc 103 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 34250281 26.40% 70.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 37595364 28.98% 99.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMemRead 47943 0.04% 99.70% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMemWrite 388183 0.30% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 57271310 43.60% 43.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 51119 0.04% 43.64% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 18601 0.01% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMisc 112 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.65% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 35025270 26.66% 70.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 38581798 29.37% 99.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemRead 47664 0.04% 99.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemWrite 368619 0.28% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 385773007 68.06% 68.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1187343 0.21% 68.27% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 69773 0.01% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 8 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 13 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 27 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMisc 84205 0.01% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 2 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.30% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 98926523 17.45% 85.75% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 80304665 14.17% 99.92% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMemRead 64060 0.01% 99.93% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMemWrite 376846 0.07% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 76 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 355477037 65.79% 65.79% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1278002 0.24% 66.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 69863 0.01% 66.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 8 0.00% 66.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 66.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.04% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMisc 79928 0.01% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.05% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 100880874 18.67% 84.72% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 82125393 15.20% 99.92% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemRead 69486 0.01% 99.93% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemWrite 364646 0.07% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 566786483 # Type of FU issued -system.cpu1.iq.rate 0.817114 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 129739334 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.228903 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1937625833 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 629808815 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 550243700 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1492982 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 556682 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 518492 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 695564416 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 961390 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2525668 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 540345314 # Type of FU issued +system.cpu1.iq.rate 0.892811 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 131364493 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.243112 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1795817951 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 604594628 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 523100921 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1450540 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 543567 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 507957 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 670779267 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 930464 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2614124 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 12072145 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 16264 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 139965 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5400546 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 12461558 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 17016 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 140230 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5490502 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2506634 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 3911021 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2570995 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 4304841 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5005485 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 6180671 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 1541266 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 577948873 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 5207801 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 6764064 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 1538743 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 551558167 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 96437745 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 82644936 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 12856669 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 62955 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1418771 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 139965 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 1860771 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 3017279 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4878050 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 559031023 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 95939165 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 7216233 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 98128925 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 84474197 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 4043182 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 70701 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1397089 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 140230 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1929682 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 3114694 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 5044376 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 532413736 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 97811900 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 7363284 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 131331 # number of nop insts executed -system.cpu1.iew.exec_refs 175402489 # number of memory reference insts executed -system.cpu1.iew.exec_branches 104887487 # Number of branches executed -system.cpu1.iew.exec_stores 79463324 # Number of stores executed -system.cpu1.iew.exec_rate 0.805934 # Inst execution rate -system.cpu1.iew.wb_sent 551451357 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 550762192 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 266030186 # num instructions producing a value -system.cpu1.iew.wb_consumers 436524752 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.794013 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.609427 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 45696838 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 14762238 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4541996 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 664504904 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.790677 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.583374 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 138202 # number of nop insts executed +system.cpu1.iew.exec_refs 179076621 # number of memory reference insts executed +system.cpu1.iew.exec_branches 97312103 # Number of branches executed +system.cpu1.iew.exec_stores 81264721 # Number of stores executed +system.cpu1.iew.exec_rate 0.879706 # Inst execution rate +system.cpu1.iew.wb_sent 524373694 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 523608878 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 254758095 # num instructions producing a value +system.cpu1.iew.wb_consumers 415275761 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.865157 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.613467 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 46732947 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 6078994 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4683791 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 573586803 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.867943 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.693393 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 434201366 65.34% 65.34% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 119136384 17.93% 83.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 51278197 7.72% 90.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 17339439 2.61% 93.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 12299899 1.85% 95.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 8244778 1.24% 96.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5665589 0.85% 97.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3433584 0.52% 98.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 12905668 1.94% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 375218582 65.42% 65.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 85397429 14.89% 80.30% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 52348334 9.13% 89.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 17503204 3.05% 92.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 12415456 2.16% 94.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 8370820 1.46% 96.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5748485 1.00% 97.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3445775 0.60% 97.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 13138718 2.29% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 664504904 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 446004136 # Number of instructions committed -system.cpu1.commit.committedOps 525408547 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 573586803 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 416374803 # Number of instructions committed +system.cpu1.commit.committedOps 497840712 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 161609989 # Number of memory references committed -system.cpu1.commit.loads 84365599 # Number of loads committed -system.cpu1.commit.membars 3561329 # Number of memory barriers committed -system.cpu1.commit.branches 99629625 # Number of branches committed -system.cpu1.commit.fp_insts 509948 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 482210935 # Number of committed integer instructions. -system.cpu1.commit.function_calls 12864051 # Number of function calls committed. +system.cpu1.commit.refs 164651061 # Number of memory references committed +system.cpu1.commit.loads 85667366 # Number of loads committed +system.cpu1.commit.membars 3698541 # Number of memory barriers committed +system.cpu1.commit.branches 91988554 # Number of branches committed +system.cpu1.commit.fp_insts 499479 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 463071817 # Number of committed integer instructions. +system.cpu1.commit.function_calls 13152854 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 362699186 69.03% 69.03% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 966499 0.18% 69.22% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 55760 0.01% 69.23% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 8 0.00% 69.23% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 13 0.00% 69.23% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 21 0.00% 69.23% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.23% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 69.23% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.23% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMisc 77071 0.01% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.24% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 84306280 16.05% 85.29% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 76870874 14.63% 99.92% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMemRead 59319 0.01% 99.93% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMemWrite 373516 0.07% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 332017365 66.69% 66.69% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1043826 0.21% 66.90% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 55377 0.01% 66.91% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 66.91% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 66.91% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 66.91% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 66.91% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 66.91% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 66.91% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMisc 73083 0.01% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.93% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 85601974 17.19% 84.12% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 78622691 15.79% 99.91% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemRead 65392 0.01% 99.93% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemWrite 361004 0.07% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 525408547 # Class of committed instruction -system.cpu1.commit.bw_lim_events 12905668 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1219098786 # The number of ROB reads -system.cpu1.rob.rob_writes 1150856845 # The number of ROB writes -system.cpu1.timesIdled 925679 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 20455657 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 94076236903 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 446004136 # Number of Instructions Simulated -system.cpu1.committedOps 525408547 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.555241 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.555241 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.642987 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.642987 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 659945611 # number of integer regfile reads -system.cpu1.int_regfile_writes 391450025 # number of integer regfile writes -system.cpu1.fp_regfile_reads 826837 # number of floating regfile reads -system.cpu1.fp_regfile_writes 461620 # number of floating regfile writes -system.cpu1.cc_regfile_reads 120567774 # number of cc regfile reads -system.cpu1.cc_regfile_writes 121287073 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1215585693 # number of misc regfile reads -system.cpu1.misc_regfile_writes 14957440 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 5242137 # number of replacements -system.cpu1.dcache.tags.tagsinuse 459.717362 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 151071021 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5242649 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.815780 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8517875621500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 459.717362 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.897885 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.897885 # Average percentage of cache occupancy +system.cpu1.commit.op_class_0::total 497840712 # Class of committed instruction +system.cpu1.commit.bw_lim_events 13138718 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1100782906 # The number of ROB reads +system.cpu1.rob.rob_writes 1098088032 # The number of ROB writes +system.cpu1.timesIdled 993023 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 22654795 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 94078628435 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 416374803 # Number of Instructions Simulated +system.cpu1.committedOps 497840712 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.453542 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.453542 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.687975 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.687975 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 625781479 # number of integer regfile reads +system.cpu1.int_regfile_writes 379830432 # number of integer regfile writes +system.cpu1.fp_regfile_reads 798661 # number of floating regfile reads +system.cpu1.fp_regfile_writes 473896 # number of floating regfile writes +system.cpu1.cc_regfile_reads 94918566 # number of cc regfile reads +system.cpu1.cc_regfile_writes 95638413 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1053266822 # number of misc regfile reads +system.cpu1.misc_regfile_writes 6252018 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 5530000 # number of replacements +system.cpu1.dcache.tags.tagsinuse 456.074004 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 153151228 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5530512 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.692052 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8516003368500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 456.074004 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890770 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.890770 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 393 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 402 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 335085452 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 335085452 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 78683388 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 78683388 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 67788952 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 67788952 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 181257 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 181257 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 140156 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 140156 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1756750 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1756750 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1770273 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1770273 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 146612496 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 146612496 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 146793753 # number of overall hits -system.cpu1.dcache.overall_hits::total 146793753 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 6126313 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 6126313 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 6911292 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 6911292 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 643081 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 643081 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 451908 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 451908 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 241040 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 241040 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 183733 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 183733 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 13489513 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 13489513 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 14132594 # number of overall misses -system.cpu1.dcache.overall_misses::total 14132594 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 94548549000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 94548549000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 128933568944 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 128933568944 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10455217570 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 10455217570 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3390405500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 3390405500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4379858500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4379858500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2605000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2605000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 233937335514 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 233937335514 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 233937335514 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 233937335514 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 84809701 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 84809701 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 74700244 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 74700244 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 824338 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 824338 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 592064 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 592064 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1997790 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1997790 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1954006 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1954006 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 160102009 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 160102009 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 160926347 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 160926347 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.072236 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.072236 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.092520 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.092520 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.780118 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.780118 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.763276 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.763276 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120653 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120653 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094029 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094029 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.084256 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.084256 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.087820 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.087820 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15433.189424 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15433.189424 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18655.494363 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18655.494363 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23135.721364 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23135.721364 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14065.738052 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14065.738052 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23838.170062 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23838.170062 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 341526918 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 341526918 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 79602961 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 79602961 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 68799990 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 68799990 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187687 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 187687 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 159948 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 159948 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1827869 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1827869 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1836377 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1836377 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 148562899 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 148562899 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 148750586 # number of overall hits +system.cpu1.dcache.overall_hits::total 148750586 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 6412648 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 6412648 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 7514708 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 7514708 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 707982 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 707982 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 465981 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 465981 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 246351 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 246351 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 195484 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 195484 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 14393337 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 14393337 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 15101319 # number of overall misses +system.cpu1.dcache.overall_misses::total 15101319 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 101710324000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 101710324000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 138164152559 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 138164152559 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10841403957 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 10841403957 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3505750500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 3505750500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4668207500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4668207500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2827500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2827500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 250715880516 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 250715880516 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 250715880516 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 250715880516 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 86015609 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 86015609 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 76314698 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 76314698 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 895669 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 895669 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 625929 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 625929 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2074220 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 2074220 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2031861 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 2031861 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 162956236 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 162956236 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 163851905 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 163851905 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074552 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.074552 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.098470 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.098470 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.790450 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.790450 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.744463 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.744463 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.118768 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.118768 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.096209 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.096209 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.088326 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.088326 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.092164 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.092164 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15860.893035 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15860.893035 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18385.831167 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18385.831167 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23265.763962 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23265.763962 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14230.713494 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14230.713494 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23880.253627 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23880.253627 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17342.163169 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17342.163169 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16553.035877 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16553.035877 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 2644851 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 20463296 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 369952 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 688434 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.149173 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 29.724412 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 5242162 # number of writebacks -system.cpu1.dcache.writebacks::total 5242162 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3113636 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3113636 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5578267 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 5578267 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3659 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 3659 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 125068 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 125068 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 8695562 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 8695562 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 8695562 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 8695562 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3012677 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3012677 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1333025 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1333025 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 643006 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 643006 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 448249 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 448249 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 115972 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 115972 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 183726 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 183726 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4793951 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4793951 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5436957 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5436957 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8871 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 8871 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 8695 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 8695 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 17566 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 17566 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 42819104500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 42819104500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26001782801 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26001782801 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14897861000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14897861000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9889085570 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9889085570 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1553813500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1553813500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4196193500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4196193500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2544000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2544000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 78709972871 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 78709972871 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 93607833871 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 93607833871 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1354957000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1354957000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1354957000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1354957000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035523 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035523 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017845 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017845 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.780027 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.780027 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.757096 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.757096 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058050 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058050 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094025 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094025 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029943 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029943 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033785 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033785 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14212.975536 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14212.975536 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19505.847828 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19505.847828 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23169.085514 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23169.085514 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22061.589808 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22061.589808 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13398.178008 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13398.178008 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22839.410318 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22839.410318 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17418.884899 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17418.884899 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16602.250473 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16602.250473 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 2802154 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 21903502 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 386416 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 756136 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.251651 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 28.967675 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 5530029 # number of writebacks +system.cpu1.dcache.writebacks::total 5530029 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3294839 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3294839 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 6084278 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 6084278 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3511 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 3511 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 126189 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 126189 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 9382628 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 9382628 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 9382628 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 9382628 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3117809 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3117809 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1430430 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1430430 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 707901 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 707901 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 462470 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 462470 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120162 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 120162 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195479 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 195479 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 5010709 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 5010709 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5718610 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5718610 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 22964 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 22964 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 21406 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 21406 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 44370 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 44370 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 44191154500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 44191154500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 27737660597 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 27737660597 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 17972389000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 17972389000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10263027957 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10263027957 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1602495500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1602495500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4472798500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4472798500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2757500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2757500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 82191843054 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 82191843054 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 100164232054 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 100164232054 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4057567500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4057567500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4057567500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4057567500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036247 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036247 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018744 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018744 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.790360 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.790360 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.738854 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.738854 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.057931 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.057931 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.096207 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.096207 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030749 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030749 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034901 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034901 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14173.785020 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14173.785020 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19391.134552 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19391.134552 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 25388.280282 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 25388.280282 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22191.770184 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22191.770184 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13336.125397 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13336.125397 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22881.222535 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22881.222535 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16418.601874 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16418.601874 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17216.953136 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17216.953136 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152740.051854 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 152740.051854 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 77135.204372 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 77135.204372 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 5955489 # number of replacements -system.cpu1.icache.tags.tagsinuse 501.186843 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 198342876 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5956001 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 33.301350 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8518419495000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.186843 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.978881 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.978881 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16403.236160 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16403.236160 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17515.485766 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17515.485766 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176692.540498 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176692.540498 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91448.444895 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91448.444895 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 6156366 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.025645 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 184011394 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 6156878 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 29.887127 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8516343949500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.025645 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.978566 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.978566 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 415232377 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 415232377 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 198342876 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 198342876 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 198342876 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 198342876 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 198342876 # number of overall hits -system.cpu1.icache.overall_hits::total 198342876 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 6295293 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 6295293 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 6295293 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 6295293 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 6295293 # number of overall misses -system.cpu1.icache.overall_misses::total 6295293 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 67919445914 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 67919445914 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 67919445914 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 67919445914 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 67919445914 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 67919445914 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 204638169 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 204638169 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 204638169 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 204638169 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 204638169 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 204638169 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030763 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.030763 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030763 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.030763 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030763 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.030763 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10788.925299 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10788.925299 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10788.925299 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10788.925299 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10788.925299 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10788.925299 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 9829448 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 701 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 729519 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.473875 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 233.666667 # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 5955489 # number of writebacks -system.cpu1.icache.writebacks::total 5955489 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 339254 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 339254 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 339254 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 339254 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 339254 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 339254 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5956039 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5956039 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5956039 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5956039 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5956039 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5956039 # number of overall MSHR misses +system.cpu1.icache.tags.tag_accesses 387206970 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 387206970 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 184011394 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 184011394 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 184011394 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 184011394 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 184011394 # number of overall hits +system.cpu1.icache.overall_hits::total 184011394 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 6513585 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 6513585 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 6513585 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 6513585 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 6513585 # number of overall misses +system.cpu1.icache.overall_misses::total 6513585 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 71534475691 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 71534475691 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 71534475691 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 71534475691 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 71534475691 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 71534475691 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 190524979 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 190524979 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 190524979 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 190524979 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 190524979 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 190524979 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.034188 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.034188 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.034188 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.034188 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.034188 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.034188 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10982.350839 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10982.350839 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10982.350839 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10982.350839 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10982.350839 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10982.350839 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 10659560 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 1026 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 770474 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.835068 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 256.500000 # average number of cycles each access was blocked +system.cpu1.icache.writebacks::writebacks 6156366 # number of writebacks +system.cpu1.icache.writebacks::total 6156366 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 356573 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 356573 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 356573 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 356573 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 356573 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 356573 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 6157012 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 6157012 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 6157012 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 6157012 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 6157012 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 6157012 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 61337721519 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 61337721519 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 61337721519 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 61337721519 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 61337721519 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 61337721519 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6801498 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6801498 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6801498 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 6801498 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.029105 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.029105 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.029105 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.029105 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.029105 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.029105 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10298.408308 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10298.408308 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10298.408308 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10298.408308 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10298.408308 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10298.408308 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101514.895522 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101514.895522 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101514.895522 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101514.895522 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7017688 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7023313 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 5116 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 64558641440 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 64558641440 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 64558641440 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 64558641440 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 64558641440 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 64558641440 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7017998 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7017998 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7017998 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 7017998 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.032316 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.032316 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.032316 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.032316 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.032316 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.032316 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10485.385028 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10485.385028 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10485.385028 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10485.385028 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10485.385028 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10485.385028 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 104746.238806 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 104746.238806 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 104746.238806 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 104746.238806 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7532579 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7540263 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 6914 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 831383 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 2042934 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 12933.505047 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 10254699 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2058843 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 4.980807 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 905745 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 2237289 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 12906.637296 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 10683229 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2253034 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 4.741708 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12624.033726 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 36.418354 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 27.691890 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 245.361077 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.770510 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002223 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001690 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014976 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.789399 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 293 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 63 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15553 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 116 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 99 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 69 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 12598.343747 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 34.232851 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 25.792432 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 248.268266 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.768942 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002089 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001574 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.015153 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.787759 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 360 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15324 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 6 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 163 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 96 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 79 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1807 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7301 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4524 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1724 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017883 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003845 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.949280 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 390440087 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 390440087 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 557579 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 186161 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 743740 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 3343376 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 3343376 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 7851276 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 7851276 # number of WritebackClean hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 37 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 859794 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 859794 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5412981 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 5412981 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2828036 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 2828036 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 191737 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 191737 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 557579 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 186161 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 5412981 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3687830 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 9844551 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 557579 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 186161 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 5412981 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3687830 # number of overall hits -system.cpu1.l2cache.overall_hits::total 9844551 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 21615 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9433 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 31048 # number of ReadReq misses -system.cpu1.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses -system.cpu1.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 224939 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 224939 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 183720 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 183720 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 255308 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 255308 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 543023 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 543023 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 939708 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 939708 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 256512 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 256512 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 21615 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9433 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 543023 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1195016 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1769087 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 21615 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9433 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 543023 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1195016 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1769087 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 686942500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 338389000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1025331500 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 939480500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 939480500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 264112000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 264112000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2448496 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2448496 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12203061000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 12203061000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 19608835500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 19608835500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 34743736987 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 34743736987 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 165000 # number of InvalidateReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::total 165000 # number of InvalidateReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 686942500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 338389000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 19608835500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 46946797987 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 67580964987 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 686942500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 338389000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 19608835500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 46946797987 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 67580964987 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 579194 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 195594 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 774788 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3343377 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 3343377 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 7851276 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 7851276 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 224976 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 224976 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 183720 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 183720 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1115102 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1115102 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5956004 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 5956004 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3767744 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 3767744 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 448249 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::total 448249 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 579194 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 195594 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 5956004 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4882846 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 11613638 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 579194 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 195594 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 5956004 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4882846 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 11613638 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.037319 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048227 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.040073 # miss rate for ReadReq accesses -system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000000 # miss rate for WritebackDirty accesses -system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000000 # miss rate for WritebackDirty accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999836 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999836 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 223 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 2395 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7644 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2882 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2180 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.021973 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.935303 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 407515579 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 407515579 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 593172 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 194279 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 787451 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 3518569 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 3518569 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 8164233 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 8164233 # number of WritebackClean hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 105 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 105 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 954506 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 954506 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5573390 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 5573390 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2940198 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 2940198 # number of ReadSharedReq hits +system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 209295 # number of InvalidateReq hits +system.cpu1.l2cache.InvalidateReq_hits::total 209295 # number of InvalidateReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 593172 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 194279 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 5573390 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3894704 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 10255545 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 593172 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 194279 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 5573390 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3894704 # number of overall hits +system.cpu1.l2cache.overall_hits::total 10255545 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 23430 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10710 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 34140 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 228701 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 228701 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 195469 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 195469 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 9 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 254871 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 254871 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 583583 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 583583 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1000824 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 1000824 # number of ReadSharedReq misses +system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 253175 # number of InvalidateReq misses +system.cpu1.l2cache.InvalidateReq_misses::total 253175 # number of InvalidateReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 23430 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10710 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 583583 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1255695 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 1873418 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 23430 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10710 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 583583 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1255695 # number of overall misses +system.cpu1.l2cache.overall_misses::total 1873418 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 794453000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 411582000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 1206035000 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 885247000 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 885247000 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 309725000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 309725000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2651498 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2651498 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 13048454496 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 13048454496 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 21566356000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 21566356000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 38197437985 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 38197437985 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 1037000 # number of InvalidateReq miss cycles +system.cpu1.l2cache.InvalidateReq_miss_latency::total 1037000 # number of InvalidateReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 794453000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 411582000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 21566356000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 51245892481 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 74018283481 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 794453000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 411582000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 21566356000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 51245892481 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 74018283481 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 616602 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 204989 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 821591 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3518569 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 3518569 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 8164233 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 8164233 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 228806 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 228806 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 195470 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 195470 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 9 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 9 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1209377 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1209377 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 6156973 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 6156973 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3941022 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 3941022 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 462470 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::total 462470 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 616602 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 204989 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 6156973 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 5150399 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 12128963 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 616602 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 204989 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 6156973 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 5150399 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 12128963 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.037999 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.052247 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.041554 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999541 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999541 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999995 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999995 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.228955 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.228955 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.091172 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.091172 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.249409 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.249409 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.572253 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.572253 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.037319 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048227 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.091172 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.244738 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.152328 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.037319 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048227 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.091172 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.244738 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.152328 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 31780.823502 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 35872.893035 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 33024.075625 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4176.601212 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4176.601212 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1437.578924 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1437.578924 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 408082.666667 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 408082.666667 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 47797.409404 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 47797.409404 # average ReadExReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36110.506369 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36110.506369 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 36972.907528 # average ReadSharedReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 36972.907528 # average ReadSharedReq miss latency -system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 0.643245 # average InvalidateReq miss latency -system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 0.643245 # average InvalidateReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 31780.823502 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 35872.893035 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36110.506369 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 39285.497422 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 38201.040982 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 31780.823502 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 35872.893035 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36110.506369 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 39285.497422 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 38201.040982 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 345 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.210746 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.210746 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.094784 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.094784 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.253950 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.253950 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.547441 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.547441 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.037999 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.052247 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.094784 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.243805 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.154458 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.037999 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.052247 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.094784 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.243805 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.154458 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 33907.511737 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 38429.691877 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 35326.157001 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 3870.761387 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 3870.761387 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1584.522354 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1584.522354 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 294610.888889 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 294610.888889 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51196.309098 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51196.309098 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36955.079226 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36955.079226 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 38165.989210 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 38165.989210 # average ReadSharedReq miss latency +system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 4.095981 # average InvalidateReq miss latency +system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 4.095981 # average InvalidateReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 33907.511737 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 38429.691877 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36955.079226 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 40810.780071 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 39509.753553 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 33907.511737 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 38429.691877 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36955.079226 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 40810.780071 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 39509.753553 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 273 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 43.125000 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 45.500000 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.unused_prefetches 42412 # number of HardPF blocks evicted w/o reference -system.cpu1.l2cache.writebacks::writebacks 1137390 # number of writebacks -system.cpu1.l2cache.writebacks::total 1137390 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 59 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 256 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 315 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 10963 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 10963 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits -system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 3995 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 3995 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 3 # number of InvalidateReq MSHR hits -system.cpu1.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 59 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 256 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 14958 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 15274 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 59 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 256 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 14958 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 15274 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 21556 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9177 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 30733 # number of ReadReq MSHR misses -system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses -system.cpu1.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 745312 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 745312 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 224939 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 224939 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 183720 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 183720 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 244345 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 244345 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 543022 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 543022 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 935713 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 935713 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 256509 # number of InvalidateReq MSHR misses -system.cpu1.l2cache.InvalidateReq_mshr_misses::total 256509 # number of InvalidateReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 21556 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9177 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 543022 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1180058 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 1753813 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 21556 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9177 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 543022 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1180058 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 745312 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 2499125 # number of overall MSHR misses +system.cpu1.l2cache.unused_prefetches 45092 # number of HardPF blocks evicted w/o reference +system.cpu1.l2cache.writebacks::writebacks 1265703 # number of writebacks +system.cpu1.l2cache.writebacks::total 1265703 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 89 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 277 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 366 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 14520 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 14520 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 6 # number of ReadCleanReq MSHR hits +system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 6 # number of ReadCleanReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 4370 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 4370 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 4 # number of InvalidateReq MSHR hits +system.cpu1.l2cache.InvalidateReq_mshr_hits::total 4 # number of InvalidateReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 89 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 277 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 18890 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 19262 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 89 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 277 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 18890 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 19262 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 23341 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10433 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 33774 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 793498 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 793498 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 228701 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 228701 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 195469 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 195469 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 9 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 240351 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 240351 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 583577 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 583577 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 996454 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 996454 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 253171 # number of InvalidateReq MSHR misses +system.cpu1.l2cache.InvalidateReq_mshr_misses::total 253171 # number of InvalidateReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 23341 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10433 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 583577 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1236805 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 1854156 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 23341 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10433 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 583577 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1236805 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 793498 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 2647654 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 8871 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 8938 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 8695 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 8695 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 22964 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 23031 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 21406 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 21406 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 17566 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 17633 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 556465500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 279014500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 835480000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 36237678760 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 36237678760 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4227924487 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4227924487 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2815609497 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2815609497 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2082496 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2082496 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9065423000 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9065423000 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 16350690000 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 16350690000 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 28869020987 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 28869020987 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 5973751999 # number of InvalidateReq MSHR miss cycles -system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 5973751999 # number of InvalidateReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 556465500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 279014500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 16350690000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 37934443987 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 55120613987 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 556465500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 279014500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 16350690000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 37934443987 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 36237678760 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 91358292747 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6298000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1283792500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1290090500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6298000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1283792500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1290090500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.037217 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.046919 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.039666 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses -system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 44370 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 44437 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 652898000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 343913500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 996811500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 46156066571 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 46156066571 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4295864494 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4295864494 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3003825995 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3003825995 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2231498 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2231498 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9417872000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9417872000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 18064709000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 18064709000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 31901371985 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 31901371985 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6217720498 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6217720498 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 652898000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 343913500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 18064709000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 41319243985 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 60380764485 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 652898000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 343913500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 18064709000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 41319243985 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 46156066571 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 106536831056 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6514500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3873635500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3880150000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6514500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3873635500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3880150000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.037854 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050895 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.041108 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999836 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999836 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999541 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999541 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999995 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.219123 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.219123 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.091172 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.091172 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.248348 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248348 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.572247 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.572247 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.037217 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046919 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.091172 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.241674 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.151013 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.037217 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046919 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.091172 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.241674 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.198740 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.198740 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.094783 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.094783 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.252842 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.252842 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.547432 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.547432 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.037854 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050895 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.094783 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.240138 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.152870 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.037854 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050895 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.094783 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.240138 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.215189 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 25814.877528 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30403.672224 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 27185.110468 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48620.817537 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48620.817537 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18795.871267 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18795.871267 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15325.547012 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15325.547012 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 347082.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 347082.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37100.914690 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37100.914690 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30110.548007 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30110.548007 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 30852.431234 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30852.431234 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23288.664331 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23288.664331 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 25814.877528 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30403.672224 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30110.548007 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32146.253817 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31429.014374 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 25814.877528 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30403.672224 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30110.548007 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32146.253817 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48620.817537 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36556.111738 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94000 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 144717.901026 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 144337.715373 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94000 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 73083.940567 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 73163.415187 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 23228623 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11943528 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 5072 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 598776 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 598706 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 70 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 867379 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10679013 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 8695 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 8695 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4499349 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 7854270 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 1254191 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 938082 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 428069 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 332128 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 468300 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 113 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1145370 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1120388 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5956039 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4785637 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 521245 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 449809 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17867666 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16911297 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 409122 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1224107 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 36412192 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 762336624 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 654015560 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1564752 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4633552 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1422550488 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5059056 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 80617704 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 17392868 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.053991 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.226018 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.218292 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 27972.152007 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 32964.008435 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 29514.167703 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58167.842352 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 58167.842352 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18783.759118 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18783.759118 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15367.275604 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15367.275604 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 247944.222222 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 247944.222222 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 39183.826986 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 39183.826986 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30955.142166 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30955.142166 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32014.896809 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32014.896809 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 24559.370931 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 24559.370931 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 27972.152007 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 32964.008435 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30955.142166 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 33408.050570 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32565.094029 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 27972.152007 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 32964.008435 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30955.142166 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 33408.050570 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58167.842352 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 40238.199952 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 97231.343284 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168682.960286 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 168475.098780 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 97231.343284 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87303.031327 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87318.000765 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 24247915 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 12479959 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 8015 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 603053 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 602834 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 219 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 936644 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 11117136 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 21406 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 21406 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4809330 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 8167824 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 1368728 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 1012133 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 404751 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 355876 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 480511 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1238980 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1214897 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 6157012 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4940216 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 522762 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 463422 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18470485 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17838362 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 429531 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1305673 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 38044051 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 788054768 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 689328153 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1639912 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4932816 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1483955649 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5334462 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 88980784 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 18249337 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.053626 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.225332 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 16453876 94.60% 94.60% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 938922 5.40% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 70 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 17270909 94.64% 94.64% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 978209 5.36% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 219 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 17392868 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 23086793966 # Layer occupancy (ticks) -system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 170580468 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 18249337 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 24116423481 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 160883108 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8939751182 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 9241921761 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7774836803 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 8211674528 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 213941664 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 224968642 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 645834647 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 690043535 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40408 # Transaction distribution -system.iobus.trans_dist::ReadResp 40408 # Transaction distribution -system.iobus.trans_dist::WriteReq 136658 # Transaction distribution -system.iobus.trans_dist::WriteResp 136658 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47776 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40285 # Transaction distribution +system.iobus.trans_dist::ReadResp 40285 # Transaction distribution +system.iobus.trans_dist::WriteReq 136579 # Transaction distribution +system.iobus.trans_dist::WriteResp 136579 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47524 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -3026,15 +3027,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122710 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231342 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231342 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122406 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231242 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354132 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47796 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353728 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47544 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -3045,21 +3046,21 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155817 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339384 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7339384 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338984 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338984 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7497287 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 37041003 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496606 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36861002 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 331500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 327000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -3069,81 +3070,81 @@ system.iobus.reqLayer13.occupancy 9500 # La system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 24305002 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 24160506 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36394500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36392501 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 570335330 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 570209840 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92783000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92558000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148038000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147938000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115667 # number of replacements -system.iocache.tags.tagsinuse 11.289924 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115633 # number of replacements +system.iocache.tags.tagsinuse 11.369333 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115683 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115649 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9156457442000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.417343 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.872581 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463584 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.242036 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705620 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9154282048000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.419555 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.949778 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463722 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.246861 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.710583 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1041396 # Number of tag accesses -system.iocache.tags.data_accesses 1041396 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1040946 # Number of tag accesses +system.iocache.tags.data_accesses 1040946 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8943 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8980 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8893 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8930 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115671 # number of demand (read+write) misses -system.iocache.demand_misses::total 115711 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115621 # number of demand (read+write) misses +system.iocache.demand_misses::total 115661 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115671 # number of overall misses -system.iocache.overall_misses::total 115711 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5200000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1878808543 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1884008543 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 370000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 370000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13080956787 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13080956787 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5570000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14959765330 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14965335330 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5570000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14959765330 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14965335330 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 115621 # number of overall misses +system.iocache.overall_misses::total 115661 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5192500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1787370736 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1792563236 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12950575604 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12950575604 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5561500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14737946340 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14743507840 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5561500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14737946340 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14743507840 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8943 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8980 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8893 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8930 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115671 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115711 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115621 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115661 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115671 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115711 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115621 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115661 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -3157,53 +3158,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140540.540541 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 210087.056133 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 209800.505902 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123333.333333 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 123333.333333 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 122563.495868 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 122563.495868 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139250 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 129330.301718 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 129333.730847 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139250 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 129330.301718 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 129333.730847 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 43850 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140337.837838 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 200986.251659 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 200734.964838 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121341.874710 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 121341.874710 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139037.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 127467.729392 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 127471.730661 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139037.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 127467.729392 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 127471.730661 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 39227 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3467 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3536 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.647822 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.093609 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106694 # number of writebacks -system.iocache.writebacks::total 106694 # number of writebacks +system.iocache.writebacks::writebacks 106710 # number of writebacks +system.iocache.writebacks::total 106710 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8943 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8980 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8893 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8930 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115671 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115711 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115621 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115661 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115671 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115711 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3350000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1431658543 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1435008543 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 220000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 220000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7738901569 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7738901569 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3570000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9170560112 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9174130112 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3570000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9170560112 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9174130112 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115621 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115661 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3342500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1342720736 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1346063236 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7608008190 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7608008190 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3561500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8950728926 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8954290426 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3561500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8950728926 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8954290426 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -3217,656 +3218,658 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90540.540541 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 160087.056133 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 159800.505902 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73333.333333 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 73333.333333 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 72510.508667 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 72510.508667 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89250 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 79281.411175 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 79284.857205 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89250 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 79281.411175 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 79284.857205 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1625787 # number of replacements -system.l2c.tags.tagsinuse 65181.204595 # Cycle average of tags in use -system.l2c.tags.total_refs 6817657 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1687923 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.039081 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 3083223500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 9617.868100 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 445.484302 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 525.919749 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4087.647415 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 22210.879235 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 20823.279726 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 29.752566 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 32.095436 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2691.005366 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3224.848807 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1492.423894 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.146757 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.006798 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.008025 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.062373 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.338911 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.317738 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000454 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000490 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.041061 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.049207 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.022773 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994586 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 12119 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 287 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 49730 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 1349 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 918 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9840 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 283 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2201 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4435 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 42789 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.184921 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.004379 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.758820 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 77430161 # Number of tag accesses -system.l2c.tags.data_accesses 77430161 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2884653 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2884653 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 199415 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 166641 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 366056 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 54285 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 48308 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 102593 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 52113 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 55927 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 108040 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 12524 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4903 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 523305 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 612159 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 287889 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 14056 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5296 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 496370 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 569933 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 304905 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2831340 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 116676 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 127973 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 244649 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 12524 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4903 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 523305 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 664272 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 287889 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 14056 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5296 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 496370 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 625860 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 304905 # number of demand (read+write) hits -system.l2c.demand_hits::total 2939380 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 12524 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4903 # number of overall hits -system.l2c.overall_hits::cpu0.inst 523305 # number of overall hits -system.l2c.overall_hits::cpu0.data 664272 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 287889 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 14056 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5296 # number of overall hits -system.l2c.overall_hits::cpu1.inst 496370 # number of overall hits -system.l2c.overall_hits::cpu1.data 625860 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 304905 # number of overall hits -system.l2c.overall_hits::total 2939380 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 23367 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 23265 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 46632 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 687 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 824 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1511 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 90180 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 49097 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 139277 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3479 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3368 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 64819 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 175048 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 338569 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1814 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1250 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 46649 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 114016 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 201392 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 950404 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 450671 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 82488 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 533159 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 3479 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 3368 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 64819 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 265228 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 338569 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1814 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1250 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 46649 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 163113 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 201392 # number of demand (read+write) misses -system.l2c.demand_misses::total 1089681 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 3479 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 3368 # number of overall misses -system.l2c.overall_misses::cpu0.inst 64819 # number of overall misses -system.l2c.overall_misses::cpu0.data 265228 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 338569 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1814 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1250 # number of overall misses -system.l2c.overall_misses::cpu1.inst 46649 # number of overall misses -system.l2c.overall_misses::cpu1.data 163113 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 201392 # number of overall misses -system.l2c.overall_misses::total 1089681 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 136803000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 150683000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 287486000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 9622000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 7084500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 16706500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 9842771994 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5304657999 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 15147429993 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 352314500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 351549500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 7169242500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 19597785998 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 51686460606 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 196164500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 138775500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 5424777500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 13175715998 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 30642096870 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 128734883472 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 352314500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 351549500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 7169242500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 29440557992 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 51686460606 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 196164500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 138775500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 5424777500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 18480373997 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 30642096870 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 143882313465 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 352314500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 351549500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 7169242500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 29440557992 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 51686460606 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 196164500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 138775500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 5424777500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 18480373997 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 30642096870 # number of overall miss cycles -system.l2c.overall_miss_latency::total 143882313465 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 2884653 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 2884653 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 222782 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 189906 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 412688 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 54972 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 49132 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 104104 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 142293 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 105024 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247317 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 16003 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 8271 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 588124 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 787207 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 626458 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 15870 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6546 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 543019 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 683949 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 506297 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 3781744 # number of ReadSharedReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu0.data 567347 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu1.data 210461 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::total 777808 # number of InvalidateReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 16003 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 8271 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 588124 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 929500 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 626458 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 15870 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6546 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 543019 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 788973 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 506297 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 4029061 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 16003 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 8271 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 588124 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 929500 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 626458 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 15870 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6546 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 543019 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 788973 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 506297 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 4029061 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.104887 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.122508 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.112996 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.012497 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.016771 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.014514 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.633763 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.467484 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.563152 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.217397 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.407206 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.110213 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.222366 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.540450 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.114304 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.190956 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.085907 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.166702 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.397774 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.251314 # miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_miss_rate::cpu0.data 0.794348 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::cpu1.data 0.391940 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::total 0.685464 # miss rate for InvalidateReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.217397 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.407206 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.110213 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.285345 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.540450 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.114304 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.190956 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.085907 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.206741 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.397774 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.270455 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.217397 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.407206 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.110213 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.285345 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.540450 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.114304 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.190956 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.085907 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.206741 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.397774 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.270455 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5854.538452 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6476.810660 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 6164.993996 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14005.822416 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 8597.694175 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 11056.585043 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 109145.841583 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 108044.442614 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 108757.583758 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 101268.899109 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 104379.305226 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 110604.028140 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 111956.640453 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 152661.527210 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 108139.195149 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 111020.400000 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 116289.255933 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 115560.237142 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 152151.509842 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 135452.800569 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 101268.899109 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 104379.305226 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 110604.028140 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 111000.942555 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 152661.527210 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 108139.195149 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 111020.400000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 116289.255933 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 113297.983588 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 152151.509842 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 132040.765568 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 101268.899109 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 104379.305226 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 110604.028140 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 111000.942555 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 152661.527210 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 108139.195149 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 111020.400000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 116289.255933 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 113297.983588 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 152151.509842 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 132040.765568 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 7046 # number of cycles access was blocked +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90337.837838 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 150986.251659 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 150734.964838 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71284.088430 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71284.088430 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89037.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 77414.387750 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 77418.407467 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89037.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 77414.387750 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 77418.407467 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 1858608 # number of replacements +system.l2c.tags.tagsinuse 65222.891140 # Cycle average of tags in use +system.l2c.tags.total_refs 7355255 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1920213 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.830437 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 1229429500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 10209.698759 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 401.592309 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 445.016269 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3734.616961 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 21322.764244 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 18260.159461 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 76.119212 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 86.745152 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3160.425498 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 4267.065632 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3258.687641 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.155788 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.006128 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.006790 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.056986 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.325360 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.278628 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001161 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.001324 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.048224 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.065110 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.049724 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995222 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 11759 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 304 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 49542 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 196 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 891 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 10670 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::1 12 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 292 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 367 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2478 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2877 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 43809 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.179428 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.004639 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.755951 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 84121444 # Number of tag accesses +system.l2c.tags.data_accesses 84121444 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 3161961 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 3161961 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 218473 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 178227 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 396700 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 60416 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 50161 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 110577 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 54320 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 59150 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113470 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 13417 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5017 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 539007 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 668528 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 293105 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 15148 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 6130 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 525725 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 626529 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 298432 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 2991038 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 122623 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 121091 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 243714 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 13417 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 5017 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 539007 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 722848 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 293105 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 15148 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6130 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 525725 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 685679 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 298432 # number of demand (read+write) hits +system.l2c.demand_hits::total 3104508 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 13417 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 5017 # number of overall hits +system.l2c.overall_hits::cpu0.inst 539007 # number of overall hits +system.l2c.overall_hits::cpu0.data 722848 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 293105 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 15148 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6130 # number of overall hits +system.l2c.overall_hits::cpu1.inst 525725 # number of overall hits +system.l2c.overall_hits::cpu1.data 685679 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 298432 # number of overall hits +system.l2c.overall_hits::total 3104508 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 21614 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 22773 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 44387 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 1033 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1052 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2085 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 96389 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 53149 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 149538 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3784 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3652 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 65121 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 199292 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 394602 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2497 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1730 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 57847 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 128371 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 264210 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 1121106 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 461443 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu1.data 96191 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 557634 # number of InvalidateReq misses +system.l2c.demand_misses::cpu0.dtb.walker 3784 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 3652 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 65121 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 295681 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 394602 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 2497 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1730 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 57847 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 181520 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 264210 # number of demand (read+write) misses +system.l2c.demand_misses::total 1270644 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 3784 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 3652 # number of overall misses +system.l2c.overall_misses::cpu0.inst 65121 # number of overall misses +system.l2c.overall_misses::cpu0.data 295681 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 394602 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 2497 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1730 # number of overall misses +system.l2c.overall_misses::cpu1.inst 57847 # number of overall misses +system.l2c.overall_misses::cpu1.data 181520 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 264210 # number of overall misses +system.l2c.overall_misses::total 1270644 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 151083000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 144162500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 295245500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 9029500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 10650000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 19679500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 10395447993 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 5744671997 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 16140119990 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 381693500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 359292500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 7105700999 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 21857572496 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 60806343315 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 266793000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 185648500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6445588500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 15192688491 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 40621267426 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 153222588727 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 381693500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 359292500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 7105700999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 32253020489 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 60806343315 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 266793000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 185648500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 6445588500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 20937360488 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 40621267426 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 169362708717 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 381693500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 359292500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 7105700999 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 32253020489 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 60806343315 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 266793000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 185648500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 6445588500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 20937360488 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 40621267426 # number of overall miss cycles +system.l2c.overall_miss_latency::total 169362708717 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 3161961 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 3161961 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 240087 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 201000 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 441087 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 61449 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 51213 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 112662 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 150709 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 112299 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 263008 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 17201 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 8669 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 604128 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 867820 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 687707 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 17645 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7860 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 583572 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 754900 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 562642 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 4112144 # number of ReadSharedReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu0.data 584066 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu1.data 217282 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::total 801348 # number of InvalidateReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 17201 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 8669 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 604128 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1018529 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 687707 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 17645 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7860 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 583572 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 867199 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 562642 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 4375152 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 17201 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 8669 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 604128 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1018529 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 687707 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 17645 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7860 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 583572 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 867199 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 562642 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 4375152 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.090026 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.113299 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.100631 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.016811 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.020542 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.018507 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.639570 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.473281 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.568568 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.219987 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.421271 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.107793 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.229647 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.573794 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.141513 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.220102 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.099126 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.170050 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.469588 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.272633 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.790053 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu1.data 0.442701 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.695870 # miss rate for InvalidateReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.219987 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.421271 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.107793 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.290302 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.573794 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.141513 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.220102 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.099126 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.209318 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.469588 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.290423 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.219987 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.421271 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.107793 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.290302 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.573794 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.141513 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.220102 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.099126 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.209318 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.469588 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.290423 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6990.052744 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6330.413209 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 6651.620970 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 8741.045499 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 10123.574144 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 9438.609113 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 107848.903848 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 108086.172778 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 107933.234295 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 100870.375264 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 98382.393209 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 109115.354479 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 109676.115930 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 154095.375378 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 106845.414497 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 107311.271676 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 111424.767058 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 118349.849195 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 153746.139154 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 136670.920258 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 100870.375264 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 98382.393209 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 109115.354479 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 109080.463368 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 154095.375378 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 106845.414497 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 107311.271676 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 111424.767058 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 115344.647907 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 153746.139154 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 133288.874553 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 100870.375264 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 98382.393209 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 109115.354479 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 109080.463368 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 154095.375378 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 106845.414497 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 107311.271676 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 111424.767058 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 115344.647907 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 153746.139154 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 133288.874553 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 15677 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 62 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 153 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 113.645161 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 102.464052 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 1244548 # number of writebacks -system.l2c.writebacks::total 1244548 # number of writebacks -system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 102 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0.data 15 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 118 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.data 19 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 254 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 102 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 118 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 19 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 102 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 118 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 19 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 254 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 67228 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 67228 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 23367 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 23265 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 46632 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 687 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 824 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1511 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 90180 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 49097 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 139277 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 3479 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3368 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 64717 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 175033 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 338569 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1814 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1250 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 46531 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 113997 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 201392 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 950150 # number of ReadSharedReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::cpu0.data 450671 # number of InvalidateReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::cpu1.data 82488 # number of InvalidateReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::total 533159 # number of InvalidateReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 3479 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 3368 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 64717 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 265213 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 338569 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 1814 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 1250 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 46531 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 163094 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 201392 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 1089427 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 3479 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 3368 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 64717 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 265213 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 338569 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 1814 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 1250 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 46531 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 163094 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 201392 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 1089427 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 29615 # number of ReadReq MSHR uncacheable +system.l2c.writebacks::writebacks 1420191 # number of writebacks +system.l2c.writebacks::total 1420191 # number of writebacks +system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 100 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0.data 8 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher 1 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 184 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.data 35 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 328 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 100 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 184 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 35 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 100 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 184 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 35 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 328 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 84488 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 84488 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 21614 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 22773 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 44387 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1033 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1052 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 2085 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 96389 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 53149 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 149538 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 3784 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3652 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 65021 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 199284 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 394601 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2497 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1730 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 57663 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 128336 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 264210 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 1120778 # number of ReadSharedReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::cpu0.data 461443 # number of InvalidateReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::cpu1.data 96191 # number of InvalidateReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::total 557634 # number of InvalidateReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 3784 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 3652 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 65021 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 295673 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 394601 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 2497 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1730 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 57663 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 181485 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 264210 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 1270316 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 3784 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 3652 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 65021 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 295673 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 394601 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 2497 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1730 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 57663 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 181485 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 264210 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 1270316 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 2093 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 15843 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 8869 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 59844 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 29691 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 8695 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 38386 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 59306 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 22962 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 40965 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 17283 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 21406 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 38689 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 2093 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 33126 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 17564 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 98230 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 466632500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 483108499 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 949740999 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 16616499 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 20367500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 36983999 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8940824795 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4813505389 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 13754330184 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 317523502 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 317869500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 6512407062 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17845292687 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 48300635417 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 178023502 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 126275001 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 4948966536 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 12033347692 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 28627972330 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 119208313229 # number of ReadSharedReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 11145696799 # number of InvalidateReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1615953000 # number of InvalidateReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::total 12761649799 # number of InvalidateReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 317523502 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 317869500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 6512407062 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 26786117482 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 48300635417 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 178023502 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 126275001 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 4948966536 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 16846853081 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 28627972330 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 132962643413 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 317523502 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 317869500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 6512407062 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 26786117482 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 48300635417 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 178023502 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 126275001 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 4948966536 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 16846853081 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 28627972330 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 132962643413 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1484185500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4824158502 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5090000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1123983502 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 7437417504 # number of ReadReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1484185500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4824158502 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5090000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1123983502 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 7437417504 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 44368 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 79654 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 437927500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 473487498 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 911414998 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 24955000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 25870500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 50825500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 9431397842 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5212978417 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 14644376259 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 343853001 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 322772001 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 6445445567 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19863990276 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 56859943438 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 241821503 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 168348500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5850563554 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 13904670289 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 37978912479 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 141980320608 # number of ReadSharedReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 11387571771 # number of InvalidateReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1886134001 # number of InvalidateReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::total 13273705772 # number of InvalidateReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 343853001 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 322772001 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 6445445567 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 29295388118 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 56859943438 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 241821503 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 168348500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 5850563554 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 19117648706 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 37978912479 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 156624696867 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 343853001 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 322772001 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 6445445567 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 29295388118 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 56859943438 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 241821503 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 168348500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 5850563554 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 19117648706 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 37978912479 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 156624696867 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 147855500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2484594002 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5308000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3460097504 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6097855006 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 147855500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2484594002 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5308000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3460097504 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 6097855006 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.104887 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.122508 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.112996 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.012497 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.016771 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.014514 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.633763 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.467484 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.563152 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.217397 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.407206 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.110040 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.222347 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.540450 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.114304 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.190956 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.085689 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.166675 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.397774 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.251247 # mshr miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.794348 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.391940 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::total 0.685464 # mshr miss rate for InvalidateReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.217397 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.407206 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.110040 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.285329 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.540450 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.114304 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.190956 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.085689 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.206717 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.397774 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.270392 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.217397 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.407206 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.110040 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.285329 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.540450 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.114304 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.190956 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.085689 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.206717 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.397774 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.270392 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19969.722258 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20765.463099 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20366.722401 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24187.043668 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24717.839806 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24476.504964 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 99144.209304 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 98040.723242 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 98755.215750 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 91268.612245 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 94379.305226 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 100629.001066 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 101953.875481 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142661.127915 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 98138.644983 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 101020.000800 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 106358.482216 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 105558.459363 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142150.494210 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 125462.625090 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24731.337936 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19590.158569 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 23935.917426 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 91268.612245 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 94379.305226 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 100629.001066 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 100998.508678 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142661.127915 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 98138.644983 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 101020.000800 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 106358.482216 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 103295.357775 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142150.494210 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 122048.235828 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 91268.612245 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 94379.305226 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 100629.001066 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 100998.508678 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142661.127915 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 98138.644983 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 101020.000800 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 106358.482216 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 103295.357775 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142150.494210 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 122048.235828 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69702.977504 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 162895.779233 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 75970.149254 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 126731.706168 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 124280.086625 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69702.977504 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 81343.515024 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 75970.149254 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 63993.594967 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 75714.318477 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 4039865 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2364937 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3552 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.090026 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.113299 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.100631 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.016811 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.020542 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.018507 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.639570 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.473281 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.568568 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.219987 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.421271 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.107628 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.229637 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.573792 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.141513 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.220102 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.098810 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.170004 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.469588 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.272553 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.790053 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.442701 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.695870 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.219987 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.421271 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.107628 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.290294 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.573792 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.141513 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.220102 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.098810 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.209277 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.469588 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.290348 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.219987 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.421271 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.107628 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.290294 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.573792 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.141513 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.220102 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.098810 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.209277 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.469588 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.290348 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20261.288979 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20791.617178 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20533.376845 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24157.792836 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24591.730038 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24376.738609 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 97847.242341 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 98082.342415 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 97930.801930 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 90870.243393 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 88382.256572 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99128.674844 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 99676.794304 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 144094.777859 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 96844.814978 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 97311.271676 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 101461.310615 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 108345.828832 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143745.174214 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126680.145941 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24678.176440 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19608.216995 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 23803.616300 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 90870.243393 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 88382.256572 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99128.674844 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99080.362827 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 144094.777859 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 96844.814978 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 97311.271676 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 101461.310615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 105340.103623 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143745.174214 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 123295.854628 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 90870.243393 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 88382.256572 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99128.674844 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99080.362827 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 144094.777859 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 96844.814978 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 97311.271676 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 101461.310615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 105340.103623 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143745.174214 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 123295.854628 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70642.857143 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 156825.980054 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 79223.880597 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150687.984670 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 148855.242426 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70642.857143 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 75004.347099 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 79223.880597 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 77986.330328 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 76554.284857 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 4427188 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2544778 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3484 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 59844 # Transaction distribution -system.membus.trans_dist::ReadResp 1018974 # Transaction distribution -system.membus.trans_dist::WriteReq 38386 # Transaction distribution -system.membus.trans_dist::WriteResp 38386 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1351242 # Transaction distribution -system.membus.trans_dist::CleanEvict 267627 # Transaction distribution -system.membus.trans_dist::UpgradeReq 336754 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 267840 # Transaction distribution -system.membus.trans_dist::UpgradeResp 23 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution -system.membus.trans_dist::ReadExReq 152823 # Transaction distribution -system.membus.trans_dist::ReadExResp 138565 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 959130 # Transaction distribution -system.membus.trans_dist::InvalidateReq 652932 # Transaction distribution -system.membus.trans_dist::InvalidateResp 30629 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122710 # Packet count per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 40965 # Transaction distribution +system.membus.trans_dist::ReadResp 1170673 # Transaction distribution +system.membus.trans_dist::WriteReq 38689 # Transaction distribution +system.membus.trans_dist::WriteResp 38689 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1526901 # Transaction distribution +system.membus.trans_dist::CleanEvict 301973 # Transaction distribution +system.membus.trans_dist::UpgradeReq 291943 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 287508 # Transaction distribution +system.membus.trans_dist::UpgradeResp 8 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 162891 # Transaction distribution +system.membus.trans_dist::ReadExResp 148894 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1129708 # Transaction distribution +system.membus.trans_dist::InvalidateReq 674487 # Transaction distribution +system.membus.trans_dist::InvalidateResp 26345 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122406 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25810 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4892821 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5041417 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237968 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237968 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5279385 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155817 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27362 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5422541 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5572385 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238081 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238081 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5810466 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155536 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51620 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 149644096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 149852089 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7250176 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7250176 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 157102265 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 616817 # Total snoops (count) -system.membus.snoopTraffic 199808 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2467715 # Request fanout histogram -system.membus.snoop_fanout::mean 0.013862 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.116919 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54724 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 172160384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 172371200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7263808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7263808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 179635008 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 585668 # Total snoops (count) +system.membus.snoopTraffic 182912 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2626196 # Request fanout histogram +system.membus.snoop_fanout::mean 0.011361 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.105982 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2433507 98.61% 98.61% # Request fanout histogram -system.membus.snoop_fanout::1 34208 1.39% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2596359 98.86% 98.86% # Request fanout histogram +system.membus.snoop_fanout::1 29837 1.14% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2467715 # Request fanout histogram -system.membus.reqLayer0.occupancy 98169995 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2626196 # Request fanout histogram +system.membus.reqLayer0.occupancy 97843991 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21686998 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22899493 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9247698101 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 10387724889 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5871093052 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6773203746 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 81490219 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 76561844 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3909,82 +3912,83 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 12086303 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6387551 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2235502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 239971 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 217052 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 22919 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 59846 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4613854 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38386 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38386 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 4129201 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2768870 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 702098 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 370433 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1072531 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 113 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 113 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298786 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298786 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4554900 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 905153 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 886862 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9925339 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7679367 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17604706 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 251196049 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 191962664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 443158713 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3147878 # Total snoops (count) -system.toL2Bus.snoopTraffic 132377296 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 8556431 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.371457 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.488706 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 12840687 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6804210 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2233432 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 286650 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 259465 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 27185 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 40967 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4895074 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38689 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38689 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 4582152 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2976886 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 687999 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 398085 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1086084 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 122 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 311857 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 311857 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4854758 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 900244 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 885499 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10402586 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8325072 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 18727658 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 271068295 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 211681017 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 482749312 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3295138 # Total snoops (count) +system.toL2Bus.snoopTraffic 141512016 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 9092383 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.348495 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.482728 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5401002 63.12% 63.12% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3132510 36.61% 99.73% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 22919 0.27% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5950920 65.45% 65.45% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3114278 34.25% 99.70% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 27185 0.30% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8556431 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9443624545 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 9092383 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 10118543300 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 9237873 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 8937131 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4533014073 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4714839859 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3814018472 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4090244927 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13606 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 5530 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5169 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 13684 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index fa5414686..982f55812 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -1,140 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.558690 # Number of seconds simulated -sim_ticks 51558689626000 # Number of ticks simulated -final_tick 51558689626000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.277959 # Number of seconds simulated +sim_ticks 51277959410000 # Number of ticks simulated +final_tick 51277959410000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 210245 # Simulator instruction rate (inst/s) -host_op_rate 247121 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9737217389 # Simulator tick rate (ticks/s) -host_mem_usage 695392 # Number of bytes of host memory used -host_seconds 5295.01 # Real time elapsed on the host -sim_insts 1113248331 # Number of instructions simulated -sim_ops 1308509399 # Number of ops (including micro ops) simulated +host_inst_rate 210382 # Simulator instruction rate (inst/s) +host_op_rate 250295 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 13357159040 # Simulator tick rate (ticks/s) +host_mem_usage 689664 # Number of bytes of host memory used +host_seconds 3838.99 # Real time elapsed on the host +sim_insts 807652759 # Number of instructions simulated +sim_ops 960879271 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 688064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 572736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 6466080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 114242184 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 427328 # Number of bytes read from this memory -system.physmem.bytes_read::total 122396392 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 6466080 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6466080 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 142998784 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 253184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 234496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5589856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 47714440 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 412800 # Number of bytes read from this memory +system.physmem.bytes_read::total 54204776 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5589856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5589856 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 74605824 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 143019364 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 10751 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 8949 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 116985 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1785047 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6677 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1928409 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2234356 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 74626404 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3956 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3664 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 88894 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 745551 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6450 # Number of read requests responded to by this memory +system.physmem.num_reads::total 848515 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1165716 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2236929 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 13345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 11108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 125412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2215770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8288 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2373924 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 125412 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 125412 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2773515 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2773914 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2773515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 13345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 11108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 125412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2216169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5147838 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1928410 # Number of read requests accepted -system.physmem.writeReqs 2236929 # Number of write requests accepted -system.physmem.readBursts 1928410 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2236929 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 123382976 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 35200 # Total number of bytes read from write queue -system.physmem.bytesWritten 143016896 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 122396456 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 143019364 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 550 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2266 # Number of DRAM write bursts merged with an existing one +system.physmem.num_writes::total 1168289 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 4937 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 4573 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 109011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 930506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1057077 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 109011 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 109011 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1454930 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1455331 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1454930 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 4937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 4573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 109011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 930907 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2512408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 848516 # Number of read requests accepted +system.physmem.writeReqs 1168289 # Number of write requests accepted +system.physmem.readBursts 848516 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1168289 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 54258624 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 46336 # Total number of bytes read from write queue +system.physmem.bytesWritten 74623296 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 54204840 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 74626404 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 724 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2278 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 114164 # Per bank write bursts -system.physmem.perBankRdBursts::1 120325 # Per bank write bursts -system.physmem.perBankRdBursts::2 121021 # Per bank write bursts -system.physmem.perBankRdBursts::3 117289 # Per bank write bursts -system.physmem.perBankRdBursts::4 115474 # Per bank write bursts -system.physmem.perBankRdBursts::5 125294 # Per bank write bursts -system.physmem.perBankRdBursts::6 117554 # Per bank write bursts -system.physmem.perBankRdBursts::7 120469 # Per bank write bursts -system.physmem.perBankRdBursts::8 115697 # Per bank write bursts -system.physmem.perBankRdBursts::9 146662 # Per bank write bursts -system.physmem.perBankRdBursts::10 119160 # Per bank write bursts -system.physmem.perBankRdBursts::11 123181 # Per bank write bursts -system.physmem.perBankRdBursts::12 118002 # Per bank write bursts -system.physmem.perBankRdBursts::13 121360 # Per bank write bursts -system.physmem.perBankRdBursts::14 114093 # Per bank write bursts -system.physmem.perBankRdBursts::15 118114 # Per bank write bursts -system.physmem.perBankWrBursts::0 133629 # Per bank write bursts -system.physmem.perBankWrBursts::1 139072 # Per bank write bursts -system.physmem.perBankWrBursts::2 140295 # Per bank write bursts -system.physmem.perBankWrBursts::3 139312 # Per bank write bursts -system.physmem.perBankWrBursts::4 138711 # Per bank write bursts -system.physmem.perBankWrBursts::5 145043 # Per bank write bursts -system.physmem.perBankWrBursts::6 137653 # Per bank write bursts -system.physmem.perBankWrBursts::7 140751 # Per bank write bursts -system.physmem.perBankWrBursts::8 137271 # Per bank write bursts -system.physmem.perBankWrBursts::9 144471 # Per bank write bursts -system.physmem.perBankWrBursts::10 139139 # Per bank write bursts -system.physmem.perBankWrBursts::11 142751 # Per bank write bursts -system.physmem.perBankWrBursts::12 139024 # Per bank write bursts -system.physmem.perBankWrBursts::13 141466 # Per bank write bursts -system.physmem.perBankWrBursts::14 137078 # Per bank write bursts -system.physmem.perBankWrBursts::15 138973 # Per bank write bursts +system.physmem.perBankRdBursts::0 50870 # Per bank write bursts +system.physmem.perBankRdBursts::1 59107 # Per bank write bursts +system.physmem.perBankRdBursts::2 53673 # Per bank write bursts +system.physmem.perBankRdBursts::3 52283 # Per bank write bursts +system.physmem.perBankRdBursts::4 52009 # Per bank write bursts +system.physmem.perBankRdBursts::5 59846 # Per bank write bursts +system.physmem.perBankRdBursts::6 50421 # Per bank write bursts +system.physmem.perBankRdBursts::7 52784 # Per bank write bursts +system.physmem.perBankRdBursts::8 49319 # Per bank write bursts +system.physmem.perBankRdBursts::9 57871 # Per bank write bursts +system.physmem.perBankRdBursts::10 53663 # Per bank write bursts +system.physmem.perBankRdBursts::11 59850 # Per bank write bursts +system.physmem.perBankRdBursts::12 49313 # Per bank write bursts +system.physmem.perBankRdBursts::13 51526 # Per bank write bursts +system.physmem.perBankRdBursts::14 46865 # Per bank write bursts +system.physmem.perBankRdBursts::15 48391 # Per bank write bursts +system.physmem.perBankWrBursts::0 70028 # Per bank write bursts +system.physmem.perBankWrBursts::1 76221 # Per bank write bursts +system.physmem.perBankWrBursts::2 72051 # Per bank write bursts +system.physmem.perBankWrBursts::3 73117 # Per bank write bursts +system.physmem.perBankWrBursts::4 72572 # Per bank write bursts +system.physmem.perBankWrBursts::5 78772 # Per bank write bursts +system.physmem.perBankWrBursts::6 71408 # Per bank write bursts +system.physmem.perBankWrBursts::7 73272 # Per bank write bursts +system.physmem.perBankWrBursts::8 71515 # Per bank write bursts +system.physmem.perBankWrBursts::9 77080 # Per bank write bursts +system.physmem.perBankWrBursts::10 72838 # Per bank write bursts +system.physmem.perBankWrBursts::11 77780 # Per bank write bursts +system.physmem.perBankWrBursts::12 69170 # Per bank write bursts +system.physmem.perBankWrBursts::13 71642 # Per bank write bursts +system.physmem.perBankWrBursts::14 68698 # Per bank write bursts +system.physmem.perBankWrBursts::15 69825 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 512 # Number of times write queue was full causing retry -system.physmem.totGap 51558688241500 # Total gap between requests +system.physmem.numWrRetry 522 # Number of times write queue was full causing retry +system.physmem.totGap 51277958025500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) -system.physmem.readPktSize::4 21272 # Read request sizes (log2) +system.physmem.readPktSize::4 2072 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1907125 # Read request sizes (log2) +system.physmem.readPktSize::6 846431 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2234356 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1137157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 697006 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 62243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 25848 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 474 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 529 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 986 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 614 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 299 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 146 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 96 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 87 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1165716 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 541295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 247060 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15383 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 464 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 939 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 638 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 319 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 154 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 95 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 81 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -160,184 +160,185 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 28528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 36181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 84750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 118181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 127464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 131678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 133520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 138083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 140930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 136900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 140021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 142369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 134210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 132730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 134518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 146577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 128734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 131799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 3385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 2020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1898 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 1664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 1560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 1314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 1520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1159 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 946985 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 281.313381 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 167.848752 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 307.664857 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 373897 39.48% 39.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 237629 25.09% 64.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 90926 9.60% 74.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 53224 5.62% 79.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 39122 4.13% 83.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 27360 2.89% 86.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 21677 2.29% 89.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 17745 1.87% 90.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 85405 9.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 946985 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 117910 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 16.350064 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 51.964300 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 117905 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 117910 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 117910 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.952074 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.420057 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 17.842093 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 113720 96.45% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 1383 1.17% 97.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 426 0.36% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 819 0.69% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 466 0.40% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 257 0.22% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 350 0.30% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 159 0.13% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 44 0.04% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 53 0.04% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 45 0.04% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 26 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 14 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 12 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 23 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 25 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 22 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 13 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 4 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 7 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 7 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 4 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-591 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::624-639 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-655 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::15 18590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 25743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 45741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 55757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 63122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 66457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 68011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 72400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 75195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 71101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 74150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 75214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 67195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 65816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 65315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 67462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 3581 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 2250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 1705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 1442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 1488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1155 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 505782 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 254.816375 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 152.511846 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 294.316020 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 218537 43.21% 43.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 130980 25.90% 69.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 46546 9.20% 78.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 24886 4.92% 83.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 16948 3.35% 86.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10705 2.12% 88.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8138 1.61% 90.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6857 1.36% 91.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 42185 8.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 505782 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 52835 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.045538 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 23.735472 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 52822 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 8 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 3 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1279 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 52835 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 52835 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.068496 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.791739 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 25.919021 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 48708 92.19% 92.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 1351 2.56% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 388 0.73% 95.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 806 1.53% 97.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 454 0.86% 97.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 263 0.50% 98.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 370 0.70% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 158 0.30% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 43 0.08% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 52 0.10% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 56 0.11% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 28 0.05% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 16 0.03% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 21 0.04% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 12 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 27 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 19 0.04% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 15 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 3 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 5 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 4 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 8 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 3 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::592-607 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-623 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::624-639 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 4 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::656-671 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::736-751 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::752-767 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::768-783 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::864-879 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::880-895 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 117910 # Writes before turning the bus around for reads -system.physmem.totQLat 71195410655 # Total ticks spent queuing -system.physmem.totMemAccLat 107342766905 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9639295000 # Total ticks spent in databus transfers -system.physmem.avgQLat 36929.76 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 55679.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.39 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.77 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.77 # Average system write bandwidth in MiByte/s +system.physmem.wrPerTurnAround::880-895 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::912-927 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::992-1007 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 52835 # Writes before turning the bus around for reads +system.physmem.totQLat 32888008041 # Total ticks spent queuing +system.physmem.totMemAccLat 48784089291 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4238955000 # Total ticks spent in databus transfers +system.physmem.avgQLat 38792.54 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 4999.99 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 57542.52 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.06 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.46 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.06 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.46 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.83 # Average write queue length when enqueuing -system.physmem.readRowHits 1556076 # Number of row buffer hits during reads -system.physmem.writeRowHits 1659436 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.72 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.26 # Row buffer hit rate for writes -system.physmem.avgGap 12378029.31 # Average gap between requests -system.physmem.pageHitRate 77.25 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3355628640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1783558920 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6794352600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5817512520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 51361776960.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 51335807970 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 3128372160 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 100703099850 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 75728818080 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 12253311191655 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 12553360719255 # Total energy per rank (pJ) -system.physmem_0.averagePower 243.477109 # Core power per rank (mW) -system.physmem_0.totalIdleTime 51437874182990 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 5229192000 # Time in different power states -system.physmem_0.memoryStateTime::REF 21823720000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 51019823371500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 197210375905 # Time in different power states -system.physmem_0.memoryStateTime::ACT 93762531010 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 220840435585 # Time in different power states -system.physmem_1.actEnergy 3405851400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1810249155 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6970560660 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5847303060 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 52613798640.000015 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 52063882650 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 3186128160 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 104825729160 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 76862967360 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 12250174362465 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 12557802494490 # Total energy per rank (pJ) -system.physmem_1.averagePower 243.563259 # Core power per rank (mW) -system.physmem_1.totalIdleTime 51436124881809 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 5313449750 # Time in different power states -system.physmem_1.memoryStateTime::REF 22355242000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 51006079595250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 200164062707 # Time in different power states -system.physmem_1.memoryStateTime::ACT 94896006191 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 229881270102 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 26.62 # Average write queue length when enqueuing +system.physmem.readRowHits 648292 # Number of row buffer hits during reads +system.physmem.writeRowHits 859704 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.73 # Row buffer hit rate for writes +system.physmem.avgGap 25425342.57 # Average gap between requests +system.physmem.pageHitRate 74.88 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1849802640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 983185830 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3077290020 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3066442020 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 32858039760.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 30159163980 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1958344800 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 66073114650 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 46519620000 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 12231781860420 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 12418342348350 # Total energy per rank (pJ) +system.physmem_0.averagePower 242.176999 # Core power per rank (mW) +system.physmem_0.totalIdleTime 51206686329778 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3544531992 # Time in different power states +system.physmem_0.memoryStateTime::REF 13966174000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 50940644588000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 121144747142 # Time in different power states +system.physmem_0.memoryStateTime::ACT 53762327980 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 144897040886 # Time in different power states +system.physmem_1.actEnergy 1761495120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 936256860 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2975937720 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3020020560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 32012909760.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 29684228010 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1902447840 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 63461801580 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 45299969760 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 12234156504570 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 12415225828860 # Total energy per rank (pJ) +system.physmem_1.averagePower 242.116222 # Core power per rank (mW) +system.physmem_1.totalIdleTime 51207876412176 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3424177242 # Time in different power states +system.physmem_1.memoryStateTime::REF 13608086000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 50950737151500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 117968786503 # Time in different power states +system.physmem_1.memoryStateTime::ACT 53050734582 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 139170474173 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory @@ -354,30 +355,30 @@ system.realview.nvmem.bw_inst_read::total 7 # I system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 291746368 # Number of BP lookups -system.cpu.branchPred.condPredicted 199670043 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 13704274 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 209695065 # Number of BTB lookups -system.cpu.branchPred.BTBHits 131330914 # Number of BTB hits +system.cpu.branchPred.lookups 214792288 # Number of BP lookups +system.cpu.branchPred.condPredicted 137846282 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12464803 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 146135265 # Number of BTB lookups +system.cpu.branchPred.BTBHits 84448125 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.629473 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 37689025 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 403296 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 8150983 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 6071547 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2079436 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 799941 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 57.787643 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31594768 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 349324 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 6874034 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 4883721 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1990313 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 771971 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -407,93 +408,87 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 1432753 # Table walker walks requested -system.cpu.dtb.walker.walksLong 1432753 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 31582 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 277767 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 672727 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 760026 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 2835.541153 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 21869.031891 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-65535 752912 99.06% 99.06% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-131071 4648 0.61% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-196607 979 0.13% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-262143 465 0.06% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-327679 329 0.04% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-393215 37 0.00% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-458751 227 0.03% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::458752-524287 31 0.00% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::524288-589823 15 0.00% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::589824-655359 373 0.05% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::655360-720895 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 760026 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 802864 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 26261.811465 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 21447.525498 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 20174.954942 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 783898 97.64% 97.64% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 15255 1.90% 99.54% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 1830 0.23% 99.77% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 1111 0.14% 99.90% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 417 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 138 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 67 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 44 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 12 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 88 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 802864 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 1071344974520 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.740930 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.520683 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 1067157103520 99.61% 99.61% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 2648963000 0.25% 99.86% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 765456500 0.07% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 299226500 0.03% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 205947000 0.02% 99.97% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 124770000 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 49360500 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 91134000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 2962000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::18-19 28500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::20-21 23000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 1071344974520 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 277768 89.79% 89.79% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 31582 10.21% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 309350 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1432753 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 970467 # Table walker walks requested +system.cpu.dtb.walker.walksLong 970467 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 18061 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 162102 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 433748 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 536719 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 2148.778970 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 14488.438649 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-65535 533045 99.32% 99.32% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-131071 2702 0.50% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-196607 468 0.09% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-262143 229 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-327679 124 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-393215 18 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-458751 94 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::458752-524287 8 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::524288-589823 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::589824-655359 22 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 536719 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 489559 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 21856.142978 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 16984.908569 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 19510.602702 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 478829 97.81% 97.81% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 9216 1.88% 99.69% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 680 0.14% 99.83% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 491 0.10% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 167 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 30 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 18 0.00% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 13 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 15 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 87 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 13 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 489559 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 687539152416 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.766147 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.508794 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 685391448916 99.69% 99.69% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 1144327500 0.17% 99.85% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 477284500 0.07% 99.92% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 191925000 0.03% 99.95% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 139963500 0.02% 99.97% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 102241500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 33074500 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 56365000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 2522000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 687539152416 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 162103 89.98% 89.98% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 18061 10.02% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 180164 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 970467 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1432753 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 309350 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 970467 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 180164 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 309350 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1742103 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 180164 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1150631 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 218702786 # DTB read hits -system.cpu.dtb.read_misses 1008685 # DTB read misses -system.cpu.dtb.write_hits 193509885 # DTB write hits -system.cpu.dtb.write_misses 424068 # DTB write misses -system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed +system.cpu.dtb.read_hits 174485449 # DTB read hits +system.cpu.dtb.read_misses 696020 # DTB read misses +system.cpu.dtb.write_hits 152010399 # DTB write hits +system.cpu.dtb.write_misses 274447 # DTB write misses +system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 63704 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 88843 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 16314 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 41510 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1047 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 74778 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 103 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 10363 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 85947 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 219711471 # DTB read accesses -system.cpu.dtb.write_accesses 193933953 # DTB write accesses +system.cpu.dtb.perms_faults 69607 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 175181469 # DTB read accesses +system.cpu.dtb.write_accesses 152284846 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 412212671 # DTB hits -system.cpu.dtb.misses 1432753 # DTB misses -system.cpu.dtb.accesses 413645424 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 326495848 # DTB hits +system.cpu.dtb.misses 970467 # DTB misses +system.cpu.dtb.accesses 327466315 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -523,1117 +518,1115 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 178667 # Table walker walks requested -system.cpu.itb.walker.walksLong 178667 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1505 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 129431 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 20285 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 158382 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1812.216666 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 18363.278107 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-65535 157121 99.20% 99.20% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-131071 1064 0.67% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-196607 45 0.03% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-262143 30 0.02% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-327679 12 0.01% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::327680-393215 8 0.01% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::393216-458751 4 0.00% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::458752-524287 1 0.00% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::524288-589823 38 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::589824-655359 58 0.04% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 158382 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 151221 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 29741.047870 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 23638.717531 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 30785.807578 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 145088 95.94% 95.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 5051 3.34% 99.28% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 405 0.27% 99.55% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 372 0.25% 99.80% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 84 0.06% 99.85% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 62 0.04% 99.89% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 13 0.01% 99.90% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 11 0.01% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 6 0.00% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 89 0.06% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::655360-720895 6 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::720896-786431 31 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 151221 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 912431133568 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.946195 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.225953 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 49158537652 5.39% 5.39% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 863207621416 94.61% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 64327000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 645500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 912431133568 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 129431 98.85% 98.85% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1505 1.15% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 130936 # Table walker page sizes translated +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 166329 # Table walker walks requested +system.cpu.itb.walker.walksLong 166329 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1543 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 121824 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 18039 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 148290 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1030.507789 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 10121.197556 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-65535 147791 99.66% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-131071 435 0.29% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-196607 25 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-262143 11 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-327679 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::327680-393215 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::458752-524287 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::524288-589823 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::589824-655359 11 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 148290 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 141406 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 26889.721794 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 22183.567838 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 21940.142141 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 138369 97.85% 97.85% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 2580 1.82% 99.68% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 191 0.14% 99.81% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 150 0.11% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 40 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 18 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 2 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 49 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 141406 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 580161918016 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.951845 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.214419 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 27974300560 4.82% 4.82% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 552153156456 95.17% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 33290000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 609500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 49000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::5 512500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 580161918016 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 121824 98.75% 98.75% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1543 1.25% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 123367 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 178667 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 178667 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 166329 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 166329 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 130936 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 130936 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 309603 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 465155459 # ITB inst hits -system.cpu.itb.inst_misses 178667 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123367 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 123367 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 289696 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 333977355 # ITB inst hits +system.cpu.itb.inst_misses 166329 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 63704 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1209 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 62700 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 41510 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1047 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 54464 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 443616 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 373131 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 465334126 # ITB inst accesses -system.cpu.itb.hits 465155459 # DTB hits -system.cpu.itb.misses 178667 # DTB misses -system.cpu.itb.accesses 465334126 # DTB accesses -system.cpu.numPwrStateTransitions 34326 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 17163 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 2940291030.619589 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 58535247231.170448 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 7840 45.68% 45.68% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9287 54.11% 99.79% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 334143684 # ITB inst accesses +system.cpu.itb.hits 333977355 # DTB hits +system.cpu.itb.misses 166329 # DTB misses +system.cpu.itb.accesses 334143684 # DTB accesses +system.cpu.numPwrStateTransitions 32546 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 16273 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3107516335.044798 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 60196725189.485252 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 6948 42.70% 42.70% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9289 57.08% 99.78% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.83% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::9.5e+11-1e+12 1 0.01% 99.90% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::overflows 18 0.10% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 17163 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 1094474667476 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50464214958524 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2188958665 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::total 16273 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 709346089816 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50568613320184 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1418701600 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 793327228 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1301291266 # Number of instructions fetch has processed -system.cpu.fetch.Branches 291746368 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 175091486 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1303318637 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29494258 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 4691335 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 27171 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11697076 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1210879 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 1191 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 464693718 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6899661 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 52634 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 2129020646 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.716284 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.134063 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 626970761 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 964955706 # Number of instructions fetch has processed +system.cpu.fetch.Branches 214792288 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 120926614 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 712354427 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26627776 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3832226 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 25955 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9044924 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1035738 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 1059 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 333569052 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6336680 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 48713 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 1366578978 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.835386 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.187527 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1402178691 65.86% 65.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 283295913 13.31% 79.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 88951632 4.18% 83.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 354594410 16.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 828034594 60.59% 60.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 202016384 14.78% 75.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 69979562 5.12% 80.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 266548438 19.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 2129020646 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.133281 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.594480 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 614901243 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 887926164 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542267168 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 73189541 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10736530 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 41417664 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4068147 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1415615504 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 33076716 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10736530 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 677683388 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 94369025 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 569420569 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 556850066 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 219961068 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1391316215 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 8139294 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7433415 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 989914 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1107412 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 140152556 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 22881 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1341380585 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2214711658 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1650667847 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1431319 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1262462841 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 78917741 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 44085987 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 39608884 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 160777326 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 223759172 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 197950271 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12848262 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11112686 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1338031616 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 44396038 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1368016868 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4222413 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 73918251 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 42115616 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 367601 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 2129020646 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.642557 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.913774 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1366578978 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.151401 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.680168 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 523831535 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 358407215 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 444986242 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 29823356 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9530630 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 82997397 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 3840205 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1051662188 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29872784 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9530630 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 559062030 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 58275029 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 221284587 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 439543391 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 78883311 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1030946151 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 7084405 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 5220432 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 401053 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 689601 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 52909282 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 20659 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 944726342 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1460373617 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1214391439 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1466073 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 877604087 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 67122252 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11621737 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 7877357 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 58456344 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 178961087 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 155538156 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 10194150 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9195511 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1010975595 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 11936880 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1010573430 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3406540 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 62033200 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 34713553 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 312805 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1366578978 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.739491 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.966076 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 1277602195 60.01% 60.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 452152764 21.24% 81.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 292326493 13.73% 94.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 96574735 4.54% 99.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10335382 0.49% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 29077 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 766524619 56.09% 56.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 278054062 20.35% 76.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 240507320 17.60% 94.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 74487645 5.45% 99.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6984867 0.51% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20465 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 2129020646 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1366578978 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 73998347 33.81% 33.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 90252 0.04% 33.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26750 0.01% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 451 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 58933248 26.93% 60.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 85092406 38.88% 99.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 64953 0.03% 99.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 641116 0.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 59327643 34.80% 34.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 97860 0.06% 34.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26629 0.02% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 606 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 45774518 26.85% 61.72% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 64550245 37.86% 99.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 65013 0.04% 99.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 650262 0.38% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 41 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 945166591 69.09% 69.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2943445 0.22% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 129819 0.01% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 9 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 24 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 112220 0.01% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 223636421 16.35% 85.67% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 195247662 14.27% 99.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 119006 0.01% 99.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 661615 0.05% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 675222587 66.82% 66.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2579661 0.26% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 123552 0.01% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 381 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 24 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 118042 0.01% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 178525210 17.67% 84.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 153211297 15.16% 99.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 117761 0.01% 99.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 674889 0.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1368016868 # Type of FU issued -system.cpu.iq.rate 0.624962 # Inst issue rate -system.cpu.iq.fu_busy_cnt 218847523 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.159974 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5085629992 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1455613237 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1345805572 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2494325 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 915085 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 886623 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1585264941 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1599409 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5699315 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1010573430 # Type of FU issued +system.cpu.iq.rate 0.712323 # Inst issue rate +system.cpu.iq.fu_busy_cnt 170492776 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.168709 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3559085350 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1084154908 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 991977756 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2539803 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 933979 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 905255 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1179439202 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1626993 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 4435926 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 17397321 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 21752 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 184120 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8002822 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14385160 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 15174 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 144472 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6174251 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3610863 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2045833 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2629445 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1524875 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10736530 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13380632 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5317474 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1382714005 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 9530630 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 7210038 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 4323845 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1023153770 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 223759172 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 197950271 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 39068255 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 183844 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4942045 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 184120 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4054774 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6111734 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10166508 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1354334153 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 218708027 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 12279784 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 178961087 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 155538156 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7437223 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 69213 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4169498 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 144472 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3542728 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5585702 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 9128430 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 998939859 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 174475303 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10677060 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 286351 # number of nop insts executed -system.cpu.iew.exec_refs 412227919 # number of memory reference insts executed -system.cpu.iew.exec_branches 257147927 # Number of branches executed -system.cpu.iew.exec_stores 193519892 # Number of stores executed -system.cpu.iew.exec_rate 0.618712 # Inst execution rate -system.cpu.iew.wb_sent 1347736728 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1346692195 # cumulative count of insts written-back -system.cpu.iew.wb_producers 575598964 # num instructions producing a value -system.cpu.iew.wb_consumers 947631330 # num instructions consuming a value -system.cpu.iew.wb_rate 0.615220 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.607408 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 63004798 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 44028437 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9693675 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 2114795220 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.618740 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.263829 # Number of insts commited each cycle +system.cpu.iew.exec_nop 241295 # number of nop insts executed +system.cpu.iew.exec_refs 326482764 # number of memory reference insts executed +system.cpu.iew.exec_branches 185483896 # Number of branches executed +system.cpu.iew.exec_stores 152007461 # Number of stores executed +system.cpu.iew.exec_rate 0.704123 # Inst execution rate +system.cpu.iew.wb_sent 993723823 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 992883011 # cumulative count of insts written-back +system.cpu.iew.wb_producers 420701773 # num instructions producing a value +system.cpu.iew.wb_consumers 671731184 # num instructions consuming a value +system.cpu.iew.wb_rate 0.699853 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.626295 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 52581924 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 11624075 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 8681545 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1354317292 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.709493 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.365584 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1434472892 67.83% 67.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 397205670 18.78% 86.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 150685224 7.13% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 44578118 2.11% 95.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 36046556 1.70% 97.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 18010679 0.85% 98.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 11270632 0.53% 98.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5868076 0.28% 99.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 16657373 0.79% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 893350952 65.96% 65.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 231145639 17.07% 83.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 123165028 9.09% 92.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 37514552 2.77% 94.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29252763 2.16% 97.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14325561 1.06% 98.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8938173 0.66% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4404967 0.33% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 12219657 0.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 2114795220 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1113248331 # Number of instructions committed -system.cpu.commit.committedOps 1308509399 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1354317292 # Number of insts commited each cycle +system.cpu.commit.committedInsts 807652759 # Number of instructions committed +system.cpu.commit.committedOps 960879271 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 396309299 # Number of memory references committed -system.cpu.commit.loads 206361850 # Number of loads committed -system.cpu.commit.membars 9184659 # Number of memory barriers committed -system.cpu.commit.branches 248844974 # Number of branches committed -system.cpu.commit.fp_insts 874713 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1195788175 # Number of committed integer instructions. -system.cpu.commit.function_calls 31054705 # Number of function calls committed. +system.cpu.commit.refs 313939831 # Number of memory references committed +system.cpu.commit.loads 164575926 # Number of loads committed +system.cpu.commit.membars 7185354 # Number of memory barriers committed +system.cpu.commit.branches 178524482 # Number of branches committed +system.cpu.commit.fp_insts 893967 # Number of committed floating point instructions. +system.cpu.commit.int_insts 893684330 # Number of committed integer instructions. +system.cpu.commit.function_calls 25910780 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 909436322 69.50% 69.50% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2554044 0.20% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 103998 0.01% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 8 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 13 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 21 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 105694 0.01% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 206248879 15.76% 85.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 189291443 14.47% 99.94% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 112971 0.01% 99.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 656006 0.05% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 644536442 67.08% 67.08% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2193608 0.23% 67.31% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 98465 0.01% 67.32% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 8 0.00% 67.32% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 13 0.00% 67.32% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 21 0.00% 67.32% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.32% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 67.32% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.32% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 110883 0.01% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.33% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 164464107 17.12% 84.44% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 148692682 15.47% 99.92% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 111819 0.01% 99.93% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 671223 0.07% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1308509399 # Class of committed instruction -system.cpu.commit.bw_lim_events 16657373 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3460150362 # The number of ROB reads -system.cpu.rob.rob_writes 2757143126 # The number of ROB writes -system.cpu.timesIdled 9093879 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59938019 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 100928420629 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 1113248331 # Number of Instructions Simulated -system.cpu.committedOps 1308509399 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.966281 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.966281 # CPI: Total CPI of All Threads -system.cpu.ipc 0.508574 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.508574 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1608691208 # number of integer regfile reads -system.cpu.int_regfile_writes 947917634 # number of integer regfile writes -system.cpu.fp_regfile_reads 1422673 # number of floating regfile reads -system.cpu.fp_regfile_writes 763952 # number of floating regfile writes -system.cpu.cc_regfile_reads 314581614 # number of cc regfile reads -system.cpu.cc_regfile_writes 315450766 # number of cc regfile writes -system.cpu.misc_regfile_reads 3476012517 # number of misc regfile reads -system.cpu.misc_regfile_writes 44950556 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 13775006 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.982219 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 363107662 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 13775518 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 26.358912 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1801582500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.982219 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999965 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy +system.cpu.commit.op_class_0::total 960879271 # Class of committed instruction +system.cpu.commit.bw_lim_events 12219657 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2347791153 # The number of ROB reads +system.cpu.rob.rob_writes 2039089805 # The number of ROB writes +system.cpu.timesIdled 8233460 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 52122622 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 101137217350 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 807652759 # Number of Instructions Simulated +system.cpu.committedOps 960879271 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.756574 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.756574 # CPI: Total CPI of All Threads +system.cpu.ipc 0.569290 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.569290 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1178021092 # number of integer regfile reads +system.cpu.int_regfile_writes 719548586 # number of integer regfile writes +system.cpu.fp_regfile_reads 1455011 # number of floating regfile reads +system.cpu.fp_regfile_writes 777624 # number of floating regfile writes +system.cpu.cc_regfile_reads 183031164 # number of cc regfile reads +system.cpu.cc_regfile_writes 183683629 # number of cc regfile writes +system.cpu.misc_regfile_reads 2245464732 # number of misc regfile reads +system.cpu.misc_regfile_writes 11742996 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 10097387 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.998168 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 291447803 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 10097899 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 28.862222 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 194046500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.998168 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 399 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1608531103 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1608531103 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 187963659 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 187963659 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 164128124 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 164128124 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 464529 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 464529 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 334911 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 334911 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4841304 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4841304 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5331661 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5331661 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 352426694 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 352426694 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 352891223 # number of overall hits -system.cpu.dcache.overall_hits::total 352891223 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12866276 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12866276 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 18869425 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 18869425 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 2066021 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 2066021 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1270837 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1270837 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 552138 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 552138 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 8 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 33006538 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 33006538 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 35072559 # number of overall misses -system.cpu.dcache.overall_misses::total 35072559 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 225016613000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 225016613000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1113555465610 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1113555465610 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 30066239407 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 30066239407 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 9389478000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 9389478000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 268500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 268500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1368638318017 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1368638318017 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1368638318017 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1368638318017 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 200829935 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 200829935 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 182997549 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 182997549 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2530550 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2530550 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1605748 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1605748 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5393442 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5393442 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5331669 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5331669 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 385433232 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 385433232 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 387963782 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 387963782 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064066 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.064066 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.103113 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.103113 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.816432 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.816432 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791430 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.791430 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102372 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.102372 # miss rate for LoadLockedReq accesses +system.cpu.dcache.tags.tag_accesses 1275104379 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1275104379 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 151424979 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 151424979 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 131950159 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 131950159 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 388682 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 388682 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 326177 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 326177 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3459521 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3459521 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3868336 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3868336 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 283701315 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 283701315 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 284089997 # number of overall hits +system.cpu.dcache.overall_hits::total 284089997 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9913119 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9913119 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 11970495 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 11970495 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1253745 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1253745 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1236891 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1236891 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 459501 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 459501 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 9 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 23120505 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 23120505 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 24374250 # number of overall misses +system.cpu.dcache.overall_misses::total 24374250 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 163455721000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 163455721000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 418494791659 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 418494791659 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 27820801905 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 27820801905 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6946845500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 6946845500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 284500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 284500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 609771314564 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 609771314564 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 609771314564 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 609771314564 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 161338098 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 161338098 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 143920654 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 143920654 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1642427 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1642427 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1563068 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1563068 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3919022 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3919022 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3868345 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3868345 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 306821820 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 306821820 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 308464247 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 308464247 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061443 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.061443 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083174 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.083174 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.763349 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.763349 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791323 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.791323 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.117249 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.117249 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.085635 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.085635 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.090402 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.090402 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17488.868807 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17488.868807 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59013.746609 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59013.746609 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23658.611928 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23658.611928 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17005.672495 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17005.672495 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 33562.500000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 33562.500000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41465.673195 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41465.673195 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39023.052695 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39023.052695 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29226576 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.075355 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.075355 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.079018 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.079018 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16488.828693 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16488.828693 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34960.525163 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34960.525163 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 22492.525134 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 22492.525134 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15118.238045 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15118.238045 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 31611.111111 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 31611.111111 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26373.615739 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26373.615739 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25017.028814 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25017.028814 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 19489299 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2109542 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1643530 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.854465 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.858195 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 10412623 # number of writebacks -system.cpu.dcache.writebacks::total 10412623 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5753869 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5753869 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15770096 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 15770096 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6914 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 6914 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 268040 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 268040 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 21530879 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 21530879 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 21530879 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 21530879 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7112407 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7112407 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3099329 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3099329 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2059217 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 2059217 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263923 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1263923 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 284098 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 284098 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 8 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 11475659 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 11475659 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 13534876 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 13534876 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 33692 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 67395 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 119879387000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 119879387000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 164321917838 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 164321917838 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 34890815500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 34890815500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 28496186907 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 28496186907 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4243086000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4243086000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 260500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 260500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 312697491745 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 312697491745 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 347588307245 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 347588307245 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6225622500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6225622500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6225622500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6225622500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035415 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035415 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016936 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016936 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.813743 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.813743 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787124 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787124 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.052675 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.052675 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.writebacks::writebacks 7764980 # number of writebacks +system.cpu.dcache.writebacks::total 7764980 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4590646 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4590646 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9875948 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9875948 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6846 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 6846 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 225673 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 225673 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 14473440 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 14473440 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 14473440 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 14473440 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5322473 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5322473 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2094547 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2094547 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1246940 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1246940 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1230045 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1230045 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 233828 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 233828 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 9 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 9 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 8647065 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 8647065 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9894005 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9894005 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33590 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 33590 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33609 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 33609 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67199 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 67199 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84299556500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 84299556500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 70150658430 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 70150658430 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 22795031000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 22795031000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 26312863405 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 26312863405 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3251889000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3251889000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 275500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 275500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 180763078335 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 180763078335 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 203558109335 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 203558109335 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6204454000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6204454000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6204454000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6204454000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032990 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032990 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014553 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014553 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.759206 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.759206 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786943 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786943 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.059665 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.059665 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029773 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029773 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034887 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034887 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16854.967242 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16854.967242 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53018.546220 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53018.546220 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16943.729340 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16943.729340 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22545.825107 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22545.825107 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14935.289935 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14935.289935 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 32562.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 32562.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27248.761204 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27248.761204 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25680.937693 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25680.937693 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184780.437493 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184780.437493 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92375.139105 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92375.139105 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 16945634 # number of replacements -system.cpu.icache.tags.tagsinuse 511.953469 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 446936468 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 16946146 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26.373930 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 13767479500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.953469 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028183 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028183 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032075 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032075 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15838.418814 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15838.418814 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33492.043115 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33492.043115 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18280.776140 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18280.776140 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 21391.789248 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 21391.789248 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13907.183913 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13907.183913 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 30611.111111 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 30611.111111 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20904.558753 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20904.558753 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20573.883815 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20573.883815 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184711.342662 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184711.342662 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92329.558476 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92329.558476 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 15304958 # number of replacements +system.cpu.icache.tags.tagsinuse 511.969276 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 317502771 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15305470 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 20.744399 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 12156673500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.969276 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999940 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999940 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 481618789 # Number of tag accesses -system.cpu.icache.tags.data_accesses 481618789 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 446936468 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 446936468 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 446936468 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 446936468 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 446936468 # number of overall hits -system.cpu.icache.overall_hits::total 446936468 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17735952 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17735952 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17735952 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17735952 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17735952 # number of overall misses -system.cpu.icache.overall_misses::total 17735952 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 237635395867 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 237635395867 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 237635395867 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 237635395867 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 237635395867 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 237635395867 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 464672420 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 464672420 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 464672420 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 464672420 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 464672420 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 464672420 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038169 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.038169 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.038169 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.038169 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.038169 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.038169 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13398.513701 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13398.513701 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13398.513701 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13398.513701 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13398.513701 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13398.513701 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 21075 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 348872656 # Number of tag accesses +system.cpu.icache.tags.data_accesses 348872656 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 317502771 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 317502771 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 317502771 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 317502771 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 317502771 # number of overall hits +system.cpu.icache.overall_hits::total 317502771 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 16064183 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 16064183 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 16064183 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 16064183 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 16064183 # number of overall misses +system.cpu.icache.overall_misses::total 16064183 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 215226774877 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 215226774877 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 215226774877 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 215226774877 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 215226774877 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 215226774877 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 333566954 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 333566954 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 333566954 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 333566954 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 333566954 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 333566954 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.048159 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.048159 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.048159 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.048159 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.048159 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.048159 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13397.928477 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13397.928477 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13397.928477 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13397.928477 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13397.928477 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13397.928477 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 20885 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1467 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1543 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 14.366053 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 13.535321 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 16945634 # number of writebacks -system.cpu.icache.writebacks::total 16945634 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 789581 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 789581 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 789581 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 789581 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 789581 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 789581 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16946371 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16946371 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16946371 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16946371 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16946371 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16946371 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable -system.cpu.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable -system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 213535123378 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 213535123378 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 213535123378 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 213535123378 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 213535123378 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 213535123378 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1752662500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1752662500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1752662500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 1752662500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036470 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036470 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036470 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.036470 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036470 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.036470 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12600.640183 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12600.640183 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12600.640183 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12600.640183 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12600.640183 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12600.640183 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82307.809712 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82307.809712 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82307.809712 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82307.809712 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 2400192 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65402.662910 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 59310777 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2462586 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 24.084754 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2677803000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9273.019739 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 380.440424 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 420.878818 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6709.693607 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48618.630322 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.141495 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005805 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006422 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.102382 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.741861 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997965 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 239 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62155 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 239 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 998 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5581 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55200 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003647 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.948410 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 508162919 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 508162919 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1310607 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 311860 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1622467 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 10412623 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 10412623 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 16942916 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 16942916 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 39365 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 39365 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 5 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1729760 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1729760 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16850415 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 16850415 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 8995594 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 8995594 # number of ReadSharedReq hits -system.cpu.l2cache.InvalidateReq_hits::cpu.data 670573 # number of InvalidateReq hits -system.cpu.l2cache.InvalidateReq_hits::total 670573 # number of InvalidateReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 1310607 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 311860 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 16850415 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 10725354 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 29198236 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 1310607 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 311860 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 16850415 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 10725354 # number of overall hits -system.cpu.l2cache.overall_hits::total 29198236 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 10751 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 8953 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 19704 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 4081 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 4081 # number of UpgradeReq misses +system.cpu.icache.writebacks::writebacks 15304958 # number of writebacks +system.cpu.icache.writebacks::total 15304958 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 758480 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 758480 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 758480 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 758480 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 758480 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 758480 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15305703 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15305703 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15305703 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15305703 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15305703 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15305703 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 2094 # number of ReadReq MSHR uncacheable +system.cpu.icache.ReadReq_mshr_uncacheable::total 2094 # number of ReadReq MSHR uncacheable +system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 2094 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::total 2094 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 193058693887 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 193058693887 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 193058693887 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 193058693887 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 193058693887 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 193058693887 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 174071500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 174071500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 174071500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 174071500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.045885 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.045885 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.045885 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.045885 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.045885 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.045885 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12613.513661 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12613.513661 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12613.513661 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12613.513661 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12613.513661 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12613.513661 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 83128.701051 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 83128.701051 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 83128.701051 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 83128.701051 # average overall mshr uncacheable latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 1248689 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65406.058647 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 49295549 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1311963 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 37.573887 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 1068241000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 9667.637617 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 499.308772 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 609.219516 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6963.202905 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 47666.689838 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.147516 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.007619 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.009296 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106250 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.727336 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998017 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 512 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 62762 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 512 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1132 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5479 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55729 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.007812 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.957672 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 417429422 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 417429422 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 796619 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 283100 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1079719 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 7764980 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 7764980 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 15302294 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 15302294 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 25817 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 25817 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 6 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 6 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1591016 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1591016 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15218653 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 15218653 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6530102 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 6530102 # number of ReadSharedReq hits +system.cpu.l2cache.InvalidateReq_hits::cpu.data 728891 # number of InvalidateReq hits +system.cpu.l2cache.InvalidateReq_hits::total 728891 # number of InvalidateReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 796619 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 283100 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 15218653 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 8121118 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 24419490 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 796619 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 283100 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 15218653 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 8121118 # number of overall hits +system.cpu.l2cache.overall_hits::total 24419490 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3956 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3665 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 7621 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 4094 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 4094 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1342610 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1342610 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 95730 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 95730 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 443644 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 443644 # number of ReadSharedReq misses -system.cpu.l2cache.InvalidateReq_misses::cpu.data 593350 # number of InvalidateReq misses -system.cpu.l2cache.InvalidateReq_misses::total 593350 # number of InvalidateReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 10751 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 8953 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 95730 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1786254 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1901688 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 10751 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 8953 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 95730 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1786254 # number of overall misses -system.cpu.l2cache.overall_misses::total 1901688 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1481609000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 989051000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2470660000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 73641000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 73641000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_misses::cpu.data 478353 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 478353 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 86839 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 86839 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 268407 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 268407 # number of ReadSharedReq misses +system.cpu.l2cache.InvalidateReq_misses::cpu.data 501154 # number of InvalidateReq misses +system.cpu.l2cache.InvalidateReq_misses::total 501154 # number of InvalidateReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 3956 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 3665 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 86839 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 746760 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 841220 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 3956 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 3665 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 86839 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 746760 # number of overall misses +system.cpu.l2cache.overall_misses::total 841220 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 431772500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 382599000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 814371500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 72848000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 72848000 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162500 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 140820985000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 140820985000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 10474446000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 10474446000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49360603500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 49360603500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1481609000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 989051000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 10474446000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 190181588500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 203126694500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1481609000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 989051000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 10474446000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 190181588500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 203126694500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 1321358 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 320813 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1642171 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 10412623 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 10412623 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 16942916 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 16942916 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43446 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 43446 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 8 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 8 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 3072370 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 3072370 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 16946145 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 16946145 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 9439238 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 9439238 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1263923 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::total 1263923 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 1321358 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 320813 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 16946145 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 12511608 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 31099924 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 1321358 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 320813 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 16946145 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 12511608 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 31099924 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.008136 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.027907 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.011999 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.093933 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.093933 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.375000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.375000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436995 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.436995 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005649 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005649 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.047000 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.047000 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.469451 # miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::total 0.469451 # miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.008136 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.027907 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005649 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.142768 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.061148 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.008136 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.027907 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005649 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.142768 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.061148 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137811.273370 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 110471.462080 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 125388.753553 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 18044.841951 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 18044.841951 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 49637800000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 49637800000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9658072000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 9658072000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30942623000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 30942623000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 431772500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 382599000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9658072000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 80580423000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 91052866500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 431772500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 382599000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9658072000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 80580423000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 91052866500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 800575 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 286765 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1087340 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 7764980 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 7764980 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 15302294 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 15302294 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 29911 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 29911 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 9 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 9 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2069369 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2069369 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15305492 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 15305492 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6798509 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 6798509 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1230045 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::total 1230045 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 800575 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 286765 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 15305492 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 8867878 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 25260710 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 800575 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 286765 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15305492 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 8867878 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 25260710 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.004941 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.012780 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.007009 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.136873 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.136873 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.333333 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.333333 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.231159 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.231159 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005674 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005674 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.039480 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.039480 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.407427 # miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.407427 # miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.004941 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.012780 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005674 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.084210 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.033302 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.004941 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.012780 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005674 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.084210 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.033302 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 109143.705763 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 104392.633015 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 106858.876788 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17793.844651 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17793.844651 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 54166.666667 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 54166.666667 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104885.994444 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104885.994444 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 109416.546537 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 109416.546537 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 111261.740269 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 111261.740269 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137811.273370 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 110471.462080 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 109416.546537 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106469.510215 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 106813.890870 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137811.273370 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 110471.462080 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 109416.546537 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106469.510215 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 106813.890870 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 103768.137756 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 103768.137756 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 111218.139315 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 111218.139315 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115282.474004 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115282.474004 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 109143.705763 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 104392.633015 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111218.139315 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 107906.721035 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 108239.065286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 109143.705763 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 104392.633015 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111218.139315 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 107906.721035 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 108239.065286 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 2127726 # number of writebacks -system.cpu.l2cache.writebacks::total 2127726 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.itb.walker 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 1059086 # number of writebacks +system.cpu.l2cache.writebacks::total 1059086 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.itb.walker 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.itb.walker 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.itb.walker 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 25 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.itb.walker 4 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.itb.walker 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 25 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10751 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 8949 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 19700 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 22 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3956 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3664 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 7620 # number of ReadReq MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4081 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 4081 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4094 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 4094 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1342610 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1342610 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 95730 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 95730 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 443623 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 443623 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 593350 # number of InvalidateReq MSHR misses -system.cpu.l2cache.InvalidateReq_mshr_misses::total 593350 # number of InvalidateReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10751 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 8949 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 95730 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1786233 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1901663 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10751 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 8949 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 95730 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1786233 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1901663 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54986 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88689 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1374099000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 899358000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2273457000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 77835000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 77835000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 478353 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 478353 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 86839 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 86839 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 268386 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 268386 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 501154 # number of InvalidateReq MSHR misses +system.cpu.l2cache.InvalidateReq_mshr_misses::total 501154 # number of InvalidateReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3956 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3664 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 86839 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 746739 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 841198 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3956 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3664 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 86839 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 746739 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 841198 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 2094 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33590 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 35684 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33609 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33609 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 2094 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67199 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 69293 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 392212500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 345880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 738092500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 78102500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 78102500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 163000 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 163000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 127394865041 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 127394865041 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9517134048 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9517134048 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 44922827064 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 44922827064 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 12274426752 # number of InvalidateReq MSHR miss cycles -system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 12274426752 # number of InvalidateReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1374099000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 899358000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9517134048 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 172317692105 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 184108283153 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1374099000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 899358000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9517134048 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 172317692105 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 184108283153 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1486487500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5804330500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7290818000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1486487500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5804330500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 7290818000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.008136 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.027895 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011996 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44854250540 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44854250540 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8789667055 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8789667055 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28257377566 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28257377566 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 10480376502 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 10480376502 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 392212500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 345880000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8789667055 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 73111628106 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 82639387661 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 392212500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 345880000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8789667055 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 73111628106 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 82639387661 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 147896500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5784421000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5932317500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 147896500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5784421000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 5932317500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004941 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.012777 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.007008 # mshr miss rate for ReadReq accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.093933 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.093933 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.375000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.375000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436995 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436995 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005649 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005649 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.046998 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.046998 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.469451 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.469451 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008136 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.027895 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005649 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.142766 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.061147 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008136 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.027895 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005649 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.142766 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.061147 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127811.273370 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 100498.156219 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 115403.908629 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19072.531242 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19072.531242 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.136873 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.136873 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.231159 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.231159 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005674 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005674 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.039477 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.039477 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.407427 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.407427 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004941 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.012777 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005674 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.084207 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.033301 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004941 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.012777 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005674 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.084207 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.033301 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 99143.705763 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 94399.563319 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 96862.532808 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19077.308256 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19077.308256 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 54333.333333 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 54333.333333 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94885.979578 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94885.979578 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99416.421686 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99416.421686 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 101263.521197 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 101263.521197 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20686.655013 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20686.655013 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127811.273370 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 100498.156219 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99416.421686 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96469.885007 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 96814.358355 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127811.273370 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 100498.156219 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99416.421686 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96469.885007 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 96814.358355 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69807.809712 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172276.222842 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132594.078493 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69807.809712 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86124.052229 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 82206.564512 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 62406736 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 31684635 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4771 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2157 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2157 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93768.097075 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93768.097075 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101217.967215 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101217.967215 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105286.332245 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105286.332245 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20912.486984 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20912.486984 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 99143.705763 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 94399.563319 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101217.967215 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 97907.874245 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 98240.114291 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 99143.705763 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 94399.563319 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101217.967215 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 97907.874245 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 98240.114291 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 70628.701051 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172206.638881 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166245.866495 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 70628.701051 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86078.974389 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 85612.074813 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 51553426 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 26149596 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7713 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1993 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1993 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 2262463 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 28648866 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33703 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33703 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 12540349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 16945634 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 3634849 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43449 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43457 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3072370 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3072370 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 16946371 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 9441630 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1296845 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1263929 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50880736 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41548571 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 789343 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3060305 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 96278955 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2169414432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1467392114 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2566504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10570864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 3649943914 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 3001846 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 140762320 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 35497041 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.026133 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.159532 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1662998 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23767979 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33609 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33609 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 8824066 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 15304958 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2522010 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 29914 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 29923 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2069369 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2069369 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15305703 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6801111 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1260813 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1230062 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45920340 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30488261 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 721887 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1992767 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 79123255 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1959102240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1064742138 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2294120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6404600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 3032543098 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1823037 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 72164080 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 28412224 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.025596 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.157926 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 34569387 97.39% 97.39% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 927654 2.61% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 27684996 97.44% 97.44% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 727226 2.56% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 2 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 35497041 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 59266206483 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 28412224 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 49353009980 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1503389 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1469889 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 25451406259 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 22969214259 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 19476952327 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13985386089 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 468902194 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 435462274 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1739672503 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1192643074 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40306 # Transaction distribution -system.iobus.trans_dist::ReadResp 40306 # Transaction distribution -system.iobus.trans_dist::WriteReq 136571 # Transaction distribution -system.iobus.trans_dist::WriteResp 136571 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40205 # Transaction distribution +system.iobus.trans_dist::ReadResp 40205 # Transaction distribution +system.iobus.trans_dist::WriteReq 136485 # Transaction distribution +system.iobus.trans_dist::WriteResp 136485 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47478 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -1646,13 +1639,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230970 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230970 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122360 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230940 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353754 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47498 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1665,21 +1658,21 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334312 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155490 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334192 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334192 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 41898000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7491768 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 41589500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 340000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 341500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -1691,77 +1684,77 @@ system.iobus.reqLayer15.occupancy 9500 # La system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25176500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25178000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36502500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36502000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 568938305 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 568968268 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92542000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147730000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147700000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115466 # number of replacements -system.iocache.tags.tagsinuse 10.450358 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115451 # number of replacements +system.iocache.tags.tagsinuse 10.420620 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115482 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115467 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13091904723000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.528286 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.922072 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.220518 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.432629 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653147 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13090295539000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.547144 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.873475 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221697 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429592 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651289 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039722 # Number of tag accesses -system.iocache.tags.data_accesses 1039722 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039587 # Number of tag accesses +system.iocache.tags.data_accesses 1039587 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8821 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8858 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8806 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8843 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115485 # number of demand (read+write) misses -system.iocache.demand_misses::total 115525 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115470 # number of demand (read+write) misses +system.iocache.demand_misses::total 115510 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115485 # number of overall misses -system.iocache.overall_misses::total 115525 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5085500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1915316073 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1920401573 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115470 # number of overall misses +system.iocache.overall_misses::total 115510 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1876442585 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1881528585 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13385817732 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13385817732 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5436500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15301133805 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15306570305 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5436500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15301133805 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15306570305 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13387619683 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13387619683 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15264062268 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15269499268 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15264062268 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15269499268 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8821 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8858 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8806 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8843 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115485 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115525 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115470 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115510 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115485 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115525 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115470 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115510 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1775,53 +1768,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 217131.399274 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 216798.551930 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 213086.825460 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 212770.392966 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125495.178617 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125495.178617 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 132494.556046 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 132495.739494 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 132494.556046 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 132495.739494 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 46527 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125512.072330 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125512.072330 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 132190.718524 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 132192.011670 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 132190.718524 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 132192.011670 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 45104 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3437 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3423 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.537096 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.176746 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8821 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8858 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8806 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8843 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115485 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115525 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115470 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115510 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115485 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115525 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3235500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1474266073 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1477501573 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115470 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115510 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1436142585 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1439378585 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8047307820 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8047307820 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3436500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9521573893 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9525010393 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3436500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9521573893 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9525010393 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8048941203 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8048941203 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9485083788 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9488520788 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9485083788 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9488520788 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1835,96 +1828,96 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87445.945946 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167131.399274 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 166798.551930 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 163086.825460 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 162770.392966 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75445.396947 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75445.396947 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 82448.576811 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 82449.776178 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85912.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 82448.576811 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 82449.776178 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 5129530 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2552281 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3338 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75460.710296 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75460.710296 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 82143.273474 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 82144.583049 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 82143.273474 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 82144.583049 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 2825507 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1398744 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3574 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 54986 # Transaction distribution -system.membus.trans_dist::ReadResp 622896 # Transaction distribution -system.membus.trans_dist::WriteReq 33703 # Transaction distribution -system.membus.trans_dist::WriteResp 33703 # Transaction distribution -system.membus.trans_dist::WritebackDirty 2234356 # Transaction distribution -system.membus.trans_dist::CleanEvict 280040 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4640 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 35684 # Transaction distribution +system.membus.trans_dist::ReadResp 407371 # Transaction distribution +system.membus.trans_dist::WriteReq 33609 # Transaction distribution +system.membus.trans_dist::WriteResp 33609 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1165716 # Transaction distribution +system.membus.trans_dist::CleanEvict 197310 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4655 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 1342054 # Transaction distribution -system.membus.trans_dist::ReadExResp 1342054 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 567911 # Transaction distribution -system.membus.trans_dist::InvalidateReq 700014 # Transaction distribution -system.membus.trans_dist::InvalidateResp 32639 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 477795 # Transaction distribution +system.membus.trans_dist::ReadExResp 477795 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 371688 # Transaction distribution +system.membus.trans_dist::InvalidateReq 607818 # Transaction distribution +system.membus.trans_dist::InvalidateResp 30461 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122360 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6846190 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 6975852 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237668 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237668 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7213520 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6852 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3443320 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3572590 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237411 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237411 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3810001 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155490 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 258164108 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 258334162 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7251648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7251648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 265585810 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 35487 # Total snoops (count) -system.membus.snoopTraffic 181760 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2703311 # Request fanout histogram -system.membus.snoop_fanout::mean 0.013318 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.114632 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13704 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 121594060 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 121763674 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7237120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7237120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 129000794 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 33521 # Total snoops (count) +system.membus.snoopTraffic 195328 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1531252 # Request fanout histogram +system.membus.snoop_fanout::mean 0.022242 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.147469 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2667309 98.67% 98.67% # Request fanout histogram -system.membus.snoop_fanout::1 36002 1.33% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1497194 97.78% 97.78% # Request fanout histogram +system.membus.snoop_fanout::1 34058 2.22% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2703311 # Request fanout histogram -system.membus.reqLayer0.occupancy 104009500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1531252 # Request fanout histogram +system.membus.reqLayer0.occupancy 103704000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5608500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5582500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 14476553313 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7711716413 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 10180600996 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4552014688 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 79038203 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 76660254 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1934,11 +1927,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -1967,30 +1960,30 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558689626000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51277959410000 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 17163 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 16273 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index af7693171..6bd1757fc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -1,79 +1,79 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.177074 # Number of seconds simulated -sim_ticks 47177073828000 # Number of ticks simulated -final_tick 47177073828000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.256223 # Number of seconds simulated +sim_ticks 47256222864000 # Number of ticks simulated +final_tick 47256222864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1523218 # Simulator instruction rate (inst/s) -host_op_rate 1791835 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 73539001789 # Simulator tick rate (ticks/s) -host_mem_usage 696552 # Number of bytes of host memory used -host_seconds 641.52 # Real time elapsed on the host -sim_insts 977181439 # Number of instructions simulated -sim_ops 1149505972 # Number of ops (including micro ops) simulated +host_inst_rate 1686655 # Simulator instruction rate (inst/s) +host_op_rate 2012712 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 87867845670 # Simulator tick rate (ticks/s) +host_mem_usage 696856 # Number of bytes of host memory used +host_seconds 537.81 # Real time elapsed on the host +sim_insts 907100218 # Number of instructions simulated +sim_ops 1082456754 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 157952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 131712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 4192628 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 35968392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 222400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 221568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3097544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 39307632 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 413888 # Number of bytes read from this memory -system.physmem.bytes_read::total 83713716 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4192628 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3097544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7290172 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 102127744 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 160064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 126784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3921972 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 37880648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 245824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 244416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3131208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 41316208 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 428544 # Number of bytes read from this memory +system.physmem.bytes_read::total 87455668 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3921972 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3131208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7053180 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 106476736 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 102148328 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2468 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2058 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 105917 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 562019 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3475 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 3462 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 48506 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 614198 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6467 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1348570 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1595746 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 106497320 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2501 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1981 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 65688 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 591898 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3841 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 3819 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 49032 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 645582 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6696 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1371038 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1663699 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1598320 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3348 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2792 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 88870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 762413 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 4697 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 65658 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 833194 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8773 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1774458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 88870 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 65658 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 154528 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2164775 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1666273 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3387 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2683 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 82994 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 801601 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 5202 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 5172 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 66260 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 874302 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9069 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1850670 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 82994 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 66260 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 149254 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2253179 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2165211 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2164775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3348 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2792 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 88870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 762849 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 4697 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 65658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 833194 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8773 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3939669 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.physmem.bw_write::total 2253615 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2253179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3387 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2683 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 82994 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 802037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 5202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 5172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 66260 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 874302 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9069 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4104285 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -100,9 +100,9 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -110,7 +110,7 @@ system.cf0.dma_write_full_pages 1667 # Nu system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -140,47 +140,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 123270 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 123270 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 123270 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 123270 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 123270 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 94962 90.03% 90.03% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 10516 9.97% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 105478 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 123270 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 130714 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 130714 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 130714 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 130714 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 130714 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 3646000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 3646000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 3646000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 100196 89.16% 89.16% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 12181 10.84% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 112377 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 130714 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 123270 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 105478 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 130714 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 112377 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 105478 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 228748 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 112377 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 243091 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 90958252 # DTB read hits -system.cpu0.dtb.read_misses 87293 # DTB read misses -system.cpu0.dtb.write_hits 84301704 # DTB write hits -system.cpu0.dtb.write_misses 35977 # DTB write misses +system.cpu0.dtb.read_hits 93175374 # DTB read hits +system.cpu0.dtb.read_misses 92435 # DTB read misses +system.cpu0.dtb.write_hits 86370526 # DTB write hits +system.cpu0.dtb.write_misses 38279 # DTB write misses system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 35878 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 51023 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1132 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 36393 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 5554 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 5252 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10284 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 91045545 # DTB read accesses -system.cpu0.dtb.write_accesses 84337681 # DTB write accesses +system.cpu0.dtb.perms_faults 10620 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 93267809 # DTB read accesses +system.cpu0.dtb.write_accesses 86408805 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 175259956 # DTB hits -system.cpu0.dtb.misses 123270 # DTB misses -system.cpu0.dtb.accesses 175383226 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 179545900 # DTB hits +system.cpu0.dtb.misses 130714 # DTB misses +system.cpu0.dtb.accesses 179676614 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -210,468 +210,466 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 60279 # Table walker walks requested -system.cpu0.itb.walker.walksLong 60279 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 60279 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 60279 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 60279 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 54211 98.84% 98.84% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 635 1.16% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 54846 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 60670 # Table walker walks requested +system.cpu0.itb.walker.walksLong 60670 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 60670 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 60670 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 60670 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 3644500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 3644500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 3644500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 54534 98.81% 98.81% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 657 1.19% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 55191 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60279 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60279 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60670 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60670 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 54846 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 54846 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 115125 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 489463139 # ITB inst hits -system.cpu0.itb.inst_misses 60279 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55191 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55191 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 115861 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 460432126 # ITB inst hits +system.cpu0.itb.inst_misses 60670 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 24716 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 51023 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1132 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 25186 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 489523418 # ITB inst accesses -system.cpu0.itb.hits 489463139 # DTB hits -system.cpu0.itb.misses 60279 # DTB misses -system.cpu0.itb.accesses 489523418 # DTB accesses -system.cpu0.numPwrStateTransitions 26258 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 13129 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 3571424062.507959 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 90351330790.457672 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3131 23.85% 23.85% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 9971 75.95% 99.79% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 460492796 # ITB inst accesses +system.cpu0.itb.hits 460432126 # DTB hits +system.cpu0.itb.misses 60670 # DTB misses +system.cpu0.itb.accesses 460492796 # DTB accesses +system.cpu0.numPwrStateTransitions 26581 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 13288 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 3535659625.946418 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 88810636016.861053 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3229 24.30% 24.30% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 10032 75.50% 99.80% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.82% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 2 0.02% 99.83% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 2 0.02% 99.89% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::overflows 14 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 7510114609000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 13129 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 287847311333 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 46889226516667 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 94354160786 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 7390911651500 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 13288 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 274377754424 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46981845109576 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 94512459022 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13129 # number of quiesce instructions executed -system.cpu0.committedInsts 489228722 # Number of instructions committed -system.cpu0.committedOps 575357792 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 527304848 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 518985 # Number of float alu accesses -system.cpu0.num_func_calls 28507888 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 75158499 # number of instructions that are conditional controls -system.cpu0.num_int_insts 527304848 # number of integer instructions -system.cpu0.num_fp_insts 518985 # number of float instructions -system.cpu0.num_int_register_reads 772493030 # number of times the integer registers were read -system.cpu0.num_int_register_writes 418386904 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 837696 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 439396 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 131494560 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 131170441 # number of times the CC registers were written -system.cpu0.num_mem_refs 175360180 # number of memory refs -system.cpu0.num_load_insts 91031152 # Number of load instructions -system.cpu0.num_store_insts 84329028 # Number of store instructions -system.cpu0.num_idle_cycles 93778466083.220322 # Number of idle cycles -system.cpu0.num_busy_cycles 575694702.779680 # Number of busy cycles -system.cpu0.not_idle_fraction 0.006101 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.993899 # Percentage of idle cycles -system.cpu0.Branches 109461640 # Number of branches fetched +system.cpu0.kern.inst.quiesce 13293 # number of quiesce instructions executed +system.cpu0.committedInsts 460154624 # Number of instructions committed +system.cpu0.committedOps 548413661 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 509180687 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 522850 # Number of float alu accesses +system.cpu0.num_func_calls 28957516 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 67014933 # number of instructions that are conditional controls +system.cpu0.num_int_insts 509180687 # number of integer instructions +system.cpu0.num_fp_insts 522850 # number of float instructions +system.cpu0.num_int_register_reads 679939222 # number of times the integer registers were read +system.cpu0.num_int_register_writes 397756518 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 842282 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 446532 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 104721942 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 104390194 # number of times the CC registers were written +system.cpu0.num_mem_refs 179652770 # number of memory refs +system.cpu0.num_load_insts 93252874 # Number of load instructions +system.cpu0.num_store_insts 86399896 # Number of store instructions +system.cpu0.num_idle_cycles 93963703435.962769 # Number of idle cycles +system.cpu0.num_busy_cycles 548755586.037238 # Number of busy cycles +system.cpu0.not_idle_fraction 0.005806 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.994194 # Percentage of idle cycles +system.cpu0.Branches 101918794 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 398983706 69.31% 69.31% # Class of executed instruction -system.cpu0.op_class::IntMult 1214289 0.21% 69.52% # Class of executed instruction -system.cpu0.op_class::IntDiv 59472 0.01% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatAdd 8 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatCmp 13 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatCvt 21 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatMultAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatMisc 72490 0.01% 69.54% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::MemRead 90970869 15.80% 85.34% # Class of executed instruction -system.cpu0.op_class::MemWrite 83942858 14.58% 99.92% # Class of executed instruction -system.cpu0.op_class::FloatMemRead 60283 0.01% 99.93% # Class of executed instruction -system.cpu0.op_class::FloatMemWrite 386170 0.07% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 367730477 67.01% 67.01% # Class of executed instruction +system.cpu0.op_class::IntMult 1235344 0.23% 67.24% # Class of executed instruction +system.cpu0.op_class::IntDiv 59786 0.01% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatAdd 8 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatCmp 13 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatCvt 21 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatMultAcc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatMisc 72659 0.01% 67.26% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::MemRead 93191543 16.98% 84.24% # Class of executed instruction +system.cpu0.op_class::MemWrite 86011078 15.67% 99.92% # Class of executed instruction +system.cpu0.op_class::FloatMemRead 61331 0.01% 99.93% # Class of executed instruction +system.cpu0.op_class::FloatMemWrite 388818 0.07% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 575690180 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 6169123 # number of replacements -system.cpu0.dcache.tags.tagsinuse 502.902441 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 169021316 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6169635 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.395675 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.902441 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.982231 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.982231 # Average percentage of cache occupancy +system.cpu0.op_class::total 548751079 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 6361267 # number of replacements +system.cpu0.dcache.tags.tagsinuse 499.577143 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 173125033 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6361779 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.213305 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 13850500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.577143 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.975737 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.975737 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 356856913 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 356856913 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 84588460 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 84588460 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 79569773 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 79569773 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 213774 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 213774 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259782 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 259782 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2069774 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 2069774 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2033350 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 2033350 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 164418015 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 164418015 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 164631789 # number of overall hits -system.cpu0.dcache.overall_hits::total 164631789 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3250756 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3250756 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1461940 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1461940 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 763460 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 763460 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 814949 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 814949 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 115689 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 115689 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 151036 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 151036 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5527645 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5527645 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6291105 # number of overall misses -system.cpu0.dcache.overall_misses::total 6291105 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 87839216 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 87839216 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81031713 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 81031713 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 977234 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 977234 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1074731 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1074731 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2185463 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2185463 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2184386 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2184386 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 169945660 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 169945660 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 170922894 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 170922894 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037008 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037008 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018042 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018042 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781246 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781246 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.758282 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.758282 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.052936 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052936 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.069143 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.069143 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032526 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.032526 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036807 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.036807 # miss rate for overall accesses +system.cpu0.dcache.tags.tag_accesses 365631383 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 365631383 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 86603750 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 86603750 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 81517458 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 81517458 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 217950 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 217950 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259225 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 259225 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2136353 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 2136353 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2100440 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 2100440 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 168380433 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 168380433 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 168598383 # number of overall hits +system.cpu0.dcache.overall_hits::total 168598383 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3343142 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3343142 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1509525 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1509525 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 802963 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 802963 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 820079 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 820079 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119939 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 119939 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 154648 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 154648 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 5672746 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 5672746 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 6475709 # number of overall misses +system.cpu0.dcache.overall_misses::total 6475709 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 89946892 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 89946892 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 83026983 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 83026983 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1020913 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1020913 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1079304 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1079304 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2256292 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2256292 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2255088 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2255088 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 174053179 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 174053179 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 175074092 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 175074092 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037168 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037168 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018181 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018181 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.786515 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.786515 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.759822 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.759822 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053158 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053158 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.068577 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.068577 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032592 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.032592 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036988 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.036988 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 6169123 # number of writebacks -system.cpu0.dcache.writebacks::total 6169123 # number of writebacks -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 5445857 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.988996 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 484071611 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5446369 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 88.879694 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 5759898000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.988996 # Average occupied blocks per requestor +system.cpu0.dcache.writebacks::writebacks 6361267 # number of writebacks +system.cpu0.dcache.writebacks::total 6361267 # number of writebacks +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 5436488 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.989232 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 455050312 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5437000 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 83.695110 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 5738328000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989232 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 263 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 984482344 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 984482344 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 484071611 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 484071611 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 484071611 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 484071611 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 484071611 # number of overall hits -system.cpu0.icache.overall_hits::total 484071611 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 5446374 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 5446374 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 5446374 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 5446374 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 5446374 # number of overall misses -system.cpu0.icache.overall_misses::total 5446374 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 489517985 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 489517985 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 489517985 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 489517985 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 489517985 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 489517985 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011126 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011126 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011126 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011126 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011126 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011126 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 926411639 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 926411639 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 455050312 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 455050312 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 455050312 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 455050312 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 455050312 # number of overall hits +system.cpu0.icache.overall_hits::total 455050312 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 5437005 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 5437005 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 5437005 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 5437005 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 5437005 # number of overall misses +system.cpu0.icache.overall_misses::total 5437005 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 460487317 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 460487317 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 460487317 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 460487317 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 460487317 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 460487317 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011807 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011807 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011807 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011807 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011807 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011807 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 5445857 # number of writebacks -system.cpu0.icache.writebacks::total 5445857 # number of writebacks -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.writebacks::writebacks 5436488 # number of writebacks +system.cpu0.icache.writebacks::total 5436488 # number of writebacks +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2533357 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15711.685213 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 9303903 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2548994 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 3.650029 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15660.837363 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 30.957912 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 19.889938 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.955862 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001890 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001214 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.958965 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15585 # Occupied blocks per task id +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 2619867 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15716.053325 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 9431762 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2635628 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 3.578563 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 269403000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 15665.638757 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 30.618352 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 19.796216 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.956155 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001869 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001208 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.959232 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 78 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15683 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 61 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 407 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2073 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5396 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5335 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2374 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003174 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.951233 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 396876772 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 396876772 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 281069 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 152429 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 433498 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 4385344 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 4385344 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 7228256 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 7228256 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 628811 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 628811 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4957899 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 4957899 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2920611 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 2920611 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 215443 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 215443 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 281069 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 152429 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 4957899 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3549422 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 8940819 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 281069 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 152429 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 4957899 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3549422 # number of overall hits -system.cpu0.l2cache.overall_hits::total 8940819 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 20714 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10073 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 30787 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 134964 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 134964 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 151036 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 151036 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 698165 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 698165 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 488475 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 488475 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1209294 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 1209294 # number of ReadSharedReq misses -system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 599506 # number of InvalidateReq misses -system.cpu0.l2cache.InvalidateReq_misses::total 599506 # number of InvalidateReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 20714 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10073 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 488475 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1907459 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 2426721 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 20714 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10073 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 488475 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1907459 # number of overall misses -system.cpu0.l2cache.overall_misses::total 2426721 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 301783 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 162502 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 464285 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4385344 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 4385344 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 7228256 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 7228256 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 134964 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 134964 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 151036 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 151036 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1326976 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1326976 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5446374 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 5446374 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4129905 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 4129905 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 814949 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::total 814949 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 301783 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 162502 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 5446374 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5456881 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 11367540 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 301783 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 162502 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 5446374 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5456881 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 11367540 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.068639 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.061987 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.066311 # miss rate for ReadReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 414 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2189 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5717 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5104 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2259 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004761 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.957214 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 403271236 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 403271236 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 300949 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 154418 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 455367 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 4541229 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 4541229 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 7255159 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 7255159 # number of WritebackClean hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 644334 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 644334 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4939776 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 4939776 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3020372 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 3020372 # number of ReadSharedReq hits +system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 222433 # number of InvalidateReq hits +system.cpu0.l2cache.InvalidateReq_hits::total 222433 # number of InvalidateReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 300949 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 154418 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 4939776 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3664706 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 9059849 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 300949 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 154418 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 4939776 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3664706 # number of overall hits +system.cpu0.l2cache.overall_hits::total 9059849 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 21207 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10120 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 31327 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 134662 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 134662 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 154648 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 154648 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 730529 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 730529 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 497229 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 497229 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1245672 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 1245672 # number of ReadSharedReq misses +system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 597646 # number of InvalidateReq misses +system.cpu0.l2cache.InvalidateReq_misses::total 597646 # number of InvalidateReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 21207 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10120 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 497229 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1976201 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 2504757 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 21207 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10120 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 497229 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1976201 # number of overall misses +system.cpu0.l2cache.overall_misses::total 2504757 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 322156 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 164538 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 486694 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4541229 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 4541229 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 7255159 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 7255159 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 134662 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 134662 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 154648 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 154648 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1374863 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1374863 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5437005 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 5437005 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4266044 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 4266044 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 820079 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::total 820079 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 322156 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 164538 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 5437005 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 5640907 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 11564606 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 322156 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 164538 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 5437005 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 5640907 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 11564606 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.065828 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.061506 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.064367 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.526132 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.526132 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.089688 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.089688 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.292814 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.292814 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.735636 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.735636 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.068639 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.061987 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.089688 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.349551 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.213478 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.068639 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.061987 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.089688 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.349551 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.213478 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.531347 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.531347 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.091453 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.091453 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.291997 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.291997 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.728766 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.728766 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.065828 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.061506 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.091453 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.350334 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.216588 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.065828 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.061506 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.091453 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.350334 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.216588 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.writebacks::writebacks 1537445 # number of writebacks -system.cpu0.l2cache.writebacks::total 1537445 # number of writebacks -system.cpu0.toL2Bus.snoop_filter.tot_requests 23876126 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12158327 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1385 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 304592 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 304592 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.l2cache.writebacks::writebacks 1595934 # number of writebacks +system.cpu0.l2cache.writebacks::total 1595934 # number of writebacks +system.cpu0.toL2Bus.snoop_filter.tot_requests 24251358 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12353916 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1372 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 295344 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 295344 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 614484 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 10190763 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 32444 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 32444 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 4385344 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 7229636 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 134964 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 151036 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 286000 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1326976 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1326976 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5446374 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4129905 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 814949 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 814949 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16424855 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19414693 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 360152 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 717544 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 36917244 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 697275284 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 744257581 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1440608 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2870176 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1445843649 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 4732413 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 102900484 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 28818191 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.019582 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.138557 # Request fanout histogram +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 597776 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 10300825 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 32321 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 32321 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 4541229 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 7256526 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 134662 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 154648 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 289310 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1374863 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1374863 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5437005 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4266044 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 820079 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 820079 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16319948 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19991301 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 362448 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 758854 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 37432551 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 695922452 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 768331945 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1449792 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3035416 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1468739605 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 4809457 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 106507396 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 29250499 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.019295 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.137560 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 28253885 98.04% 98.04% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 564306 1.96% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 28686107 98.07% 98.07% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 564392 1.93% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 28818191 # Request fanout histogram -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.snoop_fanout::total 29250499 # Request fanout histogram +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -701,47 +699,47 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 145570 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 145570 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walkWaitTime::samples 145570 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 145570 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 145570 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walksPending::samples -274399872 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -274399872 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -274399872 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 112948 88.82% 88.82% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 14218 11.18% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 127166 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 145570 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 149830 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 149830 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 149830 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 149830 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 149830 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walksPending::samples -295973872 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -295973872 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -295973872 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 115525 88.27% 88.27% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 15355 11.73% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 130880 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 149830 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 145570 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 127166 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 149830 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 130880 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 127166 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 272736 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 130880 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 280710 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 92188600 # DTB read hits -system.cpu1.dtb.read_misses 112898 # DTB read misses -system.cpu1.dtb.write_hits 82869602 # DTB write hits -system.cpu1.dtb.write_misses 32672 # DTB write misses +system.cpu1.dtb.read_hits 93113840 # DTB read hits +system.cpu1.dtb.read_misses 115970 # DTB read misses +system.cpu1.dtb.write_hits 83725509 # DTB write hits +system.cpu1.dtb.write_misses 33860 # DTB write misses system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 44985 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 51023 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1132 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 45912 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4483 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4582 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11594 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 92301498 # DTB read accesses -system.cpu1.dtb.write_accesses 82902274 # DTB write accesses +system.cpu1.dtb.perms_faults 11647 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 93229810 # DTB read accesses +system.cpu1.dtb.write_accesses 83759369 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 175058202 # DTB hits -system.cpu1.dtb.misses 145570 # DTB misses -system.cpu1.dtb.accesses 175203772 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 176839349 # DTB hits +system.cpu1.dtb.misses 149830 # DTB misses +system.cpu1.dtb.accesses 176989179 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -771,471 +769,467 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 62174 # Table walker walks requested -system.cpu1.itb.walker.walksLong 62174 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walkWaitTime::samples 62174 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 62174 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 62174 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walksPending::samples -274400872 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -274400872 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -274400872 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 55194 99.03% 99.03% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 542 0.97% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 55736 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 62588 # Table walker walks requested +system.cpu1.itb.walker.walksLong 62588 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 62588 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 62588 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 62588 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walksPending::samples -295974872 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -295974872 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -295974872 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 55491 99.07% 99.07% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 523 0.93% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 56014 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 62174 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 62174 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 62588 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 62588 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55736 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55736 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 117910 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 488205248 # ITB inst hits -system.cpu1.itb.inst_misses 62174 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56014 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56014 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 118602 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 447202663 # ITB inst hits +system.cpu1.itb.inst_misses 62588 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 31602 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 51023 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1132 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 32344 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 488267422 # ITB inst accesses -system.cpu1.itb.hits 488205248 # DTB hits -system.cpu1.itb.misses 62174 # DTB misses -system.cpu1.itb.accesses 488267422 # DTB accesses -system.cpu1.numPwrStateTransitions 12500 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 6250 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 7502374904.322560 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 140163345879.751923 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 4511 72.18% 72.18% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 1712 27.39% 99.57% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 7 0.11% 99.68% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.05% 99.76% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.78% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.79% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 447265251 # ITB inst accesses +system.cpu1.itb.hits 447202663 # DTB hits +system.cpu1.itb.misses 62588 # DTB misses +system.cpu1.itb.accesses 447265251 # DTB accesses +system.cpu1.numPwrStateTransitions 12622 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 6311 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 7445577920.705118 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 138960729730.016388 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 4567 72.37% 72.37% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 1718 27.22% 99.59% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.08% 99.67% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 3 0.05% 99.71% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.03% 99.75% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.03% 99.78% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.79% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::overflows 13 0.21% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 7033264907012 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 6250 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 287230675984 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 46889843152016 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 94354153907 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 6953792880276 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 6311 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 267180606430 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 46989042257570 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 94512452040 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 6250 # number of quiesce instructions executed -system.cpu1.committedInsts 487952717 # Number of instructions committed -system.cpu1.committedOps 574148180 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 526945204 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 380393 # Number of float alu accesses -system.cpu1.num_func_calls 28766283 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 74749330 # number of instructions that are conditional controls -system.cpu1.num_int_insts 526945204 # number of integer instructions -system.cpu1.num_fp_insts 380393 # number of float instructions -system.cpu1.num_int_register_reads 777937433 # number of times the integer registers were read -system.cpu1.num_int_register_writes 419402413 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 618522 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 309432 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 129016491 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 128726040 # number of times the CC registers were written -system.cpu1.num_mem_refs 175180123 # number of memory refs -system.cpu1.num_load_insts 92288401 # Number of load instructions -system.cpu1.num_store_insts 82891722 # Number of store instructions -system.cpu1.num_idle_cycles 93779692516.971710 # Number of idle cycles -system.cpu1.num_busy_cycles 574461390.028282 # Number of busy cycles -system.cpu1.not_idle_fraction 0.006088 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.993912 # Percentage of idle cycles -system.cpu1.Branches 108727125 # Number of branches fetched +system.cpu1.kern.inst.quiesce 6311 # number of quiesce instructions executed +system.cpu1.committedInsts 446945594 # Number of instructions committed +system.cpu1.committedOps 534043093 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 497796457 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 375258 # Number of float alu accesses +system.cpu1.num_func_calls 29044812 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 64056743 # number of instructions that are conditional controls +system.cpu1.num_int_insts 497796457 # number of integer instructions +system.cpu1.num_fp_insts 375258 # number of float instructions +system.cpu1.num_int_register_reads 659899184 # number of times the integer registers were read +system.cpu1.num_int_register_writes 389220604 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 611056 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 302696 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 95980638 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 95700174 # number of times the CC registers were written +system.cpu1.num_mem_refs 176965712 # number of memory refs +system.cpu1.num_load_insts 93216701 # Number of load instructions +system.cpu1.num_store_insts 83749011 # Number of store instructions +system.cpu1.num_idle_cycles 93978090791.450775 # Number of idle cycles +system.cpu1.num_busy_cycles 534361248.549225 # Number of busy cycles +system.cpu1.not_idle_fraction 0.005654 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.994346 # Percentage of idle cycles +system.cpu1.Branches 98364194 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 398021787 69.29% 69.29% # Class of executed instruction -system.cpu1.op_class::IntMult 1155567 0.20% 69.49% # Class of executed instruction -system.cpu1.op_class::IntDiv 62024 0.01% 69.50% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::FloatMultAcc 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction -system.cpu1.op_class::FloatMisc 37076 0.01% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::MemRead 92237466 16.06% 85.56% # Class of executed instruction -system.cpu1.op_class::MemWrite 82599340 14.38% 99.94% # Class of executed instruction -system.cpu1.op_class::FloatMemRead 50935 0.01% 99.95% # Class of executed instruction -system.cpu1.op_class::FloatMemWrite 292382 0.05% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 356129610 66.65% 66.65% # Class of executed instruction +system.cpu1.op_class::IntMult 1162336 0.22% 66.86% # Class of executed instruction +system.cpu1.op_class::IntDiv 62196 0.01% 66.88% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::FloatMultAcc 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::FloatMisc 36452 0.01% 66.88% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 66.88% # Class of executed instruction +system.cpu1.op_class::MemRead 93166406 17.44% 84.32% # Class of executed instruction +system.cpu1.op_class::MemWrite 83460500 15.62% 99.94% # Class of executed instruction +system.cpu1.op_class::FloatMemRead 50295 0.01% 99.95% # Class of executed instruction +system.cpu1.op_class::FloatMemWrite 288511 0.05% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 574456577 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 6056013 # number of replacements -system.cpu1.dcache.tags.tagsinuse 439.385542 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 169014740 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 6056525 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 27.906223 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8470277781000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 439.385542 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.858175 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.858175 # Average percentage of cache occupancy +system.cpu1.op_class::total 534356306 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 6135169 # number of replacements +system.cpu1.dcache.tags.tagsinuse 439.724728 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 170720636 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 6135681 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.824236 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8470256211500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 439.724728 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.858837 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.858837 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 345 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 376 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 136 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 356467951 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 356467951 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 85651314 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 85651314 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 78663816 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 78663816 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 189367 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 189367 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 66166 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 66166 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2074874 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 2074874 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2069738 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 2069738 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 164381296 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 164381296 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 164570663 # number of overall hits -system.cpu1.dcache.overall_hits::total 164570663 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3417226 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3417226 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1481686 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1481686 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 799274 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 799274 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 443256 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 443256 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 150141 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 150141 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 154039 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 154039 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5342168 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5342168 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6141442 # number of overall misses -system.cpu1.dcache.overall_misses::total 6141442 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 89068540 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 89068540 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 80145502 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 80145502 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 988641 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 988641 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 509422 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 509422 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2225015 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2225015 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2223777 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 2223777 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 169723464 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 169723464 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 170712105 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 170712105 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038366 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.038366 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018487 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018487 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808457 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808457 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870116 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870116 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.067479 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.067479 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.069269 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.069269 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031476 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031476 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035975 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035975 # miss rate for overall accesses +system.cpu1.dcache.tags.tag_accesses 360116437 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 360116437 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 86463703 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 86463703 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 79472088 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 79472088 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 192310 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 192310 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 67346 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 67346 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2116228 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 2116228 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2109994 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 2109994 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 166003137 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 166003137 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 166195447 # number of overall hits +system.cpu1.dcache.overall_hits::total 166195447 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3476659 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3476659 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1488439 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1488439 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 809340 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 809340 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 440862 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 440862 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 151875 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 151875 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 156847 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 156847 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5405960 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5405960 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 6215300 # number of overall misses +system.cpu1.dcache.overall_misses::total 6215300 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 89940362 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 89940362 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 80960527 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 80960527 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 1001650 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 1001650 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 508208 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 508208 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2268103 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 2268103 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2266841 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 2266841 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 171409097 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 171409097 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 172410747 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 172410747 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038655 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.038655 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018385 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018385 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808007 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808007 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.867483 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.867483 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066961 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066961 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.069192 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.069192 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031538 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031538 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036049 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.036049 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 6056013 # number of writebacks -system.cpu1.dcache.writebacks::total 6056013 # number of writebacks -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 4848965 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.412961 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 483411507 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 4849477 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 99.683225 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8470205818500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.412961 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969557 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969557 # Average percentage of cache occupancy +system.cpu1.dcache.writebacks::writebacks 6135169 # number of writebacks +system.cpu1.dcache.writebacks::total 6135169 # number of writebacks +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 4821762 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.439302 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 442436403 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 4822274 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 91.748499 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8470184249000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.439302 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969608 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969608 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 146 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 151 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 981371445 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 981371445 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 483411507 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 483411507 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 483411507 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 483411507 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 483411507 # number of overall hits -system.cpu1.icache.overall_hits::total 483411507 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 4849477 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 4849477 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 4849477 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 4849477 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 4849477 # number of overall misses -system.cpu1.icache.overall_misses::total 4849477 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 488260984 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 488260984 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 488260984 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 488260984 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 488260984 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 488260984 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009932 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.009932 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009932 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.009932 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009932 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.009932 # miss rate for overall accesses +system.cpu1.icache.tags.tag_accesses 899339628 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 899339628 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 442436403 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 442436403 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 442436403 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 442436403 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 442436403 # number of overall hits +system.cpu1.icache.overall_hits::total 442436403 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 4822274 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 4822274 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 4822274 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 4822274 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 4822274 # number of overall misses +system.cpu1.icache.overall_misses::total 4822274 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 447258677 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 447258677 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 447258677 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 447258677 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 447258677 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 447258677 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.010782 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.010782 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.010782 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.010782 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.010782 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.010782 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 4848965 # number of writebacks -system.cpu1.icache.writebacks::total 4848965 # number of writebacks -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.writebacks::writebacks 4821762 # number of writebacks +system.cpu1.icache.writebacks::total 4821762 # number of writebacks +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 2230269 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13059.321303 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 8938644 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2245943 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 3.979907 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 2257136 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13044.860493 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 8980176 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2273016 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 3.950776 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 13021.698131 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 21.453000 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 16.170172 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.794781 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001309 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000987 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.797078 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 85 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15589 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 49 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 2501 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7586 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3485 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1787 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005188 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.951477 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 374536552 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 374536552 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 340661 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155597 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 496258 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 4122422 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 4122422 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 6782171 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 6782171 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 622232 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 622232 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4374488 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 4374488 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3137655 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 3137655 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 166849 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 166849 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 340661 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 155597 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4374488 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3759887 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 8630633 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 340661 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 155597 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4374488 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3759887 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8630633 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 22356 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 11279 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 33635 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 145163 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 145163 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 154039 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 154039 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 714291 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 714291 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 474989 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 474989 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1228986 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 1228986 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 276407 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 276407 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 22356 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 11279 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 474989 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1943277 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 2451901 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 22356 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 11279 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 474989 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1943277 # number of overall misses -system.cpu1.l2cache.overall_misses::total 2451901 # number of overall misses -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 363017 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 166876 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 529893 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4122422 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 4122422 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 6782171 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 6782171 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 145163 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 145163 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 154039 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 154039 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1336523 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1336523 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4849477 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 4849477 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4366641 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 4366641 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 443256 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::total 443256 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 363017 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 166876 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 4849477 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 5703164 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 11082534 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 363017 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 166876 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 4849477 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 5703164 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 11082534 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.061584 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.067589 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.063475 # miss rate for ReadReq accesses +system.cpu1.l2cache.tags.occ_blocks::writebacks 13005.388479 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 22.571640 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 16.900374 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.793786 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001378 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001032 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.796195 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 60 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15820 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 29 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 398 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 2679 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7364 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3549 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1830 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003662 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.965576 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 376404615 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 376404615 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 350077 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155851 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 505928 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 4161473 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 4161473 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 6795092 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 6795092 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 621244 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 621244 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4351439 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 4351439 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3193387 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 3193387 # number of ReadSharedReq hits +system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 167103 # number of InvalidateReq hits +system.cpu1.l2cache.InvalidateReq_hits::total 167103 # number of InvalidateReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 350077 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 155851 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 4351439 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3814631 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 8671998 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 350077 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 155851 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 4351439 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3814631 # number of overall hits +system.cpu1.l2cache.overall_hits::total 8671998 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 22799 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 11519 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 34318 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 141879 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 141879 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 156847 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 156847 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 725316 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 725316 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 470835 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 470835 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1244487 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 1244487 # number of ReadSharedReq misses +system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 273759 # number of InvalidateReq misses +system.cpu1.l2cache.InvalidateReq_misses::total 273759 # number of InvalidateReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 22799 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 11519 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 470835 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1969803 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 2474956 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 22799 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 11519 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 470835 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1969803 # number of overall misses +system.cpu1.l2cache.overall_misses::total 2474956 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 372876 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 167370 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 540246 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4161473 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 4161473 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 6795092 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 6795092 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 141879 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 141879 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 156847 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 156847 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1346560 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1346560 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4822274 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 4822274 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4437874 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 4437874 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 440862 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::total 440862 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 372876 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 167370 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 4822274 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 5784434 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 11146954 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 372876 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 167370 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 4822274 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 5784434 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 11146954 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.061144 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.068824 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.063523 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.534440 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.534440 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097946 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097946 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.281449 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.281449 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.623583 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.623583 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.061584 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.067589 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097946 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.340737 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.221240 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.061584 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.067589 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097946 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.340737 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.221240 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.538644 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.538644 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097638 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097638 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.280424 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.280424 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.620963 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.620963 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.061144 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.068824 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097638 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.340535 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.222030 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.061144 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.068824 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097638 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.340535 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.222030 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.writebacks::writebacks 1226637 # number of writebacks -system.cpu1.l2cache.writebacks::total 1226637 # number of writebacks -system.cpu1.toL2Bus.snoop_filter.tot_requests 22478068 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11482434 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 385 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 282472 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 282472 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.l2cache.writebacks::writebacks 1247214 # number of writebacks +system.cpu1.l2cache.writebacks::total 1247214 # number of writebacks +system.cpu1.toL2Bus.snoop_filter.tot_requests 22589206 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11541877 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 366 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 281509 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 281509 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 614190 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9830308 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 6354 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 6354 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4122422 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 6782556 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 145163 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 154039 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 299202 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1336523 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1336523 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4849477 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4366641 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 443256 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 443256 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14548179 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18972689 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 371656 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 843740 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 34736264 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 620700808 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 752625722 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1486624 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3374960 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1378188114 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 4390439 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 84812544 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 27053766 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.020745 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.142530 # Request fanout histogram +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 627108 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9887256 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 6357 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 6357 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4161473 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 6795458 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 141879 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 156847 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 298726 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1346560 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1346560 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4822274 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4437874 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 440862 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 440862 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14466570 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 19208649 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 374184 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 867050 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 34916453 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 617218824 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 762892902 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1496736 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3468200 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1385076662 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4471176 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 86426880 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 27252775 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.020850 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.142882 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 26492533 97.93% 97.93% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 561233 2.07% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 26684555 97.92% 97.92% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 568220 2.08% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 27053766 # Request fanout histogram -system.iobus.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40293 # Transaction distribution -system.iobus.trans_dist::ReadResp 40293 # Transaction distribution -system.iobus.trans_dist::WriteReq 136632 # Transaction distribution -system.iobus.trans_dist::WriteResp 136632 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47630 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.snoop_fanout::total 27252775 # Request fanout histogram +system.iobus.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40208 # Transaction distribution +system.iobus.trans_dist::ReadResp 40208 # Transaction distribution +system.iobus.trans_dist::WriteReq 136550 # Transaction distribution +system.iobus.trans_dist::WriteResp 136550 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47302 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -1248,13 +1242,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122564 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231206 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231206 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122236 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231200 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231200 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353850 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47650 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353516 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47322 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1267,56 +1261,56 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155671 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338840 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338840 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155343 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338816 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338816 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496597 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115584 # number of replacements -system.iocache.tags.tagsinuse 11.285245 # Cycle average of tags in use +system.iobus.pkt_size::total 7496245 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115580 # number of replacements +system.iocache.tags.tagsinuse 11.294790 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115600 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115596 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9107772860509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.859437 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.425808 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.241215 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.464113 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705328 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9107754177509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.848737 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.446053 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240546 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.465378 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705924 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040784 # Number of tag accesses -system.iocache.tags.data_accesses 1040784 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1040757 # Number of tag accesses +system.iocache.tags.data_accesses 1040757 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8875 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8912 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8872 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8909 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115603 # number of demand (read+write) misses -system.iocache.demand_misses::total 115643 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115600 # number of demand (read+write) misses +system.iocache.demand_misses::total 115640 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115603 # number of overall misses -system.iocache.overall_misses::total 115643 # number of overall misses +system.iocache.overall_misses::realview.ide 115600 # number of overall misses +system.iocache.overall_misses::total 115640 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8875 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8912 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8872 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8909 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115603 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115643 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115600 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115640 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115603 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115643 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115600 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115640 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1336,282 +1330,281 @@ system.iocache.blocked::no_mshrs 0 # nu system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106694 # number of writebacks -system.iocache.writebacks::total 106694 # number of writebacks -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1923250 # number of replacements -system.l2c.tags.tagsinuse 65186.498545 # Cycle average of tags in use -system.l2c.tags.total_refs 5749330 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1985687 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.895386 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 477350500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 10983.634083 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 57.375221 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 60.020702 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3162.214163 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 16603.028209 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 344.016385 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 410.384147 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2922.724883 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 30643.100751 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.167597 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000875 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000916 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.048252 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.253342 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005249 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.006262 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.044597 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.467577 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994667 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 241 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62196 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 239 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 271 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3250 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4725 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53923 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.003677 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.949036 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 71541788 # Number of tag accesses -system.l2c.tags.data_accesses 71541788 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2764082 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2764082 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 56104 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 51044 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 107148 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 8413 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 7881 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 16294 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 200040 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 182839 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 382879 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 12914 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5340 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 425659 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 696237 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 12397 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4498 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 426584 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 681796 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2265425 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 112817 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 103406 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 216223 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 12914 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5340 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 425659 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 896277 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 12397 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4498 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 426584 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 864635 # number of demand (read+write) hits -system.l2c.demand_hits::total 2648304 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 12914 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5340 # number of overall hits -system.l2c.overall_hits::cpu0.inst 425659 # number of overall hits -system.l2c.overall_hits::cpu0.data 896277 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 12397 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4498 # number of overall hits -system.l2c.overall_hits::cpu1.inst 426584 # number of overall hits -system.l2c.overall_hits::cpu1.data 864635 # number of overall hits -system.l2c.overall_hits::total 2648304 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 19306 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 23056 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 42362 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 403 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 802 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1205 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 372703 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 418393 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 791096 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2468 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2058 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 62816 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 191372 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3475 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3462 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 48405 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 197388 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 511444 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 440136 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 128597 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 568733 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2468 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2058 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 62816 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 564075 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3475 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 3462 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 48405 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 615781 # number of demand (read+write) misses -system.l2c.demand_misses::total 1302540 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2468 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2058 # number of overall misses -system.l2c.overall_misses::cpu0.inst 62816 # number of overall misses -system.l2c.overall_misses::cpu0.data 564075 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3475 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 3462 # number of overall misses -system.l2c.overall_misses::cpu1.inst 48405 # number of overall misses -system.l2c.overall_misses::cpu1.data 615781 # number of overall misses -system.l2c.overall_misses::total 1302540 # number of overall misses -system.l2c.WritebackDirty_accesses::writebacks 2764082 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 2764082 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 75410 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 74100 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 149510 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 8816 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 8683 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 17499 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 572743 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 601232 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 1173975 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 15382 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7398 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 488475 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 887609 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 15872 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7960 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 474989 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 879184 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 2776869 # number of ReadSharedReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu0.data 552953 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu1.data 232003 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::total 784956 # number of InvalidateReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 15382 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 7398 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 488475 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1460352 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 15872 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7960 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 474989 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 1480416 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3950844 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 15382 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 7398 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 488475 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1460352 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 15872 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7960 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 474989 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 1480416 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3950844 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.256014 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.311147 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.283339 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.045712 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.092364 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.068861 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.650733 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.695893 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.673861 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.160447 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.278183 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.128596 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.215604 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.218939 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.434925 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.101908 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.224513 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.184180 # miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_miss_rate::cpu0.data 0.795974 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::cpu1.data 0.554290 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::total 0.724541 # miss rate for InvalidateReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.160447 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.278183 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.128596 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.386260 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.218939 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.434925 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.101908 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.415951 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.329687 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.160447 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.278183 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.128596 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.386260 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.218939 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.434925 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.101908 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.415951 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.329687 # miss rate for overall accesses +system.iocache.writebacks::writebacks 106693 # number of writebacks +system.iocache.writebacks::total 106693 # number of writebacks +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 2000796 # number of replacements +system.l2c.tags.tagsinuse 65236.747854 # Cycle average of tags in use +system.l2c.tags.total_refs 5872089 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 2062236 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.847438 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 458916500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 10773.265369 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 57.425728 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 60.472796 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3088.117960 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 16913.790714 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 343.005231 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 383.707168 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2970.710524 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 30646.252365 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.164387 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000876 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000923 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.047121 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.258084 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005234 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.005855 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.045329 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.467625 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995434 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 236 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 61204 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 232 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3527 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4478 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52898 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.003601 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.933899 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 73224508 # Number of tag accesses +system.l2c.tags.data_accesses 73224508 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 2843148 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2843148 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 57335 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 51488 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 108823 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 8370 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 7752 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 16122 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 205747 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 172848 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 378595 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 13551 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5506 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 436242 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 735903 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 12336 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4370 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 421904 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 692405 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 2322217 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 112000 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 99469 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 211469 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 13551 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 5506 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 436242 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 941650 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 12336 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4370 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 421904 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 865253 # number of demand (read+write) hits +system.l2c.demand_hits::total 2700812 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 13551 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 5506 # number of overall hits +system.l2c.overall_hits::cpu0.inst 436242 # number of overall hits +system.l2c.overall_hits::cpu0.data 941650 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 12336 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 4370 # number of overall hits +system.l2c.overall_hits::cpu1.inst 421904 # number of overall hits +system.l2c.overall_hits::cpu1.data 865253 # number of overall hits +system.l2c.overall_hits::total 2700812 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 20153 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 22374 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 42527 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 465 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 952 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1417 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 404904 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 443379 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 848283 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2501 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1981 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 60987 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 188974 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3841 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3819 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 48931 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 203657 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 514691 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 441546 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu1.data 132806 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 574352 # number of InvalidateReq misses +system.l2c.demand_misses::cpu0.dtb.walker 2501 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1981 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 60987 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 593878 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3841 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 3819 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 48931 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 647036 # number of demand (read+write) misses +system.l2c.demand_misses::total 1362974 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 2501 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1981 # number of overall misses +system.l2c.overall_misses::cpu0.inst 60987 # number of overall misses +system.l2c.overall_misses::cpu0.data 593878 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3841 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 3819 # number of overall misses +system.l2c.overall_misses::cpu1.inst 48931 # number of overall misses +system.l2c.overall_misses::cpu1.data 647036 # number of overall misses +system.l2c.overall_misses::total 1362974 # number of overall misses +system.l2c.WritebackDirty_accesses::writebacks 2843148 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 2843148 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 77488 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 73862 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 151350 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 8835 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 8704 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 17539 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 610651 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 616227 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 1226878 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 16052 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7487 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 497229 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 924877 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 16177 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 8189 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 470835 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 896062 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 2836908 # number of ReadSharedReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu0.data 553546 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu1.data 232275 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::total 785821 # number of InvalidateReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 16052 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 7487 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 497229 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1535528 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 16177 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 8189 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 470835 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 1512289 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 4063786 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 16052 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 7487 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 497229 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1535528 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 16177 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 8189 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 470835 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 1512289 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 4063786 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.260079 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.302916 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.280984 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.052632 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.109375 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.080791 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.663069 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.719506 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.691416 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.155806 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.264592 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.122654 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.204323 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.237436 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.466357 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.103924 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.227280 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.181427 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.797668 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu1.data 0.571762 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.730894 # miss rate for InvalidateReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.155806 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.264592 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.122654 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.386758 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.237436 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.466357 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.103924 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.427852 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.335395 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.155806 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.264592 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.122654 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.386758 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.237436 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.466357 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.103924 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.427852 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.335395 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 1489052 # number of writebacks -system.l2c.writebacks::total 1489052 # number of writebacks -system.membus.snoop_filter.tot_requests 4378272 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2451994 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3422 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.writebacks::writebacks 1557006 # number of writebacks +system.l2c.writebacks::total 1557006 # number of writebacks +system.membus.snoop_filter.tot_requests 4511574 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2519656 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3180 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 82126 # Transaction distribution -system.membus.trans_dist::ReadResp 602482 # Transaction distribution -system.membus.trans_dist::WriteReq 38798 # Transaction distribution -system.membus.trans_dist::WriteResp 38798 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1595746 # Transaction distribution -system.membus.trans_dist::CleanEvict 267406 # Transaction distribution -system.membus.trans_dist::UpgradeReq 230305 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 288781 # Transaction distribution -system.membus.trans_dist::UpgradeResp 46602 # Transaction distribution -system.membus.trans_dist::ReadExReq 791817 # Transaction distribution -system.membus.trans_dist::ReadExResp 788064 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 520356 # Transaction distribution -system.membus.trans_dist::InvalidateReq 683860 # Transaction distribution -system.membus.trans_dist::InvalidateResp 675461 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122564 # Packet count per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 43614 # Transaction distribution +system.membus.trans_dist::ReadResp 567214 # Transaction distribution +system.membus.trans_dist::WriteReq 38678 # Transaction distribution +system.membus.trans_dist::WriteResp 38678 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1663699 # Transaction distribution +system.membus.trans_dist::CleanEvict 266504 # Transaction distribution +system.membus.trans_dist::UpgradeReq 223308 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 295373 # Transaction distribution +system.membus.trans_dist::UpgradeResp 46773 # Transaction distribution +system.membus.trans_dist::ReadExReq 849453 # Transaction distribution +system.membus.trans_dist::ReadExResp 845457 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 523600 # Transaction distribution +system.membus.trans_dist::InvalidateReq 689636 # Transaction distribution +system.membus.trans_dist::InvalidateResp 681080 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122236 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27546 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6153530 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 6303732 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346870 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 346870 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6650602 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155671 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27410 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6276469 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 6426207 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346860 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 346860 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6773067 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155343 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55092 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 178661596 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 178872563 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7398784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7398784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 186271347 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54820 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 186738012 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 186948379 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7398528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7398528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 194346907 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 4499195 # Request fanout histogram -system.membus.snoop_fanout::mean 0.007389 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.085643 # Request fanout histogram +system.membus.snoop_fanout::samples 4593865 # Request fanout histogram +system.membus.snoop_fanout::mean 0.007098 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.083952 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4465949 99.26% 99.26% # Request fanout histogram -system.membus.snoop_fanout::1 33246 0.74% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4561256 99.29% 99.29% # Request fanout histogram +system.membus.snoop_fanout::1 32609 0.71% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4499195 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.membus.snoop_fanout::total 4593865 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1654,68 +1647,68 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 11103133 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5636149 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1803428 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 289976 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 265298 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 24678 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 82128 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 3548294 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38798 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38798 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 2764082 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1999311 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 334418 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 305075 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 639493 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1358165 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1358165 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 3466166 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 875913 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 875913 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9373855 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8310864 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17684719 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 252267457 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 233795714 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 486063171 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1971827 # Total snoops (count) -system.toL2Bus.snoopTraffic 95347072 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 13179862 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.305132 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.464512 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 11315905 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5737208 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1831359 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 298423 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 272858 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 25565 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47256222864000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 43616 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3567484 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38678 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38678 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 2843148 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2033600 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 329302 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 311495 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 640797 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1403084 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1403084 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 3523868 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 871405 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 871405 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9542040 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8377604 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17919644 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 260882877 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 236654062 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 497536939 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2048171 # Total snoops (count) +system.toL2Bus.snoopTraffic 99695936 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 13430913 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.303362 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.463832 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 9182942 69.67% 69.67% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3972242 30.14% 99.81% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 24678 0.19% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 9382052 69.85% 69.85% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 4023296 29.96% 99.81% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 25565 0.19% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 13179862 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 13430913 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt index 203bf8cf0..81cebbb77 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt @@ -1,58 +1,58 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.548252 # Number of seconds simulated -sim_ticks 51548252400500 # Number of ticks simulated -final_tick 51548252400500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.071102 # Number of seconds simulated +sim_ticks 51071102402000 # Number of ticks simulated +final_tick 51071102402000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1717705 # Simulator instruction rate (inst/s) -host_op_rate 1880520 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48787200192 # Simulator tick rate (ticks/s) -host_mem_usage 679528 # Number of bytes of host memory used -host_seconds 1056.59 # Real time elapsed on the host -sim_insts 1814916572 # Number of instructions simulated -sim_ops 1986945286 # Number of ops (including micro ops) simulated +host_inst_rate 1747137 # Simulator instruction rate (inst/s) +host_op_rate 2084338 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 95484785421 # Simulator tick rate (ticks/s) +host_mem_usage 679432 # Number of bytes of host memory used +host_seconds 534.86 # Real time elapsed on the host +sim_insts 934475925 # Number of instructions simulated +sim_ops 1114831373 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 388608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 367808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5292340 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 73326152 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 442368 # Number of bytes read from this memory -system.physmem.bytes_read::total 79817276 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5292340 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5292340 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 101858624 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 487168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 439168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5588020 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 87025992 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 439360 # Number of bytes read from this memory +system.physmem.bytes_read::total 93979708 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5588020 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5588020 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 115462912 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 101879204 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 6072 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5747 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 123100 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1145734 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6912 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1287565 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1591541 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 115483492 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 7612 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6862 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 91720 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1359794 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6865 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1472853 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1804108 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1594114 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 7539 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 7135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 102668 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1422476 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8582 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1548399 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 102668 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 102668 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1975986 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1976385 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1975986 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 7539 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 7135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 102668 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1422875 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8582 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3524784 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.physmem.num_writes::total 1806681 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 9539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 8599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 109416 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1704016 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8603 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1840174 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 109416 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 109416 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2260827 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2261230 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2260827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 9539 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 8599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 109416 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1704419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8603 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4101404 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -69,9 +69,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -79,7 +79,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -109,47 +109,47 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 267664 # Table walker walks requested -system.cpu.dtb.walker.walksLong 267664 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walkWaitTime::samples 267664 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 267664 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 267664 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 206672 89.75% 89.75% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 23595 10.25% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 230267 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 267664 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 297729 # Table walker walks requested +system.cpu.dtb.walker.walksLong 297729 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walkWaitTime::samples 297729 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 297729 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 297729 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walksPending::samples 3646000 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 3646000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 3646000 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 228847 88.79% 88.79% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 28897 11.21% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 257744 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 297729 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 267664 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 230267 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 297729 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 257744 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 230267 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 497931 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 257744 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 555473 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 421603994 # DTB read hits -system.cpu.dtb.read_misses 196270 # DTB read misses -system.cpu.dtb.write_hits 167651282 # DTB write hits -system.cpu.dtb.write_misses 71394 # DTB write misses +system.cpu.dtb.read_hits 192113611 # DTB read hits +system.cpu.dtb.read_misses 218086 # DTB read misses +system.cpu.dtb.write_hits 176013555 # DTB write hits +system.cpu.dtb.write_misses 79643 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 49773 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 81418 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb_mva_asid 53573 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1171 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 85167 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 9097 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 10256 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 21656 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 421800264 # DTB read accesses -system.cpu.dtb.write_accesses 167722676 # DTB write accesses +system.cpu.dtb.perms_faults 22356 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 192331697 # DTB read accesses +system.cpu.dtb.write_accesses 176093198 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 589255276 # DTB hits -system.cpu.dtb.misses 267664 # DTB misses -system.cpu.dtb.accesses 589522940 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 368127166 # DTB hits +system.cpu.dtb.misses 297729 # DTB misses +system.cpu.dtb.accesses 368424895 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -179,470 +179,469 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 126885 # Table walker walks requested -system.cpu.itb.walker.walksLong 126885 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walkWaitTime::samples 126885 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 126885 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 126885 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 113624 99.02% 99.02% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1122 0.98% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 114746 # Table walker page sizes translated +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 128928 # Table walker walks requested +system.cpu.itb.walker.walksLong 128928 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walkWaitTime::samples 128928 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 128928 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 128928 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walksPending::samples 3644500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 3644500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 3644500 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 115252 99.04% 99.04% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1122 0.96% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 116374 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126885 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 126885 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 128928 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 128928 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114746 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 114746 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 241631 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 1815394284 # ITB inst hits -system.cpu.itb.inst_misses 126885 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 116374 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 116374 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 245302 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 935011975 # ITB inst hits +system.cpu.itb.inst_misses 128928 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 49773 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 57333 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 53573 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1171 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 59711 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 1815521169 # ITB inst accesses -system.cpu.itb.hits 1815394284 # DTB hits -system.cpu.itb.misses 126885 # DTB misses -system.cpu.itb.accesses 1815521169 # DTB accesses -system.cpu.numPwrStateTransitions 33574 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 16787 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3011524161.053136 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 59680214632.955681 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 7463 44.46% 44.46% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9289 55.33% 99.79% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 935140903 # ITB inst accesses +system.cpu.itb.hits 935011975 # DTB hits +system.cpu.itb.misses 128928 # DTB misses +system.cpu.itb.accesses 935140903 # DTB accesses +system.cpu.numPwrStateTransitions 33906 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 16953 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 2979611399.652038 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 59761128093.250465 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 7631 45.01% 45.01% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9287 54.78% 99.79% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 3 0.02% 99.87% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::3.5e+11-4e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 3 0.02% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::9.5e+11-1e+12 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 1988782948204 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 16787 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 993796308901 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50554456091599 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 103096521589 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::max_value 1988782908468 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 16953 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 557750343699 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50513352058301 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 102142221758 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16787 # number of quiesce instructions executed -system.cpu.committedInsts 1814916572 # Number of instructions committed -system.cpu.committedOps 1986945286 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1711962456 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 884728 # Number of float alu accesses -system.cpu.num_func_calls 56754008 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 449117161 # number of instructions that are conditional controls -system.cpu.num_int_insts 1711962456 # number of integer instructions -system.cpu.num_fp_insts 884728 # number of float instructions -system.cpu.num_int_register_reads 2333816547 # number of times the integer registers were read -system.cpu.num_int_register_writes 1316284167 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1424283 # number of times the floating registers were read -system.cpu.num_fp_register_writes 753044 # number of times the floating registers were written -system.cpu.num_cc_register_reads 621173289 # number of times the CC registers were read -system.cpu.num_cc_register_writes 620585461 # number of times the CC registers were written -system.cpu.num_mem_refs 589476099 # number of memory refs -system.cpu.num_load_insts 421772480 # Number of load instructions -system.cpu.num_store_insts 167703619 # Number of store instructions -system.cpu.num_idle_cycles 101108928647.540985 # Number of idle cycles -system.cpu.num_busy_cycles 1987592941.459016 # Number of busy cycles -system.cpu.not_idle_fraction 0.019279 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.980721 # Percentage of idle cycles -system.cpu.Branches 576475057 # Number of branches fetched +system.cpu.kern.inst.quiesce 16953 # number of quiesce instructions executed +system.cpu.committedInsts 934475925 # Number of instructions committed +system.cpu.committedOps 1114831373 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1036744712 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 878021 # Number of float alu accesses +system.cpu.num_func_calls 59056085 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 135851428 # number of instructions that are conditional controls +system.cpu.num_int_insts 1036744712 # number of integer instructions +system.cpu.num_fp_insts 878021 # number of float instructions +system.cpu.num_int_register_reads 1380118426 # number of times the integer registers were read +system.cpu.num_int_register_writes 809399347 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1413239 # number of times the floating registers were read +system.cpu.num_fp_register_writes 747664 # number of times the floating registers were written +system.cpu.num_cc_register_reads 207723168 # number of times the CC registers were read +system.cpu.num_cc_register_writes 207152857 # number of times the CC registers were written +system.cpu.num_mem_refs 368379179 # number of memory refs +system.cpu.num_load_insts 192305014 # Number of load instructions +system.cpu.num_store_insts 176074165 # Number of store instructions +system.cpu.num_idle_cycles 101026720885.444443 # Number of idle cycles +system.cpu.num_busy_cycles 1115500872.555553 # Number of busy cycles +system.cpu.not_idle_fraction 0.010921 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.989079 # Percentage of idle cycles +system.cpu.Branches 206489174 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 1395540402 70.21% 70.21% # Class of executed instruction -system.cpu.op_class::IntMult 2356131 0.12% 70.33% # Class of executed instruction -system.cpu.op_class::IntDiv 100370 0.01% 70.34% # Class of executed instruction -system.cpu.op_class::FloatAdd 8 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatCmp 13 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatCvt 21 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatMisc 107824 0.01% 70.34% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::MemRead 421659035 21.21% 91.56% # Class of executed instruction -system.cpu.op_class::MemWrite 167040202 8.40% 99.96% # Class of executed instruction -system.cpu.op_class::FloatMemRead 113445 0.01% 99.97% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 663417 0.03% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 744480688 66.74% 66.74% # Class of executed instruction +system.cpu.op_class::IntMult 2418794 0.22% 66.96% # Class of executed instruction +system.cpu.op_class::IntDiv 103036 0.01% 66.97% # Class of executed instruction +system.cpu.op_class::FloatAdd 8 0.00% 66.97% # Class of executed instruction +system.cpu.op_class::FloatCmp 13 0.00% 66.97% # Class of executed instruction +system.cpu.op_class::FloatCvt 21 0.00% 66.97% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 66.97% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 66.97% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 66.97% # Class of executed instruction +system.cpu.op_class::FloatMisc 106782 0.01% 66.98% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.98% # Class of executed instruction +system.cpu.op_class::MemRead 192192210 17.23% 84.21% # Class of executed instruction +system.cpu.op_class::MemWrite 175415772 15.73% 99.93% # Class of executed instruction +system.cpu.op_class::FloatMemRead 112804 0.01% 99.94% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 658393 0.06% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1987580869 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 11603445 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.999721 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 577795083 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11603957 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 49.792936 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.999721 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy +system.cpu.op_class::total 1115488522 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 12292096 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.999911 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 356005277 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 12292608 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 28.960923 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 13850500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.999911 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 1.000000 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 1.000000 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 203 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 2369200172 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 2369200172 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 409181313 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 409181313 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 158964390 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158964390 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 425694 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 425694 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 336647 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 336647 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4299455 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4299455 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4553147 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4553147 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 568482350 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 568482350 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 568908044 # number of overall hits -system.cpu.dcache.overall_hits::total 568908044 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 5993326 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 5993326 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2556217 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2556217 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1586747 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1586747 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1246619 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1246619 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 255495 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 255495 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1485484203 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1485484203 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 178905891 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 178905891 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 166844782 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 166844782 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 437201 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 437201 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 338801 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 338801 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4589501 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4589501 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4852460 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4852460 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 346089474 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 346089474 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 346526675 # number of overall hits +system.cpu.dcache.overall_hits::total 346526675 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6353340 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6353340 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2735988 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2735988 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1721890 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1721890 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1253245 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1253245 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 264796 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 264796 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 9796162 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9796162 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 11382909 # number of overall misses -system.cpu.dcache.overall_misses::total 11382909 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 415174639 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 415174639 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 161520607 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 161520607 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2012441 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2012441 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583266 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1583266 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4554950 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4554950 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4553148 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4553148 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 578278512 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 578278512 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 580290953 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 580290953 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014436 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.014436 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015826 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015826 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788469 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.788469 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787372 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.787372 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.056092 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.056092 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 10342573 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 10342573 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 12064463 # number of overall misses +system.cpu.dcache.overall_misses::total 12064463 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 185259231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 185259231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 169580770 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 169580770 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2159091 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2159091 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1592046 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1592046 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4854297 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4854297 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4852461 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4852461 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 356432047 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 356432047 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 358591138 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 358591138 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.034294 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.034294 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.016134 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.016134 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.797507 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.797507 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787191 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.787191 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.054549 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.054549 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016940 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016940 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.019616 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.019616 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.029017 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.029017 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.033644 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.033644 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 8939334 # number of writebacks -system.cpu.dcache.writebacks::total 8939334 # number of writebacks -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 14289332 # number of replacements -system.cpu.icache.tags.tagsinuse 511.984730 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1801219181 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 14289844 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 126.048904 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6061932500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.984730 # Average occupied blocks per requestor +system.cpu.dcache.writebacks::writebacks 9441403 # number of writebacks +system.cpu.dcache.writebacks::total 9441403 # number of writebacks +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 14554443 # number of replacements +system.cpu.icache.tags.tagsinuse 511.984790 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 920573389 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 14554955 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 63.248110 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6040365000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.984790 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 190 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1829798879 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1829798879 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1801219181 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1801219181 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1801219181 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1801219181 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1801219181 # number of overall hits -system.cpu.icache.overall_hits::total 1801219181 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14289849 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14289849 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14289849 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14289849 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14289849 # number of overall misses -system.cpu.icache.overall_misses::total 14289849 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 1815509030 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1815509030 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1815509030 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1815509030 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1815509030 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1815509030 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007871 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007871 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007871 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007871 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007871 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007871 # miss rate for overall accesses +system.cpu.icache.tags.tag_accesses 949683309 # Number of tag accesses +system.cpu.icache.tags.data_accesses 949683309 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 920573389 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 920573389 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 920573389 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 920573389 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 920573389 # number of overall hits +system.cpu.icache.overall_hits::total 920573389 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14554960 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14554960 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14554960 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14554960 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14554960 # number of overall misses +system.cpu.icache.overall_misses::total 14554960 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 935128349 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 935128349 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 935128349 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 935128349 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 935128349 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 935128349 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015565 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015565 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015565 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015565 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015565 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015565 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 14289332 # number of writebacks -system.cpu.icache.writebacks::total 14289332 # number of writebacks -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1684196 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65394.978455 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 49472483 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1746767 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 28.322314 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 395496000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9677.706964 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 426.448625 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 480.005287 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6101.422178 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48709.395401 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.147670 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006507 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007324 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.093100 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.743246 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997848 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 329 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62242 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 328 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1404 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5082 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55348 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.005020 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949738 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 422888423 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 422888423 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 482010 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 237204 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 719214 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 8939334 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 8939334 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 14287756 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 14287756 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 30651 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 30651 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1695121 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1695121 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14209837 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 14209837 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7515311 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 7515311 # number of ReadSharedReq hits -system.cpu.l2cache.InvalidateReq_hits::cpu.data 704740 # number of InvalidateReq hits -system.cpu.l2cache.InvalidateReq_hits::total 704740 # number of InvalidateReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 482010 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 237204 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 14209837 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 9210432 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 24139483 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 482010 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 237204 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 14209837 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 9210432 # number of overall hits -system.cpu.l2cache.overall_hits::total 24139483 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6072 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5747 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 11819 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 3785 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 3785 # number of UpgradeReq misses +system.cpu.icache.writebacks::writebacks 14554443 # number of writebacks +system.cpu.icache.writebacks::total 14554443 # number of writebacks +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 1939529 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65410.509732 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 51207751 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2002275 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 25.574784 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 373950000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 9607.000136 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 373.212421 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 441.072045 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6073.861347 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48915.363784 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.146591 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005695 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006730 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.092680 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.746389 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998085 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 323 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 62423 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 323 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1416 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5058 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55500 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004929 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952499 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 439130926 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 439130926 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 564464 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 243894 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 808358 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 9441403 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 9441403 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 14552867 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 14552867 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 32762 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 32762 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1717134 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1717134 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14467928 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 14467928 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7961263 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 7961263 # number of ReadSharedReq hits +system.cpu.l2cache.InvalidateReq_hits::cpu.data 682418 # number of InvalidateReq hits +system.cpu.l2cache.InvalidateReq_hits::total 682418 # number of InvalidateReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 564464 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 243894 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 14467928 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 9678397 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 24954683 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 564464 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 243894 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 14467928 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 9678397 # number of overall hits +system.cpu.l2cache.overall_hits::total 24954683 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7612 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6862 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 14474 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 3878 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 3878 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 826660 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 826660 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 80012 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 80012 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 320257 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 320257 # number of ReadSharedReq misses -system.cpu.l2cache.InvalidateReq_misses::cpu.data 541879 # number of InvalidateReq misses -system.cpu.l2cache.InvalidateReq_misses::total 541879 # number of InvalidateReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 6072 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5747 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 80012 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1146917 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1238748 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 6072 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 5747 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 80012 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1146917 # number of overall misses -system.cpu.l2cache.overall_misses::total 1238748 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 488082 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 242951 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 731033 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 8939334 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 8939334 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 14287756 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 14287756 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 34436 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 34436 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 982214 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 982214 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 87032 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 87032 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 378763 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 378763 # number of ReadSharedReq misses +system.cpu.l2cache.InvalidateReq_misses::cpu.data 570827 # number of InvalidateReq misses +system.cpu.l2cache.InvalidateReq_misses::total 570827 # number of InvalidateReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 7612 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 6862 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 87032 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1360977 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1462483 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 7612 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 6862 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 87032 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1360977 # number of overall misses +system.cpu.l2cache.overall_misses::total 1462483 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 572076 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 250756 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 822832 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 9441403 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 9441403 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 14552867 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 14552867 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 36640 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 36640 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2521781 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2521781 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14289849 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 14289849 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7835568 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7835568 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1246619 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::total 1246619 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 488082 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 242951 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 14289849 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 10357349 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 25378231 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 488082 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 242951 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 14289849 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 10357349 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 25378231 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012441 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.023655 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016168 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.109914 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.109914 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2699348 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2699348 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14554960 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 14554960 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 8340026 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 8340026 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1253245 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::total 1253245 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 572076 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 250756 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 14554960 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 11039374 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 26417166 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 572076 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 250756 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 14554960 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 11039374 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 26417166 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.013306 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.027365 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.017590 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.105841 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.105841 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.327808 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.327808 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005599 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005599 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.040872 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.040872 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.434679 # miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::total 0.434679 # miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012441 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.023655 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005599 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.110735 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.048811 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012441 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.023655 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005599 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.110735 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.048811 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.363871 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.363871 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005980 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005980 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.045415 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.045415 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.455479 # miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.455479 # miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.013306 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.027365 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005980 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.123284 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.055361 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.013306 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.027365 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005980 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.123284 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.055361 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1484910 # number of writebacks -system.cpu.l2cache.writebacks::total 1484910 # number of writebacks -system.cpu.toL2Bus.snoop_filter.tot_requests 52410934 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 26517119 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1745 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2740 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2740 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.writebacks::writebacks 1697477 # number of writebacks +system.cpu.l2cache.writebacks::total 1697477 # number of writebacks +system.cpu.toL2Bus.snoop_filter.tot_requests 54350593 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 27503016 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1759 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2697 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2697 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1234221 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23359638 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8939334 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 14289332 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2664111 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 34436 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1286731 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 24181717 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 9441403 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 14554443 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2850693 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 36640 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 34437 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2521781 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2521781 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 14289849 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7835568 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1246619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1246619 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42955280 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35014647 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758514 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1556522 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 80284963 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1829240084 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1235177526 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3034056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6226088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 3073677754 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1724598 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 95094976 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 54812635 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.010876 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103719 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 36641 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2699348 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2699348 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 14554960 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 8340026 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1253245 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1253245 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43673813 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 37084586 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 770772 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1726308 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 83255479 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1863020692 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1310959042 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3083088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6905232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 3183968054 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1977015 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 108689536 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 57027218 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.010978 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.104200 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 54216500 98.91% 98.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 596135 1.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 56401167 98.90% 98.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 626051 1.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 54812635 # Request fanout histogram -system.iobus.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40253 # Transaction distribution -system.iobus.trans_dist::ReadResp 40253 # Transaction distribution -system.iobus.trans_dist::WriteReq 136515 # Transaction distribution -system.iobus.trans_dist::WriteResp 136515 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.snoop_fanout::total 57027218 # Request fanout histogram +system.iobus.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40168 # Transaction distribution +system.iobus.trans_dist::ReadResp 40168 # Transaction distribution +system.iobus.trans_dist::WriteReq 136429 # Transaction distribution +system.iobus.trans_dist::WriteResp 136429 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47254 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -655,13 +654,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230976 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230976 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122136 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230978 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230978 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353536 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353194 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47274 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -674,56 +673,56 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334336 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334336 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155266 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334344 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334344 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492032 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115470 # number of replacements -system.iocache.tags.tagsinuse 10.454534 # Cycle average of tags in use +system.iobus.pkt_size::total 7491696 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115471 # number of replacements +system.iocache.tags.tagsinuse 10.402763 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115486 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115487 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13082113307009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.524459 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.930076 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.220279 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433130 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653408 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13082091783509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.557357 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.845405 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.222335 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.427838 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.650173 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039749 # Number of tag accesses -system.iocache.tags.data_accesses 1039749 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039758 # Number of tag accesses +system.iocache.tags.data_accesses 1039758 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8824 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8861 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8825 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8862 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115488 # number of demand (read+write) misses -system.iocache.demand_misses::total 115528 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115489 # number of demand (read+write) misses +system.iocache.demand_misses::total 115529 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115488 # number of overall misses -system.iocache.overall_misses::total 115528 # number of overall misses +system.iocache.overall_misses::realview.ide 115489 # number of overall misses +system.iocache.overall_misses::total 115529 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8824 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8861 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8825 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8862 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115488 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115528 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115489 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115529 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115488 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115528 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115489 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115529 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -745,71 +744,71 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks -system.membus.snoop_filter.tot_requests 3698370 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1836830 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3132 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_requests 4206457 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2089632 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3012 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 76703 # Transaction distribution -system.membus.trans_dist::ReadResp 497652 # Transaction distribution -system.membus.trans_dist::WriteReq 33618 # Transaction distribution -system.membus.trans_dist::WriteResp 33618 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1591541 # Transaction distribution -system.membus.trans_dist::CleanEvict 206888 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4346 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 38191 # Transaction distribution +system.membus.trans_dist::ReadResp 527322 # Transaction distribution +system.membus.trans_dist::WriteReq 33519 # Transaction distribution +system.membus.trans_dist::WriteResp 33519 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1804108 # Transaction distribution +system.membus.trans_dist::CleanEvict 249631 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4439 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4347 # Transaction distribution -system.membus.trans_dist::ReadExReq 826102 # Transaction distribution -system.membus.trans_dist::ReadExResp 826102 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 420949 # Transaction distribution -system.membus.trans_dist::InvalidateReq 648543 # Transaction distribution -system.membus.trans_dist::InvalidateResp 648543 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 4440 # Transaction distribution +system.membus.trans_dist::ReadExReq 981656 # Transaction distribution +system.membus.trans_dist::ReadExResp 981656 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 489131 # Transaction distribution +system.membus.trans_dist::InvalidateReq 677491 # Transaction distribution +system.membus.trans_dist::InvalidateResp 677491 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122136 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6726 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5343163 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5472427 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346526 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 346526 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5818953 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6648 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6027224 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 6156066 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346529 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 346529 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6502595 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155266 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13452 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 174471520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 174640714 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391488 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7391488 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 182032202 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 202241248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 202409942 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391552 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7391552 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 209801494 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3808691 # Request fanout histogram -system.membus.snoop_fanout::mean 0.010569 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.102262 # Request fanout histogram +system.membus.snoop_fanout::samples 4278167 # Request fanout histogram +system.membus.snoop_fanout::mean 0.008735 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.093051 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3768436 98.94% 98.94% # Request fanout histogram -system.membus.snoop_fanout::1 40255 1.06% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4240798 99.13% 99.13% # Request fanout histogram +system.membus.snoop_fanout::1 37369 0.87% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3808691 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.membus.snoop_fanout::total 4278167 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -819,11 +818,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -852,28 +851,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51548252400500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51071102402000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index 529d7a06f..c24bc3993 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.405081 # Number of seconds simulated -sim_ticks 47405080882500 # Number of ticks simulated -final_tick 47405080882500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.401371 # Number of seconds simulated +sim_ticks 47401370587500 # Number of ticks simulated +final_tick 47401370587500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1071981 # Simulator instruction rate (inst/s) -host_op_rate 1260946 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57861452624 # Simulator tick rate (ticks/s) -host_mem_usage 765552 # Number of bytes of host memory used -host_seconds 819.29 # Real time elapsed on the host -sim_insts 878258906 # Number of instructions simulated -sim_ops 1033075205 # Number of ops (including micro ops) simulated +host_inst_rate 1122973 # Simulator instruction rate (inst/s) +host_op_rate 1337206 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65940331964 # Simulator tick rate (ticks/s) +host_mem_usage 757896 # Number of bytes of host memory used +host_seconds 718.85 # Real time elapsed on the host +sim_insts 807251718 # Number of instructions simulated +sim_ops 961253990 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 98944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 98688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3570996 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 13936584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 15336640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 134720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 134720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2530168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 9676304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 10811456 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 435904 # Number of bytes read from this memory -system.physmem.bytes_read::total 56765124 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3570996 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2530168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6101164 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 74743808 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 62784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 59776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2908084 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 11497800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 12850688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 108160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 115584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2943416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 9887760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 11019584 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 443392 # Number of bytes read from this memory +system.physmem.bytes_read::total 51897028 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2908084 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2943416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5851500 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70859904 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 74764392 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1546 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1542 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 96204 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 217772 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 239635 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2105 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2105 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 39622 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 151205 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 168929 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6811 # Number of read requests responded to by this memory -system.physmem.num_reads::total 927476 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1167872 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 70880488 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 981 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 934 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 49846 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 179666 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 200792 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1690 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1806 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 46079 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 154509 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 172181 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6928 # Number of read requests responded to by this memory +system.physmem.num_reads::total 815412 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1107186 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1170446 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2082 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 75329 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 293989 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 323523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 53373 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 204120 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 228065 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9195 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1197448 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 75329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 53373 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 128703 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1576705 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1109760 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 61350 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 242563 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 271104 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2282 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 62096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 208597 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 232474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9354 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1094842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 61350 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 62096 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 123446 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1494891 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1577139 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1576705 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2087 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2082 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 75329 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 294423 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 323523 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2842 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2842 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 53373 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 204120 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 228065 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9195 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2774587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 927476 # Number of read requests accepted -system.physmem.writeReqs 1170446 # Number of write requests accepted -system.physmem.readBursts 927476 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1170446 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 59335744 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 22720 # Total number of bytes read from write queue -system.physmem.bytesWritten 74761408 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 56765124 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 74764392 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 355 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2268 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1495326 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1494891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 61350 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 242997 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 271104 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2282 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 62096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 208597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 232474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9354 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2590168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 815412 # Number of read requests accepted +system.physmem.writeReqs 1109760 # Number of write requests accepted +system.physmem.readBursts 815412 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1109760 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 52162176 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 24192 # Total number of bytes read from write queue +system.physmem.bytesWritten 70877120 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 51897028 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 70880488 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 378 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2280 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 53525 # Per bank write bursts -system.physmem.perBankRdBursts::1 58700 # Per bank write bursts -system.physmem.perBankRdBursts::2 53136 # Per bank write bursts -system.physmem.perBankRdBursts::3 59915 # Per bank write bursts -system.physmem.perBankRdBursts::4 57558 # Per bank write bursts -system.physmem.perBankRdBursts::5 67025 # Per bank write bursts -system.physmem.perBankRdBursts::6 57593 # Per bank write bursts -system.physmem.perBankRdBursts::7 57551 # Per bank write bursts -system.physmem.perBankRdBursts::8 45941 # Per bank write bursts -system.physmem.perBankRdBursts::9 94599 # Per bank write bursts -system.physmem.perBankRdBursts::10 49635 # Per bank write bursts -system.physmem.perBankRdBursts::11 57294 # Per bank write bursts -system.physmem.perBankRdBursts::12 48522 # Per bank write bursts -system.physmem.perBankRdBursts::13 56965 # Per bank write bursts -system.physmem.perBankRdBursts::14 52794 # Per bank write bursts -system.physmem.perBankRdBursts::15 56368 # Per bank write bursts -system.physmem.perBankWrBursts::0 71875 # Per bank write bursts -system.physmem.perBankWrBursts::1 75753 # Per bank write bursts -system.physmem.perBankWrBursts::2 71549 # Per bank write bursts -system.physmem.perBankWrBursts::3 77042 # Per bank write bursts -system.physmem.perBankWrBursts::4 73392 # Per bank write bursts -system.physmem.perBankWrBursts::5 80022 # Per bank write bursts -system.physmem.perBankWrBursts::6 71461 # Per bank write bursts -system.physmem.perBankWrBursts::7 73088 # Per bank write bursts -system.physmem.perBankWrBursts::8 65465 # Per bank write bursts -system.physmem.perBankWrBursts::9 74249 # Per bank write bursts -system.physmem.perBankWrBursts::10 70475 # Per bank write bursts -system.physmem.perBankWrBursts::11 74236 # Per bank write bursts -system.physmem.perBankWrBursts::12 69250 # Per bank write bursts -system.physmem.perBankWrBursts::13 75271 # Per bank write bursts -system.physmem.perBankWrBursts::14 70641 # Per bank write bursts -system.physmem.perBankWrBursts::15 74378 # Per bank write bursts +system.physmem.perBankRdBursts::0 50443 # Per bank write bursts +system.physmem.perBankRdBursts::1 58279 # Per bank write bursts +system.physmem.perBankRdBursts::2 46176 # Per bank write bursts +system.physmem.perBankRdBursts::3 52637 # Per bank write bursts +system.physmem.perBankRdBursts::4 47826 # Per bank write bursts +system.physmem.perBankRdBursts::5 55648 # Per bank write bursts +system.physmem.perBankRdBursts::6 52176 # Per bank write bursts +system.physmem.perBankRdBursts::7 51274 # Per bank write bursts +system.physmem.perBankRdBursts::8 44248 # Per bank write bursts +system.physmem.perBankRdBursts::9 55412 # Per bank write bursts +system.physmem.perBankRdBursts::10 43487 # Per bank write bursts +system.physmem.perBankRdBursts::11 55151 # Per bank write bursts +system.physmem.perBankRdBursts::12 50800 # Per bank write bursts +system.physmem.perBankRdBursts::13 57431 # Per bank write bursts +system.physmem.perBankRdBursts::14 46539 # Per bank write bursts +system.physmem.perBankRdBursts::15 47507 # Per bank write bursts +system.physmem.perBankWrBursts::0 68734 # Per bank write bursts +system.physmem.perBankWrBursts::1 74075 # Per bank write bursts +system.physmem.perBankWrBursts::2 65910 # Per bank write bursts +system.physmem.perBankWrBursts::3 69531 # Per bank write bursts +system.physmem.perBankWrBursts::4 66080 # Per bank write bursts +system.physmem.perBankWrBursts::5 73115 # Per bank write bursts +system.physmem.perBankWrBursts::6 69817 # Per bank write bursts +system.physmem.perBankWrBursts::7 69743 # Per bank write bursts +system.physmem.perBankWrBursts::8 63555 # Per bank write bursts +system.physmem.perBankWrBursts::9 71485 # Per bank write bursts +system.physmem.perBankWrBursts::10 64662 # Per bank write bursts +system.physmem.perBankWrBursts::11 72406 # Per bank write bursts +system.physmem.perBankWrBursts::12 68380 # Per bank write bursts +system.physmem.perBankWrBursts::13 74722 # Per bank write bursts +system.physmem.perBankWrBursts::14 65945 # Per bank write bursts +system.physmem.perBankWrBursts::15 69295 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 399 # Number of times write queue was full causing retry -system.physmem.totGap 47405077592000 # Total gap between requests +system.physmem.numWrRetry 463 # Number of times write queue was full causing retry +system.physmem.totGap 47401367297000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 43195 # Read request sizes (log2) +system.physmem.readPktSize::2 4795 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 884251 # Read request sizes (log2) +system.physmem.readPktSize::6 810587 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1167872 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 648346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 87693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 41445 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 28689 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 25203 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 22073 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 18329 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15555 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2733 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1025 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 772 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 592 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 417 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 104 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1107186 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 559891 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 78604 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 37389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 30365 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 26588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 23379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 20454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 17072 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 14604 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2581 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1059 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 789 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 314 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 170 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 100 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -189,167 +189,189 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 28770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 36931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 48299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 54487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 63693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 65505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 67515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 70215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 70242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 73447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 75382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 72205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 70493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 71352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 75176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 68341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 65445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 1023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 921 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 928498 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 144.423393 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 98.327252 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 191.341879 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 616929 66.44% 66.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 189662 20.43% 86.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 44616 4.81% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20270 2.18% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 14755 1.59% 95.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9179 0.99% 96.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6168 0.66% 97.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5453 0.59% 97.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21466 2.31% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 928498 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60682 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 15.278254 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 130.725132 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 60680 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60682 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60682 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.250305 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.439777 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.504538 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 53685 88.47% 88.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 4623 7.62% 96.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 1219 2.01% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 192 0.32% 98.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 86 0.14% 98.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 66 0.11% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 562 0.93% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 118 0.19% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 38 0.06% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 2 0.00% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 5 0.01% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 14 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 2 0.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 28 0.05% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 15 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 6 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 5 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60682 # Writes before turning the bus around for reads -system.physmem.totQLat 46391884854 # Total ticks spent queuing -system.physmem.totMemAccLat 63775403604 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4635605000 # Total ticks spent in databus transfers -system.physmem.avgQLat 50038.65 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 27848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 46446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 51674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 57512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 59733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 63717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 66102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 66334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 69492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 71245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 67739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 66506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 67172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 70520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 64778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 61855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3835 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 864 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 626 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 783 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 881 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 1107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1057 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 862223 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 142.699715 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 97.984234 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 187.236614 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 572247 66.37% 66.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 178435 20.69% 87.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 41649 4.83% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 18745 2.17% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13461 1.56% 95.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8413 0.98% 96.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6049 0.70% 97.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5161 0.60% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 18063 2.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 862223 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 57012 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.295727 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 26.624569 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 57003 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 3 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 3 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1535 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5120-5375 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 57012 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 57012 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.424946 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.563445 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.850614 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 45452 79.72% 79.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 4610 8.09% 87.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 2793 4.90% 92.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 1774 3.11% 95.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 1007 1.77% 97.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 224 0.39% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 148 0.26% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 47 0.08% 98.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 57 0.10% 98.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 22 0.04% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 26 0.05% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 34 0.06% 98.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 476 0.83% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 79 0.14% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 57 0.10% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 65 0.11% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 45 0.08% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.00% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.01% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.00% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 12 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 4 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 16 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 7 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 4 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 5 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 3 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 9 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::252-255 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 57012 # Writes before turning the bus around for reads +system.physmem.totQLat 43191913053 # Total ticks spent queuing +system.physmem.totMemAccLat 58473800553 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4075170000 # Total ticks spent in databus transfers +system.physmem.avgQLat 52994.00 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 68788.65 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 71744.00 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.10 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.50 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.09 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.50 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.27 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.29 # Average write queue length when enqueuing -system.physmem.readRowHits 687053 # Number of row buffer hits during reads -system.physmem.writeRowHits 479716 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.11 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.07 # Row buffer hit rate for writes -system.physmem.avgGap 22596205.96 # Average gap between requests -system.physmem.pageHitRate 55.69 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3406258380 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1810469265 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3320121420 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3101630040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 41354208480.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 46841067270 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2207636640 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 80277254730 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 57514863840 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 11279816434935 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 11519667255870 # Total energy per rank (pJ) -system.physmem_0.averagePower 243.004907 # Core power per rank (mW) -system.physmem_0.totalIdleTime 47296565897576 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 3842888750 # Time in different power states -system.physmem_0.memoryStateTime::REF 17568968000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 46970746731500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 149777866049 # Time in different power states -system.physmem_0.memoryStateTime::ACT 87097852174 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 176046576027 # Time in different power states -system.physmem_1.actEnergy 3223224480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1713180645 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3299522520 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 2996097300 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 40281047040.000008 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 47571960030 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2174762400 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 74931048030 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 56612801280 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 11282749861635 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 11515570196190 # Total energy per rank (pJ) -system.physmem_1.averagePower 242.918480 # Core power per rank (mW) -system.physmem_1.totalIdleTime 47295055254584 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3757232201 # Time in different power states -system.physmem_1.memoryStateTime::REF 17114078000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 46983304269750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 147428799179 # Time in different power states -system.physmem_1.memoryStateTime::ACT 89154269965 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 164322233405 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing +system.physmem.readRowHits 599171 # Number of row buffer hits during reads +system.physmem.writeRowHits 461094 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.51 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.63 # Row buffer hit rate for writes +system.physmem.avgGap 24621886.93 # Average gap between requests +system.physmem.pageHitRate 55.15 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3125163720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1661060115 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2959237260 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 2907566100 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 39767208000.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 44841459390 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2203203840 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 73351636740 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 56747456160 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 11284217805975 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 11511799212150 # Total energy per rank (pJ) +system.physmem_0.averagePower 242.857940 # Core power per rank (mW) +system.physmem_0.totalIdleTime 47297258186903 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3926700752 # Time in different power states +system.physmem_0.memoryStateTime::REF 16898782000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 46988619115750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 147779602583 # Time in different power states +system.physmem_0.memoryStateTime::ACT 83286870095 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 160859516320 # Time in different power states +system.physmem_1.actEnergy 3031115640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1611076170 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2860105500 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 2873349000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 40284120240.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 45341107710 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2193321120 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 73446933900 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 57703512480 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 11283525763155 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 11512888807215 # Total energy per rank (pJ) +system.physmem_1.averagePower 242.880926 # Core power per rank (mW) +system.physmem_1.totalIdleTime 47296183842356 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3879016799 # Time in different power states +system.physmem_1.memoryStateTime::REF 17119770000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 46984848194500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 150269925291 # Time in different power states +system.physmem_1.memoryStateTime::ACT 84186543595 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 161067137315 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -376,9 +398,9 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -386,7 +408,7 @@ system.cf0.dma_write_full_pages 1667 # Nu system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -416,72 +438,70 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 105104 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 105104 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9446 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 80223 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 26 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 105078 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 0.247435 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 80.207956 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-2047 105077 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 92556 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 92556 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8240 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 69143 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 11 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 92545 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 0.280944 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 85.466687 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-2047 92544 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 105078 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 89695 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 23784.720441 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 21979.926785 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 16790.109220 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 88715 98.91% 98.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 727 0.81% 99.72% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 132 0.15% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 44 0.05% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 40 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 12 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkWaitTime::total 92545 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 77394 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 23265.414632 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 21722.582011 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 14143.873172 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 76797 99.23% 99.23% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 427 0.55% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 102 0.13% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 27 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 20 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 6 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 89695 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples -4516142684 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.024301 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 109748704 -2.43% -2.43% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 -4625891388 102.43% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total -4516142684 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 80223 89.47% 89.47% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 9446 10.53% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 89669 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 105104 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 77394 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 6740631600 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.619851 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.485423 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 2562444572 38.01% 38.01% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 4178187028 61.99% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 6740631600 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 69143 89.35% 89.35% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 8240 10.65% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 77383 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 92556 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 105104 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 89669 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 92556 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 77383 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 89669 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 194773 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 77383 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 169939 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 85250979 # DTB read hits -system.cpu0.dtb.read_misses 79026 # DTB read misses -system.cpu0.dtb.write_hits 77401552 # DTB write hits -system.cpu0.dtb.write_misses 26078 # DTB write misses +system.cpu0.dtb.read_hits 77415423 # DTB read hits +system.cpu0.dtb.read_misses 69730 # DTB read misses +system.cpu0.dtb.write_hits 70114940 # DTB write hits +system.cpu0.dtb.write_misses 22826 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 35795 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 40011 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1026 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 34306 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4355 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 3960 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 8965 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 85330005 # DTB read accesses -system.cpu0.dtb.write_accesses 77427630 # DTB write accesses +system.cpu0.dtb.perms_faults 8638 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 77485153 # DTB read accesses +system.cpu0.dtb.write_accesses 70137766 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 162652531 # DTB hits -system.cpu0.dtb.misses 105104 # DTB misses -system.cpu0.dtb.accesses 162757635 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 147530363 # DTB hits +system.cpu0.dtb.misses 92556 # DTB misses +system.cpu0.dtb.accesses 147622919 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -511,759 +531,760 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 55600 # Table walker walks requested -system.cpu0.itb.walker.walksLong 55600 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 619 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 49488 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 55600 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 55600 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 55600 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 50107 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 25482.068374 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23271.243255 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 20741.366870 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 49151 98.09% 98.09% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 657 1.31% 99.40% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 169 0.34% 99.74% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 55 0.11% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 41 0.08% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 17 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 10 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 50107 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 14842204 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 14842204 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 14842204 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 49488 98.76% 98.76% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 619 1.24% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 50107 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 51144 # Table walker walks requested +system.cpu0.itb.walker.walksLong 51144 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 535 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 45125 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 51144 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 51144 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 51144 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 45660 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 24927.069645 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23080.556454 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 20288.256560 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 45087 98.75% 98.75% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 348 0.76% 99.51% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 137 0.30% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 34 0.07% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 20 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 10 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 2 0.00% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 16 0.04% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::655360-720895 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 45660 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 618561500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 618561500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 618561500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 45125 98.83% 98.83% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 535 1.17% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 45660 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 55600 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 55600 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 51144 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 51144 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50107 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 50107 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 105707 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 455710659 # ITB inst hits -system.cpu0.itb.inst_misses 55600 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 45660 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 45660 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 96804 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 385005651 # ITB inst hits +system.cpu0.itb.inst_misses 51144 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 25367 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 40011 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1026 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 24319 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 455766259 # ITB inst accesses -system.cpu0.itb.hits 455710659 # DTB hits -system.cpu0.itb.misses 55600 # DTB misses -system.cpu0.itb.accesses 455766259 # DTB accesses -system.cpu0.numPwrStateTransitions 25961 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 12981 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 3608162218.077806 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 66802602989.523827 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3144 24.22% 24.22% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 9807 75.55% 99.77% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.78% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.78% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.81% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 18 0.14% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 1988778266744 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 12981 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 567527129632 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 46837553752868 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 94809604801 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 385056795 # ITB inst accesses +system.cpu0.itb.hits 385005651 # DTB hits +system.cpu0.itb.misses 51144 # DTB misses +system.cpu0.itb.accesses 385056795 # DTB accesses +system.cpu0.numPwrStateTransitions 8306 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 4153 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 11295325194.838190 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 176339050181.920959 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 2776 66.84% 66.84% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 1353 32.58% 99.42% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 6 0.14% 99.57% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.59% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.61% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.64% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.66% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.69% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 12 0.29% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 6953821743500 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 4153 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 491885053337 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46909485534163 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 94802741175 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 12981 # number of quiesce instructions executed -system.cpu0.committedInsts 455440444 # Number of instructions committed -system.cpu0.committedOps 534258155 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 490602455 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 409464 # Number of float alu accesses -system.cpu0.num_func_calls 27345084 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 69133268 # number of instructions that are conditional controls -system.cpu0.num_int_insts 490602455 # number of integer instructions -system.cpu0.num_fp_insts 409464 # number of float instructions -system.cpu0.num_int_register_reads 709813202 # number of times the integer registers were read -system.cpu0.num_int_register_writes 389013737 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 678261 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 309808 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 119533818 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 119119815 # number of times the CC registers were written -system.cpu0.num_mem_refs 162644052 # number of memory refs -system.cpu0.num_load_insts 85246888 # Number of load instructions -system.cpu0.num_store_insts 77397164 # Number of store instructions -system.cpu0.num_idle_cycles 93674557209.632675 # Number of idle cycles -system.cpu0.num_busy_cycles 1135047591.367321 # Number of busy cycles -system.cpu0.not_idle_fraction 0.011972 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.988028 # Percentage of idle cycles -system.cpu0.Branches 101837898 # Number of branches fetched +system.cpu0.kern.inst.quiesce 4153 # number of quiesce instructions executed +system.cpu0.committedInsts 384730653 # Number of instructions committed +system.cpu0.committedOps 456411878 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 424236423 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 341428 # Number of float alu accesses +system.cpu0.num_func_calls 24795410 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 55287954 # number of instructions that are conditional controls +system.cpu0.num_int_insts 424236423 # number of integer instructions +system.cpu0.num_fp_insts 341428 # number of float instructions +system.cpu0.num_int_register_reads 565685630 # number of times the integer registers were read +system.cpu0.num_int_register_writes 332181203 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 574384 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 236428 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 85999446 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 85681176 # number of times the CC registers were written +system.cpu0.num_mem_refs 147523428 # number of memory refs +system.cpu0.num_load_insts 77412307 # Number of load instructions +system.cpu0.num_store_insts 70111121 # Number of store instructions +system.cpu0.num_idle_cycles 93818971068.324020 # Number of idle cycles +system.cpu0.num_busy_cycles 983770106.675979 # Number of busy cycles +system.cpu0.not_idle_fraction 0.010377 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.989623 # Percentage of idle cycles +system.cpu0.Branches 84896632 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 370653040 69.34% 69.34% # Class of executed instruction -system.cpu0.op_class::IntMult 1173518 0.22% 69.56% # Class of executed instruction -system.cpu0.op_class::IntDiv 58988 0.01% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatMultAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatMisc 41897 0.01% 69.57% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::MemRead 85199674 15.94% 85.51% # Class of executed instruction -system.cpu0.op_class::MemWrite 77076811 14.42% 99.93% # Class of executed instruction -system.cpu0.op_class::FloatMemRead 47214 0.01% 99.94% # Class of executed instruction -system.cpu0.op_class::FloatMemWrite 320353 0.06% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 307975543 67.44% 67.44% # Class of executed instruction +system.cpu0.op_class::IntMult 1108929 0.24% 67.68% # Class of executed instruction +system.cpu0.op_class::IntDiv 55110 0.01% 67.69% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.69% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.69% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.69% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.69% # Class of executed instruction +system.cpu0.op_class::FloatMultAcc 0 0.00% 67.69% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.69% # Class of executed instruction +system.cpu0.op_class::FloatMisc 28590 0.01% 67.70% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.70% # Class of executed instruction +system.cpu0.op_class::MemRead 77373487 16.94% 84.64% # Class of executed instruction +system.cpu0.op_class::MemWrite 69837103 15.29% 99.93% # Class of executed instruction +system.cpu0.op_class::FloatMemRead 38820 0.01% 99.94% # Class of executed instruction +system.cpu0.op_class::FloatMemWrite 274018 0.06% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 534571495 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 5548235 # number of replacements -system.cpu0.dcache.tags.tagsinuse 508.308001 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 156839853 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5548600 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.266563 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 4328406000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.308001 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992789 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.992789 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 330814481 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 330814481 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 79405965 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 79405965 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 72971377 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 72971377 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 204972 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 204972 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 263219 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 263219 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1813440 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1813440 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1787735 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1787735 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 152640561 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 152640561 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 152845533 # number of overall hits -system.cpu0.dcache.overall_hits::total 152845533 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3006341 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3006341 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1360477 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1360477 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 626311 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 626311 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 794287 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 794287 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 164142 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 164142 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 188530 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 188530 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5161105 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5161105 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5787416 # number of overall misses -system.cpu0.dcache.overall_misses::total 5787416 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 47850868000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 47850868000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29377875000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 29377875000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25259415500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 25259415500 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2486803500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2486803500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4498365000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4498365000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2057500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2057500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 102488158500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 102488158500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 102488158500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 102488158500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 82412306 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 82412306 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 74331854 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 74331854 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 831283 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 831283 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1057506 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1057506 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1977582 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1977582 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1976265 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1976265 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 157801666 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 157801666 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 158632949 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 158632949 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036479 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036479 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018303 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018303 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.753427 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.753427 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.751095 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.751095 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083001 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083001 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095397 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095397 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032706 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.032706 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036483 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.036483 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15916.646847 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15916.646847 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21593.804967 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 21593.804967 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 31801.370915 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 31801.370915 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15150.318017 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15150.318017 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23860.207924 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23860.207924 # average StoreCondReq miss latency +system.cpu0.op_class::total 456691600 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 5013046 # number of replacements +system.cpu0.dcache.tags.tagsinuse 470.143979 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 142293396 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5013556 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.381731 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 637122000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 470.143979 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.918250 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.918250 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 299 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 300094424 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 300094424 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 72133805 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 72133805 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 66092358 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 66092358 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186275 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 186275 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 227046 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 227046 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1654353 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1654353 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1603859 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1603859 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 138453209 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 138453209 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 138639484 # number of overall hits +system.cpu0.dcache.overall_hits::total 138639484 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2704079 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 2704079 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1255388 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1255388 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 579222 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 579222 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 722220 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 722220 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 141818 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 141818 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 191065 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 191065 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4681687 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4681687 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5260909 # number of overall misses +system.cpu0.dcache.overall_misses::total 5260909 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41586194000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 41586194000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 27254591500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 27254591500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 23833661500 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 23833661500 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2088985000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2088985000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4536311000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4536311000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2828500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2828500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 92674447000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 92674447000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 92674447000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 92674447000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 74837884 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 74837884 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 67347746 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 67347746 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 765497 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 765497 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 949266 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 949266 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1796171 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1796171 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1794924 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1794924 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 143134896 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 143134896 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 143900393 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 143900393 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036132 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036132 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018640 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018640 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.756661 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.756661 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760819 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760819 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.078956 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.078956 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.106447 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.106447 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032708 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.032708 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036559 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.036559 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15379.060301 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15379.060301 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21710.094011 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 21710.094011 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33000.555925 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33000.555925 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14730.041321 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14730.041321 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23742.239552 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23742.239552 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19857.793728 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19857.793728 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17708.794132 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17708.794132 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19795.096725 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19795.096725 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17615.671930 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17615.671930 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 5548235 # number of writebacks -system.cpu0.dcache.writebacks::total 5548235 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 26826 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 26826 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21220 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21220 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43038 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43038 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 48046 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 48046 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 48046 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 48046 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2979515 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 2979515 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1339257 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1339257 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 624730 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 624730 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 794287 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 794287 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 121104 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 121104 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 188530 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 188530 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5113059 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5113059 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5737789 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5737789 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29828 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29828 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 29359 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 29359 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 59187 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 59187 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43367868500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43367868500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27478579500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27478579500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14655261000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14655261000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24465128500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24465128500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1605767000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1605767000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4309885000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4309885000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2007500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2007500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 95311576500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 95311576500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 109966837500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 109966837500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5687970000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5687970000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5687970000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5687970000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036154 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036154 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018017 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018017 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.751525 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.751525 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.751095 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.751095 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061238 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061238 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095397 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095397 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032402 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032402 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036170 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.036170 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14555.344914 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14555.344914 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20517.779261 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20517.779261 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23458.551694 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23458.551694 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 30801.370915 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 30801.370915 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13259.405139 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13259.405139 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22860.473134 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22860.473134 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 5013046 # number of writebacks +system.cpu0.dcache.writebacks::total 5013046 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 26558 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 26558 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21241 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21241 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 37285 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 37285 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 47799 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 47799 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 47799 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 47799 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2677521 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2677521 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1234147 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1234147 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 577585 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 577585 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 722220 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 722220 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 104533 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 104533 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 191065 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 191065 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4633888 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4633888 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5211473 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5211473 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15891 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 15891 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16800 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16800 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 32691 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 32691 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37485691500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 37485691500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 25473400500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 25473400500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13565827500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13565827500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 23111441500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 23111441500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1404174500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1404174500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4345314000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4345314000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2760500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2760500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 86070533500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 86070533500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 99636361000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 99636361000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2929733500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2929733500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2929733500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2929733500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035778 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035778 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018325 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018325 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.754523 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.754523 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.760819 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.760819 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058198 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058198 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.106447 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.106447 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032374 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032374 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036216 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.036216 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14000.148458 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14000.148458 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20640.491368 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20640.491368 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23487.153406 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23487.153406 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32000.555925 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32000.555925 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13432.834607 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13432.834607 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22742.595452 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22742.595452 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18640.812965 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18640.812965 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19165.367967 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19165.367967 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190692.302535 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190692.302535 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 96101.677733 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 96101.677733 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 4928137 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.903899 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 450782010 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 4928649 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 91.461577 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 30794452000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.903899 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999812 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999812 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18574.150584 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18574.150584 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19118.656280 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19118.656280 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184364.325719 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184364.325719 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 89618.962406 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 89618.962406 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 4327935 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.943806 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 380677204 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 4328447 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 87.947757 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 27073430000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.943806 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999890 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999890 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 407 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 105 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 916349967 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 916349967 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 450782010 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 450782010 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 450782010 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 450782010 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 450782010 # number of overall hits -system.cpu0.icache.overall_hits::total 450782010 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 4928649 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 4928649 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 4928649 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 4928649 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 4928649 # number of overall misses -system.cpu0.icache.overall_misses::total 4928649 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 54016215500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 54016215500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 54016215500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 54016215500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 54016215500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 54016215500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 455710659 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 455710659 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 455710659 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 455710659 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 455710659 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 455710659 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010815 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.010815 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010815 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.010815 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010815 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.010815 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10959.639345 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10959.639345 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10959.639345 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10959.639345 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10959.639345 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10959.639345 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 774339749 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 774339749 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 380677204 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 380677204 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 380677204 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 380677204 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 380677204 # number of overall hits +system.cpu0.icache.overall_hits::total 380677204 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 4328447 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 4328447 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 4328447 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 4328447 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 4328447 # number of overall misses +system.cpu0.icache.overall_misses::total 4328447 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 47943054500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 47943054500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 47943054500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 47943054500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 47943054500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 47943054500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 385005651 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 385005651 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 385005651 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 385005651 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 385005651 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 385005651 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011243 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011243 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011243 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011243 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011243 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011243 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11076.271582 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 11076.271582 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11076.271582 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 11076.271582 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11076.271582 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 11076.271582 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 4928137 # number of writebacks -system.cpu0.icache.writebacks::total 4928137 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4928649 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 4928649 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 4928649 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 4928649 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 4928649 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 4928649 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 51551891000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 51551891000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 51551891000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 51551891000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 51551891000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 51551891000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4116534000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4116534000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4116534000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 4116534000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010815 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010815 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010815 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010815 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010815 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010815 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10459.639345 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10459.639345 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10459.639345 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10459.639345 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10459.639345 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10459.639345 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95455.860870 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95455.860870 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7424522 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7424525 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu0.icache.writebacks::writebacks 4327935 # number of writebacks +system.cpu0.icache.writebacks::total 4327935 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4328447 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 4328447 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 4328447 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 4328447 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 4328447 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 4328447 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 4725 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 4725 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 4725 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 4725 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 45778831000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 45778831000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 45778831000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 45778831000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 45778831000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 45778831000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 463686000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 463686000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 463686000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 463686000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011243 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011243 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011243 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011243 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011243 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011243 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10576.271582 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10576.271582 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10576.271582 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10576.271582 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10576.271582 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10576.271582 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98134.603175 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98134.603175 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98134.603175 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98134.603175 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7077148 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7077156 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 998915 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2238289 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15477.322343 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 8961437 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2253120 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 3.977346 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 5406108500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15186.002225 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 32.160912 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 26.574333 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 232.584873 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.926880 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001963 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001622 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.014196 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.944661 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 343 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 59 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14429 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 31 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 121 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 191 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 27 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 31 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1242 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8440 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4747 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.020935 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003601 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.880676 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 361005368 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 361005368 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 239188 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 140105 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 379293 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 3693855 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 3693855 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 6781361 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 6781361 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 879738 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 879738 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4485760 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 4485760 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2821736 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 2821736 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 211609 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 211609 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 239188 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 140105 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 4485760 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3701474 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 8566527 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 239188 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 140105 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 4485760 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3701474 # number of overall hits -system.cpu0.l2cache.overall_hits::total 8566527 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 16649 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8661 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 25310 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 231687 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 231687 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 188526 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 188526 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 243594 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 243594 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 442889 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 442889 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 903613 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 903613 # number of ReadSharedReq misses -system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 582678 # number of InvalidateReq misses -system.cpu0.l2cache.InvalidateReq_misses::total 582678 # number of InvalidateReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 16649 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8661 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 442889 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1147207 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1615406 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 16649 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8661 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 442889 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1147207 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1615406 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 524453500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 332493500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 856947000 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 896560000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 896560000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 330254000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 330254000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1931999 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1931999 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 13649420499 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 13649420499 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 17214501500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 17214501500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 35658673000 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 35658673000 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 429500 # number of InvalidateReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::total 429500 # number of InvalidateReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 524453500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 332493500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 17214501500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 49308093499 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 67379541999 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 524453500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 332493500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 17214501500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 49308093499 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 67379541999 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 255837 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 148766 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 404603 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3693855 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 3693855 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 6781361 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 6781361 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 231687 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 231687 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 188526 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 188526 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1123332 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1123332 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4928649 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 4928649 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3725349 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 3725349 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 794287 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::total 794287 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 255837 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 148766 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 4928649 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 4848681 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 10181933 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 255837 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 148766 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 4928649 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 4848681 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 10181933 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.065077 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.058219 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.062555 # miss rate for ReadReq accesses +system.cpu0.l2cache.prefetcher.pfSpanPage 919708 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 2034832 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15580.971228 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 7927218 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2050121 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 3.866707 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 1712003500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 15267.042973 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 22.154482 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 11.284107 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 280.489666 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.931826 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001352 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000689 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.017120 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.950987 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 305 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 72 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14912 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 65 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 109 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 131 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 29 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 30 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 540 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4190 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7117 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2983 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.018616 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004395 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.910156 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 322659786 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 322659786 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 205975 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 128170 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 334145 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 3330860 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 3330860 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 6009144 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 6009144 # number of WritebackClean hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 802570 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 802570 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 3917036 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 3917036 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2528867 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 2528867 # number of ReadSharedReq hits +system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 164054 # number of InvalidateReq hits +system.cpu0.l2cache.InvalidateReq_hits::total 164054 # number of InvalidateReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 205975 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 128170 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 3917036 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3331437 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 7582618 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 205975 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 128170 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 3917036 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3331437 # number of overall hits +system.cpu0.l2cache.overall_hits::total 7582618 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 15216 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8071 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 23287 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 218667 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 218667 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 191059 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 191059 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 6 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 228793 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 228793 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 411411 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 411411 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 830772 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 830772 # number of ReadSharedReq misses +system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 558166 # number of InvalidateReq misses +system.cpu0.l2cache.InvalidateReq_misses::total 558166 # number of InvalidateReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 15216 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8071 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 411411 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1059565 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 1494263 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 15216 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8071 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 411411 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1059565 # number of overall misses +system.cpu0.l2cache.overall_misses::total 1494263 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 436278500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 272723500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 709002000 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 867672000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 867672000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 318347000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 318347000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2656998 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2656998 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 12612589500 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 12612589500 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 15771055500 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 15771055500 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 30943358500 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 30943358500 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 436278500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 272723500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 15771055500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 43555948000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 60036005500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 436278500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 272723500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 15771055500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 43555948000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 60036005500 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 221191 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 136241 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 357432 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3330860 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 3330860 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 6009144 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 6009144 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 218667 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 218667 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 191059 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 191059 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 6 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1031363 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1031363 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4328447 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 4328447 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3359639 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 3359639 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 722220 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::total 722220 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 221191 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 136241 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 4328447 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 4391002 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 9076881 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 221191 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 136241 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 4328447 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 4391002 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 9076881 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.068791 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.059241 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.065151 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.216850 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.216850 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.089860 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.089860 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.242558 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.242558 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.733586 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.733586 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.065077 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.058219 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.089860 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.236602 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.158654 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.065077 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.058219 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.089860 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.236602 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.158654 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 31500.600637 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 38389.735596 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 33858.040300 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3869.703522 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3869.703522 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1751.768987 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1751.768987 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 482999.750000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 482999.750000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 56033.483990 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 56033.483990 # average ReadExReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38868.658964 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38868.658964 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 39462.328453 # average ReadSharedReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 39462.328453 # average ReadSharedReq miss latency -system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 0.737114 # average InvalidateReq miss latency -system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 0.737114 # average InvalidateReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 31500.600637 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 38389.735596 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38868.658964 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42980.990788 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 41710.592878 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 31500.600637 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 38389.735596 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38868.658964 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42980.990788 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 41710.592878 # average overall miss latency +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.221836 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.221836 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.095048 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.095048 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.247280 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.247280 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.772848 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.772848 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.068791 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.059241 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.095048 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.241304 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.164623 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.068791 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.059241 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.095048 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.241304 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.164623 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 28672.351472 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 33790.546401 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30446.257569 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3968.006146 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3968.006146 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1666.223523 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1666.223523 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 442833 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 442833 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 55126.640675 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 55126.640675 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38334.063746 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38334.063746 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37246.511076 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37246.511076 # average ReadSharedReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 28672.351472 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 33790.546401 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38334.063746 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41107.386522 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 40177.669861 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 28672.351472 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 33790.546401 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38334.063746 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41107.386522 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 40177.669861 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.unused_prefetches 36707 # number of HardPF blocks evicted w/o reference -system.cpu0.l2cache.writebacks::writebacks 1501692 # number of writebacks -system.cpu0.l2cache.writebacks::total 1501692 # number of writebacks -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 6241 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 6241 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 600 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 600 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 1 # number of InvalidateReq MSHR hits -system.cpu0.l2cache.InvalidateReq_mshr_hits::total 1 # number of InvalidateReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6841 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 6841 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6841 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 6841 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 16649 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8661 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 25310 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 726594 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 726594 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 231687 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 231687 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 188526 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 188526 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 237353 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 237353 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 442889 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 442889 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 903013 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 903013 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 582677 # number of InvalidateReq MSHR misses -system.cpu0.l2cache.InvalidateReq_mshr_misses::total 582677 # number of InvalidateReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 16649 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8661 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 442889 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1140366 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 1608565 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 16649 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8661 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 442889 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1140366 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 726594 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 2335159 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 29828 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 72953 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 29359 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 29359 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 59187 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 102312 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 424559500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 280527500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 705087000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 37258472903 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 37258472903 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4314197500 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4314197500 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2894861999 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2894861999 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1631999 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1631999 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11516279999 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11516279999 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 14557167500 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 14557167500 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 30162372000 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 30162372000 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18401745500 # number of InvalidateReq MSHR miss cycles -system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18401745500 # number of InvalidateReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 424559500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 280527500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 14557167500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 41678651999 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 56940906499 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 424559500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 280527500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 14557167500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 41678651999 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 37258472903 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 94199379402 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3793096500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5448952500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9242049000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3793096500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5448952500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9242049000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.065077 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.058219 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.062555 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.unused_prefetches 34479 # number of HardPF blocks evicted w/o reference +system.cpu0.l2cache.writebacks::writebacks 1361012 # number of writebacks +system.cpu0.l2cache.writebacks::total 1361012 # number of writebacks +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5370 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 5370 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 489 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 489 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 5859 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 5859 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 5859 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 5859 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 15216 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8071 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 23287 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 675054 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 675054 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 218667 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 218667 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 191059 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 191059 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 6 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 223423 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 223423 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 411411 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 411411 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 830283 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 830283 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 558166 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.InvalidateReq_mshr_misses::total 558166 # number of InvalidateReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 15216 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8071 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 411411 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1053706 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 1488404 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 15216 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8071 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 411411 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1053706 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 675054 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 2163458 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 4725 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 15891 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 20616 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 16800 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 16800 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 4725 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 32691 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 37416 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 344982500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 224297500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 569280000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 32033056811 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 32033056811 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4084370000 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4084370000 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2911469499 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2911469499 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2248998 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2248998 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10644364000 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10644364000 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 13302589500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 13302589500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 25893671500 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 25893671500 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 17612762500 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 17612762500 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 344982500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 224297500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 13302589500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 36538035500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 50409905000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 344982500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 224297500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 13302589500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 36538035500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 32033056811 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 82442961811 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 428248500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2802283500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 3230532000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 428248500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 2802283500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 3230532000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.068791 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.059241 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.065151 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses @@ -1272,123 +1293,123 @@ system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.211294 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.211294 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.089860 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.089860 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.242397 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242397 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.733585 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.733585 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.065077 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.058219 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.089860 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.235191 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.157982 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.065077 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.058219 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.089860 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.235191 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.216629 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.216629 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.095048 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.095048 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.247135 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.247135 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.772848 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.772848 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.068791 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.059241 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.095048 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.239969 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.163977 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.068791 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.059241 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.095048 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.239969 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229343 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25500.600637 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 32389.735596 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27858.040300 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 51278.255674 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 51278.255674 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18620.800908 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18620.800908 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15355.240121 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15355.240121 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 407999.750000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 407999.750000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 48519.631094 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 48519.631094 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32868.658964 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32868.658964 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 33401.924446 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33401.924446 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31581.382996 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31581.382996 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25500.600637 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 32389.735596 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32868.658964 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36548.487064 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 35398.573573 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25500.600637 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 32389.735596 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32868.658964 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36548.487064 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 51278.255674 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 40339.599745 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182679.110232 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126684.975258 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 92063.333164 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 90332.013840 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 21698067 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11128745 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1153 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 593692 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 593692 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.238348 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22672.351472 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27790.546401 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24446.257569 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 47452.584254 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 47452.584254 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18678.492868 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18678.492868 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15238.588598 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15238.588598 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 374833 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 374833 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 47642.203354 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 47642.203354 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32334.063746 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32334.063746 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31186.561088 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31186.561088 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31554.703260 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31554.703260 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22672.351472 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27790.546401 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32334.063746 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34675.740197 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33868.428867 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22672.351472 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27790.546401 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32334.063746 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34675.740197 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 47452.584254 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38107.031341 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90634.603175 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176344.062677 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 156700.232829 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90634.603175 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 85720.335872 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 86340.923669 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 19414965 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 9975279 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 976 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 578988 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 578988 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 544237 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 9287091 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 29360 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 29359 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5208748 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 6782514 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1060718 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 892976 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 428421 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348722 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 483695 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1159777 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1132425 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4928649 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4659477 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 859685 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 795582 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14871685 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17955801 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 314812 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 561073 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 33703371 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 631006804 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 671861433 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1190128 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2046696 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1306105061 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 5091046 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 103758092 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 16426970 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.050205 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.218367 # Request fanout histogram +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 442233 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 8226522 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 16801 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 16800 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 4707887 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 6010120 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 978928 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 831060 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 419258 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 359151 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 478987 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 123 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1069161 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1041370 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4328447 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4301809 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 793195 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 723551 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12994279 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16301256 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 289006 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 490041 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 30074582 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 554027348 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 608753046 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1089928 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1769528 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1165639850 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 4847803 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 95443532 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 14917131 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.053800 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.225623 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 15602261 94.98% 94.98% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 824709 5.02% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 14114583 94.62% 94.62% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 802548 5.38% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 16426970 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 21511948503 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 14917131 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 19175088002 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 179528613 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 194853286 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 7436098500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 6497395500 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7925019139 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7177011173 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 166046000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 152765499 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 305236000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 268850499 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1418,72 +1439,72 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 105151 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 105151 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9241 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80639 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 105142 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.076088 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 24.671859 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-511 105141 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 108097 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 108097 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9121 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 84193 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 108080 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.074019 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 24.334214 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-511 108079 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 105142 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 89889 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 24662.817475 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 22388.286381 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 19750.546055 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 88485 98.44% 98.44% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1078 1.20% 99.64% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 161 0.18% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 60 0.07% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 44 0.05% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkWaitTime::total 108080 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 93331 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 24327.977842 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 22238.306429 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 18706.694176 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 92079 98.66% 98.66% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 920 0.99% 99.64% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 176 0.19% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 54 0.06% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 42 0.05% 99.94% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::327680-393215 24 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 9 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 23 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 89889 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 550636548 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.425840 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.494470 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 316153352 57.42% 57.42% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 234483196 42.58% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 550636548 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 80640 89.72% 89.72% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 9241 10.28% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 89881 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 105151 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 17 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 93331 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 5379088140 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.979144 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.142902 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 112185648 2.09% 2.09% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 5266902492 97.91% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 5379088140 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 84194 90.23% 90.23% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 9121 9.77% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 93315 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 108097 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 105151 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 89881 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 108097 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 93315 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 89881 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 195032 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 93315 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 201412 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 80227147 # DTB read hits -system.cpu1.dtb.read_misses 76874 # DTB read misses -system.cpu1.dtb.write_hits 72873093 # DTB write hits -system.cpu1.dtb.write_misses 28277 # DTB write misses +system.cpu1.dtb.read_hits 86913541 # DTB read hits +system.cpu1.dtb.read_misses 78813 # DTB read misses +system.cpu1.dtb.write_hits 79382446 # DTB write hits +system.cpu1.dtb.write_misses 29284 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 38283 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 40011 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1026 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 38404 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 3894 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4493 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10612 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 80304021 # DTB read accesses -system.cpu1.dtb.write_accesses 72901370 # DTB write accesses +system.cpu1.dtb.perms_faults 10593 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 86992354 # DTB read accesses +system.cpu1.dtb.write_accesses 79411730 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 153100240 # DTB hits -system.cpu1.dtb.misses 105151 # DTB misses -system.cpu1.dtb.accesses 153205391 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 166295987 # DTB hits +system.cpu1.dtb.misses 108097 # DTB misses +system.cpu1.dtb.accesses 166404084 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1513,763 +1534,767 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 60537 # Table walker walks requested -system.cpu1.itb.walker.walksLong 60537 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 545 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54626 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 60537 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 60537 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 60537 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 55171 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 27009.443367 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 24147.107472 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 24376.496047 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 53734 97.40% 97.40% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 967 1.75% 99.15% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 279 0.51% 99.65% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 75 0.14% 99.79% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 69 0.13% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 15 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 18 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 67294 # Table walker walks requested +system.cpu1.itb.walker.walksLong 67294 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 626 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61475 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 67294 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 67294 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 67294 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 62101 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 26137.727251 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23789.803797 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 22700.198457 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 60815 97.93% 97.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 864 1.39% 99.32% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 247 0.40% 99.72% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 72 0.12% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 48 0.08% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 18 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 23 0.04% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 55171 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -589503148 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -589503148 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -589503148 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 54626 99.01% 99.01% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 545 0.99% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 55171 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 62101 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -17274852 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -17274852 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -17274852 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 61475 98.99% 98.99% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 626 1.01% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 62101 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60537 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60537 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 67294 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 67294 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55171 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55171 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 115708 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 423099313 # ITB inst hits -system.cpu1.itb.inst_misses 60537 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62101 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62101 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 129395 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 422829218 # ITB inst hits +system.cpu1.itb.inst_misses 67294 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 41072 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 26774 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 40011 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1026 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 27014 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 423159850 # ITB inst accesses -system.cpu1.itb.hits 423099313 # DTB hits -system.cpu1.itb.misses 60537 # DTB misses -system.cpu1.itb.accesses 423159850 # DTB accesses -system.cpu1.numPwrStateTransitions 11486 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 5743 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 8166193258.773638 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 240112362617.634613 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 4041 70.36% 70.36% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 1686 29.36% 99.72% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 8 0.14% 99.86% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.03% 99.90% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.91% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.93% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 4 0.07% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 422896512 # ITB inst accesses +system.cpu1.itb.hits 422829218 # DTB hits +system.cpu1.itb.misses 67294 # DTB misses +system.cpu1.itb.accesses 422896512 # DTB accesses +system.cpu1.numPwrStateTransitions 29136 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 14568 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 3216976278.654242 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 84611127659.505341 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 4387 30.11% 30.11% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 10152 69.69% 99.80% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.84% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 11813607762500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 5743 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 506632997363 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 46898447885137 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 94810161765 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 7390879628476 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 14568 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 536460160065 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 46864910427435 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 94802741175 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5743 # number of quiesce instructions executed -system.cpu1.committedInsts 422818462 # Number of instructions committed -system.cpu1.committedOps 498817050 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 458669371 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 488965 # Number of float alu accesses -system.cpu1.num_func_calls 25225246 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 64273848 # number of instructions that are conditional controls -system.cpu1.num_int_insts 458669371 # number of integer instructions -system.cpu1.num_fp_insts 488965 # number of float instructions -system.cpu1.num_int_register_reads 669788044 # number of times the integer registers were read -system.cpu1.num_int_register_writes 364108323 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 780829 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 430972 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 109344834 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 109137409 # number of times the CC registers were written -system.cpu1.num_mem_refs 153090665 # number of memory refs -system.cpu1.num_load_insts 80223644 # Number of load instructions -system.cpu1.num_store_insts 72867021 # Number of store instructions -system.cpu1.num_idle_cycles 93796895770.272018 # Number of idle cycles -system.cpu1.num_busy_cycles 1013265994.727979 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010687 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989313 # Percentage of idle cycles -system.cpu1.Branches 94103649 # Number of branches fetched +system.cpu1.kern.inst.quiesce 14568 # number of quiesce instructions executed +system.cpu1.committedInsts 422521065 # Number of instructions committed +system.cpu1.committedOps 504842112 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 470472983 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 594254 # Number of float alu accesses +system.cpu1.num_func_calls 27792823 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 60626161 # number of instructions that are conditional controls +system.cpu1.num_int_insts 470472983 # number of integer instructions +system.cpu1.num_fp_insts 594254 # number of float instructions +system.cpu1.num_int_register_reads 624330931 # number of times the integer registers were read +system.cpu1.num_int_register_writes 367229936 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 937660 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 547764 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 91358730 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 91073731 # number of times the CC registers were written +system.cpu1.num_mem_refs 166284311 # number of memory refs +system.cpu1.num_load_insts 86908703 # Number of load instructions +system.cpu1.num_store_insts 79375608 # Number of store instructions +system.cpu1.num_idle_cycles 93729820854.868027 # Number of idle cycles +system.cpu1.num_busy_cycles 1072920320.131977 # Number of busy cycles +system.cpu1.not_idle_fraction 0.011317 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.988683 # Percentage of idle cycles +system.cpu1.Branches 93458434 # Number of branches fetched system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 344832107 69.09% 69.09% # Class of executed instruction -system.cpu1.op_class::IntMult 1045045 0.21% 69.30% # Class of executed instruction -system.cpu1.op_class::IntDiv 60210 0.01% 69.31% # Class of executed instruction -system.cpu1.op_class::FloatAdd 8 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::FloatCmp 13 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::FloatCvt 21 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::FloatMultAcc 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.31% # Class of executed instruction -system.cpu1.op_class::FloatMisc 69940 0.01% 69.33% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.33% # Class of executed instruction -system.cpu1.op_class::MemRead 80163191 16.06% 85.39% # Class of executed instruction -system.cpu1.op_class::MemWrite 72508491 14.53% 99.92% # Class of executed instruction -system.cpu1.op_class::FloatMemRead 60453 0.01% 99.93% # Class of executed instruction -system.cpu1.op_class::FloatMemWrite 358530 0.07% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 337624684 66.84% 66.84% # Class of executed instruction +system.cpu1.op_class::IntMult 1094737 0.22% 67.05% # Class of executed instruction +system.cpu1.op_class::IntDiv 62780 0.01% 67.07% # Class of executed instruction +system.cpu1.op_class::FloatAdd 8 0.00% 67.07% # Class of executed instruction +system.cpu1.op_class::FloatCmp 13 0.00% 67.07% # Class of executed instruction +system.cpu1.op_class::FloatCvt 21 0.00% 67.07% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 67.07% # Class of executed instruction +system.cpu1.op_class::FloatMultAcc 0 0.00% 67.07% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 67.07% # Class of executed instruction +system.cpu1.op_class::FloatMisc 83819 0.02% 67.08% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.08% # Class of executed instruction +system.cpu1.op_class::MemRead 86829386 17.19% 84.27% # Class of executed instruction +system.cpu1.op_class::MemWrite 78944532 15.63% 99.90% # Class of executed instruction +system.cpu1.op_class::FloatMemRead 79317 0.02% 99.91% # Class of executed instruction +system.cpu1.op_class::FloatMemWrite 431076 0.09% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 499098010 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 5131141 # number of replacements -system.cpu1.dcache.tags.tagsinuse 448.476526 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 147794571 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5131653 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.800578 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8379654946000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 448.476526 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.875931 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.875931 # Average percentage of cache occupancy +system.cpu1.op_class::total 505150374 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 5478037 # number of replacements +system.cpu1.dcache.tags.tagsinuse 455.042894 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 160612984 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5478549 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.316701 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8375929793000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.042894 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.888756 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.888756 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 420 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 311357915 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 311357915 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 74677091 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 74677091 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 69169144 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 69169144 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 167775 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 167775 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 60851 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 60851 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1670690 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1670690 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1646008 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1646008 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 143907086 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 143907086 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 144074861 # number of overall hits -system.cpu1.dcache.overall_hits::total 144074861 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2897407 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2897407 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1336766 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1336766 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 634591 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 634591 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 446061 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 446061 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 170887 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 170887 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 194464 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 194464 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4680234 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4680234 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5314825 # number of overall misses -system.cpu1.dcache.overall_misses::total 5314825 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43647010000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 43647010000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 25591315500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 25591315500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 9621405000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 9621405000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2591957500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2591957500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4654513500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4654513500 # number of StoreCondReq miss cycles +system.cpu1.dcache.tags.tag_accesses 338044480 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 338044480 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 80989814 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 80989814 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 75375313 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 75375313 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188638 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 188638 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 105231 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 105231 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1782566 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1782566 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1758380 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1758380 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 156470358 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 156470358 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 156658996 # number of overall hits +system.cpu1.dcache.overall_hits::total 156658996 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3115552 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3115552 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1383415 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1383415 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 634948 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 634948 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 525445 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 525445 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 179669 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 179669 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 202611 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 202611 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5024412 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5024412 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5659360 # number of overall misses +system.cpu1.dcache.overall_misses::total 5659360 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46416085500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 46416085500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 26188875500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 26188875500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10762345500 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 10762345500 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2779147000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2779147000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4838630000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4838630000 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2246000 # number of StoreCondFailReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2246000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 78859730500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 78859730500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 78859730500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 78859730500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 77574498 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 77574498 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 70505910 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 70505910 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 802366 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 802366 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 506912 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 506912 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1841577 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1841577 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1840472 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1840472 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 148587320 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 148587320 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 149389686 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 149389686 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037350 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.037350 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018960 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018960 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.790900 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.790900 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.879957 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.879957 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092794 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092794 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105660 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105660 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031498 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031498 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035577 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035577 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15064.162543 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15064.162543 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19144.199882 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 19144.199882 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 21569.706834 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 21569.706834 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15167.669279 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15167.669279 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23935.090814 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23935.090814 # average StoreCondReq miss latency +system.cpu1.dcache.demand_miss_latency::cpu1.data 83367306500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 83367306500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 83367306500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 83367306500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 84105366 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 84105366 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 76758728 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 76758728 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 823586 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 823586 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 630676 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 630676 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1962235 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1962235 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1960991 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1960991 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 161494770 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 161494770 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 162318356 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 162318356 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037043 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.037043 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018023 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018023 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.770955 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.770955 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.833146 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.833146 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091563 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091563 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103321 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103321 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031112 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031112 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034866 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.034866 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14898.189952 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14898.189952 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18930.599639 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18930.599639 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 20482.344489 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 20482.344489 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15468.149764 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15468.149764 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23881.378602 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23881.378602 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16849.527289 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16849.527289 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14837.690893 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14837.690893 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16592.450321 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16592.450321 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14730.871777 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14730.871777 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 5131141 # number of writebacks -system.cpu1.dcache.writebacks::total 5131141 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 17932 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 17932 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 468 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 468 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44381 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44381 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 18400 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 18400 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 18400 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 18400 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2879475 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2879475 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1336298 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1336298 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 634591 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 634591 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 446061 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 446061 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 126506 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 126506 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 194464 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 194464 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4661834 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4661834 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5296425 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5296425 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8724 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 8724 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 9055 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 9055 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 17779 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 17779 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39613799000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39613799000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24222435000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24222435000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14015397000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14015397000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9175344000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9175344000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1695802000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1695802000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4460100500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4460100500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2195000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2195000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 73011578000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 73011578000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 87026975000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 87026975000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1272776000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1272776000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1272776000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1272776000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037119 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037119 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018953 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018953 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.790900 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.790900 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.879957 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.879957 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068694 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068694 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105660 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105660 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031374 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031374 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035454 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035454 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13757.299160 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13757.299160 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18126.521928 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18126.521928 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22085.716627 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22085.716627 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 20569.706834 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 20569.706834 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13404.913601 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13404.913601 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22935.353073 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22935.353073 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 5478037 # number of writebacks +system.cpu1.dcache.writebacks::total 5478037 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 17265 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 17265 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 318 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 318 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 49763 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 49763 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 17583 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 17583 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 17583 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 17583 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3098287 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3098287 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1383097 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1383097 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 634948 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 634948 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 525445 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 525445 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 129906 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 129906 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 202611 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 202611 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 5006829 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 5006829 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5641777 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5641777 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 22372 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 22372 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 21343 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 21343 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 43715 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 43715 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 42239304500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 42239304500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24787763000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24787763000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13852353000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13852353000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10236900500 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10236900500 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1787997500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1787997500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4636074000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4636074000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2191000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2191000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 77263968000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 77263968000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 91116321000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 91116321000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3993280500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3993280500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3993280500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3993280500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036838 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036838 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018019 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018019 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.770955 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.770955 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.833146 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.833146 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066203 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066203 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103321 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103321 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031003 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031003 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034757 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034757 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13633.115493 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13633.115493 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17921.926662 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17921.926662 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21816.515683 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21816.515683 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 19482.344489 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 19482.344489 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13763.779194 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13763.779194 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22881.650058 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22881.650058 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15661.556804 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15661.556804 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16431.267317 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16431.267317 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145893.626777 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 145893.626777 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 71588.728275 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 71588.728275 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 5003710 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.211749 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 418095086 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5004222 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 83.548469 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8379626352000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.211749 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969164 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969164 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15431.716961 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15431.716961 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16150.287578 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16150.287578 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 178494.569104 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 178494.569104 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91348.061306 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91348.061306 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 5778503 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.250731 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 417050198 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5779015 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 72.166312 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8375901500000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.250731 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969240 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969240 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 129 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 851202853 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 851202853 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 418095086 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 418095086 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 418095086 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 418095086 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 418095086 # number of overall hits -system.cpu1.icache.overall_hits::total 418095086 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 5004227 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 5004227 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 5004227 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 5004227 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 5004227 # number of overall misses -system.cpu1.icache.overall_misses::total 5004227 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 54129933000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 54129933000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 54129933000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 54129933000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 54129933000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 54129933000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 423099313 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 423099313 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 423099313 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 423099313 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 423099313 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 423099313 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011828 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.011828 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011828 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.011828 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011828 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.011828 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10816.842042 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10816.842042 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10816.842042 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10816.842042 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10816.842042 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10816.842042 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 851437456 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 851437456 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 417050198 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 417050198 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 417050198 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 417050198 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 417050198 # number of overall hits +system.cpu1.icache.overall_hits::total 417050198 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5779020 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 5779020 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 5779020 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 5779020 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 5779020 # number of overall misses +system.cpu1.icache.overall_misses::total 5779020 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 61138169500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 61138169500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 61138169500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 61138169500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 61138169500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 61138169500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 422829218 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 422829218 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 422829218 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 422829218 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 422829218 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 422829218 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013668 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.013668 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013668 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.013668 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013668 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.013668 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10579.331703 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10579.331703 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10579.331703 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10579.331703 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10579.331703 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10579.331703 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 5003710 # number of writebacks -system.cpu1.icache.writebacks::total 5003710 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5004227 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5004227 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5004227 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5004227 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5004227 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5004227 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 5778503 # number of writebacks +system.cpu1.icache.writebacks::total 5778503 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5779020 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5779020 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5779020 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5779020 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5779020 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5779020 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 51627819500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 51627819500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 51627819500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 51627819500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 51627819500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 51627819500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10917500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10917500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10917500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 10917500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011828 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011828 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011828 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.011828 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011828 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.011828 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10316.842042 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10316.842042 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10316.842042 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10316.842042 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10316.842042 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10316.842042 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 99250 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 99250 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 99250 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 99250 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7173608 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7173625 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 58248659500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 58248659500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 58248659500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 58248659500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 58248659500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 58248659500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10594500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10594500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10594500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10594500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013668 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013668 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013668 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.013668 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013668 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.013668 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10079.331703 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10079.331703 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10079.331703 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10079.331703 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10079.331703 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10079.331703 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 96313.636364 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 96313.636364 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 96313.636364 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 96313.636364 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7190671 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7190679 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 895743 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 1888854 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13151.739114 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 8987368 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 1904692 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 4.718541 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 898577 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 1924030 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 12969.443296 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 10103718 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 1939825 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 5.208572 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12880.289345 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 17.911148 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 9.232940 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 244.305681 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.786150 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001093 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000564 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014911 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.802718 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 286 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 66 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15486 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 117 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 96 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 70 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 12701.469256 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 37.295961 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 26.822764 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 203.855315 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.775236 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002276 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001637 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.012442 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.791592 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 331 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15403 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 142 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 95 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 88 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 46 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1447 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5487 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7313 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1113 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017456 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004028 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.945190 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 349452832 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 349452832 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 234483 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 153773 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 388256 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 3241183 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 3241183 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 6893065 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 6893065 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 876408 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 876408 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4540376 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 4540376 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2756982 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 2756982 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 197607 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 197607 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 234483 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 153773 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4540376 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3633390 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 8562022 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 234483 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 153773 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4540376 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3633390 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8562022 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 18869 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10447 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 29316 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 206667 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 206667 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 194457 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 194457 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 253441 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 253441 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 463851 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 463851 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 883590 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 883590 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 248454 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 248454 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 18869 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10447 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 463851 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1137031 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1630198 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 18869 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10447 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 463851 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1137031 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1630198 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 633582000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 432596500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1066178500 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 941410000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 941410000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 356938000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 356938000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2118500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2118500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11335810999 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 11335810999 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 16839909000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 16839909000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 31901147000 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 31901147000 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 63500 # number of InvalidateReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::total 63500 # number of InvalidateReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 633582000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 432596500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 16839909000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 43236957999 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 61143045499 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 633582000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 432596500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 16839909000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 43236957999 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 61143045499 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 253352 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 164220 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 417572 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3241183 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 3241183 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 6893065 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 6893065 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 206667 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 206667 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 194457 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 194457 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1129849 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1129849 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5004227 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 5004227 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3640572 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 3640572 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 446061 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.InvalidateReq_accesses::total 446061 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 253352 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 164220 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 5004227 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4770421 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 10192220 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 253352 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 164220 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 5004227 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4770421 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 10192220 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.074477 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.063616 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.070206 # miss rate for ReadReq accesses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 32 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1498 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5779 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5762 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2244 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.020203 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.940125 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 387081443 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 387081443 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 243745 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 174457 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 418202 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 3475258 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 3475258 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 7780467 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 7780467 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 920068 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 920068 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5308980 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 5308980 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2962504 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 2962504 # number of ReadSharedReq hits +system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 264311 # number of InvalidateReq hits +system.cpu1.l2cache.InvalidateReq_hits::total 264311 # number of InvalidateReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 243745 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 174457 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 5308980 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3882572 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 9609754 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 243745 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 174457 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 5308980 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3882572 # number of overall hits +system.cpu1.l2cache.overall_hits::total 9609754 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 18156 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9553 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 27709 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 208398 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 208398 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 202605 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 202605 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 254808 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 254808 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 470040 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 470040 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 900637 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 900637 # number of ReadSharedReq misses +system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 261134 # number of InvalidateReq misses +system.cpu1.l2cache.InvalidateReq_misses::total 261134 # number of InvalidateReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 18156 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9553 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 470040 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1155445 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 1653194 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 18156 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9553 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 470040 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1155445 # number of overall misses +system.cpu1.l2cache.overall_misses::total 1653194 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 581758000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 383665000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 965423000 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 884282500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 884282500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 360962500 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 360962500 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2107498 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2107498 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11534187000 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 11534187000 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 17654070500 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 17654070500 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 32780970500 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 32780970500 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 198500 # number of InvalidateReq miss cycles +system.cpu1.l2cache.InvalidateReq_miss_latency::total 198500 # number of InvalidateReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 581758000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 383665000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 17654070500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 44315157500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 62934651000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 581758000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 383665000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 17654070500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 44315157500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 62934651000 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 261901 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 184010 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 445911 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3475258 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 3475258 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 7780467 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 7780467 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 208398 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 208398 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 202605 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 202605 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1174876 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1174876 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5779020 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 5779020 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3863141 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 3863141 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 525445 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::total 525445 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 261901 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 184010 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 5779020 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 5038017 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 11262948 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 261901 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 184010 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 5779020 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 5038017 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 11262948 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.069324 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.051916 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.062140 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.224314 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.224314 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.092692 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.092692 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.242706 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.242706 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.556996 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.556996 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.074477 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.063616 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.092692 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.238350 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.159945 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.074477 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.063616 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.092692 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.238350 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.159945 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 33577.932058 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41408.681918 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 36368.484786 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4555.202330 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4555.202330 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1835.562618 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1835.562618 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 302642.857143 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 302642.857143 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44727.613129 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44727.613129 # average ReadExReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36304.565475 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36304.565475 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 36104.015437 # average ReadSharedReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 36104.015437 # average ReadSharedReq miss latency -system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 0.255581 # average InvalidateReq miss latency -system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 0.255581 # average InvalidateReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 33577.932058 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41408.681918 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36304.565475 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 38026.191018 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 37506.514852 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 33577.932058 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41408.681918 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36304.565475 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 38026.191018 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 37506.514852 # average overall miss latency +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.216881 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.216881 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.081336 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.081336 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.233136 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.233136 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.496977 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.496977 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.069324 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.051916 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.081336 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.229345 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.146782 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.069324 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.051916 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.081336 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.229345 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.146782 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 32042.189910 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 40161.729300 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 34841.495543 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4243.238899 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4243.238899 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1781.607068 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1781.607068 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 351249.666667 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 351249.666667 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 45266.188660 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 45266.188660 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37558.655646 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37558.655646 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 36397.539186 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 36397.539186 # average ReadSharedReq miss latency +system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 0.760146 # average InvalidateReq miss latency +system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 0.760146 # average InvalidateReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 32042.189910 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 40161.729300 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37558.655646 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 38353.324909 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 38068.521299 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 32042.189910 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 40161.729300 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37558.655646 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 38353.324909 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 38068.521299 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.unused_prefetches 39938 # number of HardPF blocks evicted w/o reference -system.cpu1.l2cache.writebacks::writebacks 1086447 # number of writebacks -system.cpu1.l2cache.writebacks::total 1086447 # number of writebacks -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4568 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 4568 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 305 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 305 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.unused_prefetches 40493 # number of HardPF blocks evicted w/o reference +system.cpu1.l2cache.writebacks::writebacks 1134178 # number of writebacks +system.cpu1.l2cache.writebacks::total 1134178 # number of writebacks +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4642 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 4642 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 415 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 415 # number of ReadSharedReq MSHR hits system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 1 # number of InvalidateReq MSHR hits system.cpu1.l2cache.InvalidateReq_mshr_hits::total 1 # number of InvalidateReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 4873 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 4873 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 4873 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 4873 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 18869 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10447 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 29316 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 688963 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 688963 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 206667 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 206667 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 194457 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 194457 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 7 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 248873 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 248873 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 463851 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 463851 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 883285 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 883285 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 248453 # number of InvalidateReq MSHR misses -system.cpu1.l2cache.InvalidateReq_mshr_misses::total 248453 # number of InvalidateReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 18869 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10447 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 463851 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1132158 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 1625325 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 18869 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10447 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 463851 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1132158 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 688963 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 2314288 # number of overall MSHR misses +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 5057 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 5057 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 5057 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 5057 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 18156 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9553 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 27709 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 685885 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 685885 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 208398 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 208398 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 202605 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 202605 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 250166 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 250166 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 470040 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 470040 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 900222 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 900222 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 261133 # number of InvalidateReq MSHR misses +system.cpu1.l2cache.InvalidateReq_mshr_misses::total 261133 # number of InvalidateReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 18156 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9553 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 470040 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1150388 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 1648137 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 18156 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9553 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 470040 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1150388 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 685885 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 2334022 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 8724 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 8834 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 9055 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 9055 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 22372 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 22482 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 21343 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 21343 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 17779 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 17889 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 520368000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 369914500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 890282500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27673006691 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 27673006691 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 3909692000 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 3909692000 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3000401499 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3000401499 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1812500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1812500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9302871999 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9302871999 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14056803000 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14056803000 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 26558969500 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 26558969500 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 5731021500 # number of InvalidateReq MSHR miss cycles -system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 5731021500 # number of InvalidateReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 520368000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 369914500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14056803000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 35861841499 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 50808926999 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 520368000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 369914500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14056803000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 35861841499 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27673006691 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 78481933690 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10092500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1202508000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1212600500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 10092500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1202508000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1212600500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.074477 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.063616 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.070206 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 43715 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 43825 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 472822000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 326347000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 799169000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 28141665535 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 28141665535 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 3910093000 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 3910093000 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3115291500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3115291500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1777498 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1777498 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9489009000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9489009000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14833830500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14833830500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 27315818000 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 27315818000 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6163710000 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6163710000 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 472822000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 326347000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14833830500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 36804827000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 52437826500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 472822000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 326347000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14833830500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 36804827000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 28141665535 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 80579492035 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9769500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3813749500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3823519000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9769500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3813749500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3823519000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.069324 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.051916 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.062140 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses @@ -2278,128 +2303,128 @@ system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.220271 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.220271 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.092692 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092692 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.242623 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242623 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.556993 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.556993 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.074477 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.063616 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.092692 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.237329 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159467 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.074477 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.063616 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.092692 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.237329 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.212930 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.212930 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.081336 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.081336 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.233029 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.233029 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.496975 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.496975 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.069324 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.051916 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.081336 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.228341 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.146333 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.069324 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.051916 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.081336 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.228341 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.227064 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30368.484786 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40166.172481 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 40166.172481 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18917.834003 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18917.834003 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15429.639967 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15429.639967 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 258928.571429 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 258928.571429 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37379.997023 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37379.997023 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30304.565475 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 30068.403177 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30068.403177 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23066.823504 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23066.823504 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31675.650836 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31260.779843 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 27577.932058 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35408.681918 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30304.565475 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31675.650836 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 40166.172481 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33911.913163 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91750 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 137839.064649 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 137265.168667 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91750 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 67636.424996 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 67784.700095 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 21003363 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10784914 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 608 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 562670 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 562670 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 495353 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9225555 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 9055 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 9055 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4342808 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 6893668 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 1123725 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 834597 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 381961 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 350555 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 459411 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1160534 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1136567 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5004227 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4505940 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 508009 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 447155 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15012384 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16553521 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 345144 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 558947 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 32469996 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 640508408 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 639647146 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1313760 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2026816 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1283496130 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 4569933 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 76953880 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 15475638 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.052337 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.222706 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.207230 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26042.189910 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 34161.729300 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 28841.495543 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41029.714216 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41029.714216 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18762.622482 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18762.622482 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15376.182720 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15376.182720 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 296249.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 296249.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37930.849916 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37930.849916 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31558.655646 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31558.655646 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 30343.424178 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30343.424178 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23603.719178 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23603.719178 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26042.189910 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 34161.729300 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31558.655646 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31993.403095 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31816.424545 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26042.189910 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 34161.729300 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31558.655646 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31993.403095 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41029.714216 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34523.878539 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88813.636364 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170469.761309 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 170070.233965 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88813.636364 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87241.210111 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87245.156874 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 23256823 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11916693 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 817 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 568685 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 568681 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 4 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 538115 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 10263353 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 21343 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 21343 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4626226 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 7781279 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 1111211 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 833315 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 380175 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 364314 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 469217 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 123 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1205096 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1180975 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5779020 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4693276 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 584455 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 526474 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17336763 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17662942 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 385121 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 576423 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 35961249 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 739681912 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 678880625 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1472080 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2095208 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1422129825 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4566671 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 79930832 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 16661362 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.048994 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.215856 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 14665687 94.77% 94.77% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 809951 5.23% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 15845064 95.10% 95.10% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 816294 4.90% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 4 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 15475638 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 20769928998 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 16661362 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 23051952997 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 168229153 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 163764383 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7506450500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8668640000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7592764051 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 8058549119 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 180924000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 201111499 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 305595000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 314522000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40383 # Transaction distribution -system.iobus.trans_dist::ReadResp 40383 # Transaction distribution -system.iobus.trans_dist::WriteReq 136636 # Transaction distribution -system.iobus.trans_dist::WriteResp 136636 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47758 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40263 # Transaction distribution +system.iobus.trans_dist::ReadResp 40263 # Transaction distribution +system.iobus.trans_dist::WriteReq 136535 # Transaction distribution +system.iobus.trans_dist::WriteResp 136535 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47338 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2412,13 +2437,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122692 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231266 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231266 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122272 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47778 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353596 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47358 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2431,27 +2456,27 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155799 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339080 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7339080 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155379 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338992 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338992 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496965 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36934001 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496457 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36598000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 319001 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 319500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) @@ -2459,75 +2484,75 @@ system.iobus.reqLayer16.occupancy 13000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25636500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25735000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 37418000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 37421000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 570101370 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 570201068 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92787000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92468000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147962000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147940000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115614 # number of replacements -system.iocache.tags.tagsinuse 11.296592 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115618 # number of replacements +system.iocache.tags.tagsinuse 11.260426 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115630 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115634 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9136749782000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.841541 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.455051 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240096 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.465941 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706037 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9133276021000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.412431 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.847995 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463277 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.240500 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.703777 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1041054 # Number of tag accesses -system.iocache.tags.data_accesses 1041054 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1040955 # Number of tag accesses +system.iocache.tags.data_accesses 1040955 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8905 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8942 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8894 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8931 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115633 # number of demand (read+write) misses -system.iocache.demand_misses::total 115673 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115622 # number of demand (read+write) misses +system.iocache.demand_misses::total 115662 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115633 # number of overall misses -system.iocache.overall_misses::total 115673 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1975225504 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1980423504 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115622 # number of overall misses +system.iocache.overall_misses::total 115662 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 2022255480 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 2027450480 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13261468866 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13261468866 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15236694370 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15242261370 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15236694370 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15242261370 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13353085588 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13353085588 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15375341068 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15380905068 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15375341068 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15380905068 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8905 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8942 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8894 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8931 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115633 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115673 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115622 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115662 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115633 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115673 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115622 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115662 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2541,53 +2566,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 221810.837058 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 221474.335048 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 227373.002024 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 227012.706304 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 124254.824095 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 124254.824095 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 131767.699273 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 131770.260735 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 131767.699273 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 131770.260735 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 49344 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125113.237276 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125113.237276 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 132979.373026 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 132981.489755 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 132979.373026 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 132981.489755 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 51037 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3519 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3535 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 14.022165 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 14.437624 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8905 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8942 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8894 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8931 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115633 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115673 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115622 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115662 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115633 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115673 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1529975504 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1533323504 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115622 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115662 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1577555480 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1580900480 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7919102558 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7919102558 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9449078062 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9452645062 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9449078062 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9452645062 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8010840420 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8010840420 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9588395900 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9591959900 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9588395900 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9591959900 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2601,654 +2626,663 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 171810.837058 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 171474.335048 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 177373.002024 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 177012.706304 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74198.922101 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74198.922101 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 81716.102341 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 81718.681646 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 81716.102341 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 81718.681646 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1381741 # number of replacements -system.l2c.tags.tagsinuse 65067.880129 # Cycle average of tags in use -system.l2c.tags.total_refs 5923587 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1442494 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.106490 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 9880371500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12193.656277 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 173.628854 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 215.563389 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4072.894051 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 15215.630293 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9216.886744 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 263.489010 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 298.478725 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2688.288956 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 9916.445518 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10812.918313 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.186060 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002649 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003289 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.062147 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.232172 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.140639 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004021 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.004554 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.041020 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.151313 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.164992 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.992857 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10723 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 255 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 49775 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 111 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 261 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 10351 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 254 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1155 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4128 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 44374 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.163620 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003891 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.759506 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 67794643 # Number of tag accesses -system.l2c.tags.data_accesses 67794643 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2588139 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2588139 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 176729 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 155906 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 332635 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 47999 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 52030 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 100029 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 45484 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 61265 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106749 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 8895 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3831 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 389694 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 511362 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 253998 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 11472 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5780 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 424247 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 536390 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 284910 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2430579 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 112195 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 128573 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 240768 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 8895 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3831 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 389694 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 556846 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 253998 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 11472 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5780 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 424247 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 597655 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 284910 # number of demand (read+write) hits -system.l2c.demand_hits::total 2537328 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 8895 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3831 # number of overall hits -system.l2c.overall_hits::cpu0.inst 389694 # number of overall hits -system.l2c.overall_hits::cpu0.data 556846 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 253998 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 11472 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5780 # number of overall hits -system.l2c.overall_hits::cpu1.inst 424247 # number of overall hits -system.l2c.overall_hits::cpu1.data 597655 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 284910 # number of overall hits -system.l2c.overall_hits::total 2537328 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 21760 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 23268 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 45028 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 910 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 658 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1568 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 75776 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 50200 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 125976 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1546 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1542 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 53195 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 142597 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 239651 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2105 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2105 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 39604 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 101630 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 169145 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 753120 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 431914 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 78834 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 510748 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1546 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1542 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 53195 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 218373 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 239651 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2105 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2105 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 39604 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 151830 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 169145 # number of demand (read+write) misses -system.l2c.demand_misses::total 879096 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1546 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1542 # number of overall misses -system.l2c.overall_misses::cpu0.inst 53195 # number of overall misses -system.l2c.overall_misses::cpu0.data 218373 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 239651 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2105 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2105 # number of overall misses -system.l2c.overall_misses::cpu1.inst 39604 # number of overall misses -system.l2c.overall_misses::cpu1.data 151830 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 169145 # number of overall misses -system.l2c.overall_misses::total 879096 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 125369500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 122687000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 248056500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 8279000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 9419500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 17698500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 8192378000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5499536500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 13691914500 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 156458500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 155995000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5894542000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 15712860500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 32464178904 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 215561000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 217319500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 4715127500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 11789045500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 22441982278 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 93763070682 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 156458500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 155995000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 5894542000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 23905238500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 32464178904 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 215561000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 217319500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 4715127500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 17288582000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 22441982278 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 107454985182 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 156458500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 155995000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 5894542000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 23905238500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 32464178904 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 215561000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 217319500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 4715127500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 17288582000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 22441982278 # number of overall miss cycles -system.l2c.overall_miss_latency::total 107454985182 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 2588139 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 2588139 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 198489 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 179174 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 377663 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 48909 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 52688 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 101597 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 121260 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 111465 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 232725 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 10441 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5373 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 442889 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 653959 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 493649 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 13577 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7885 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 463851 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 638020 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 454055 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 3183699 # number of ReadSharedReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu0.data 544109 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu1.data 207407 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::total 751516 # number of InvalidateReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 10441 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 5373 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 442889 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 775219 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 493649 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 13577 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7885 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 463851 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 749485 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 454055 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3416424 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 10441 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 5373 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 442889 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 775219 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 493649 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 13577 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7885 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 463851 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 749485 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 454055 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3416424 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.109628 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.129863 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.119228 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.018606 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.012489 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.015434 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.624905 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.450366 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.541308 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.148070 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.286991 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.120109 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.218052 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.485468 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.155042 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.266963 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.085381 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.159290 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.372521 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.236555 # miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_miss_rate::cpu0.data 0.793801 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::cpu1.data 0.380093 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::total 0.679624 # miss rate for InvalidateReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.148070 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.286991 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.120109 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.281692 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.485468 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.155042 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.266963 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.085381 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.202579 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.372521 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.257315 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.148070 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.286991 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.120109 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.281692 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.485468 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.155042 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.266963 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.085381 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.202579 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.372521 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.257315 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5761.465993 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5272.778064 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 5508.938882 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 9097.802198 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 14315.349544 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 11287.308673 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 108113.096495 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 109552.519920 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 108686.690322 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 101202.134541 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 101164.072633 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 110810.076135 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 110190.680730 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 135464.399915 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 102404.275534 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 103239.667458 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 119056.850318 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 115999.660533 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 132678.957569 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 124499.509616 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 101202.134541 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 101164.072633 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 110810.076135 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 109469.753587 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 135464.399915 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 102404.275534 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 103239.667458 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 119056.850318 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 113868.023447 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132678.957569 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 122233.504853 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 101202.134541 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 101164.072633 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 110810.076135 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 109469.753587 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 135464.399915 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 102404.275534 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 103239.667458 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 119056.850318 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 113868.023447 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132678.957569 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 122233.504853 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 213 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75058.470317 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75058.470317 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 82928.818910 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 82930.953122 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 82928.818910 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 82930.953122 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 1289685 # number of replacements +system.l2c.tags.tagsinuse 65148.785380 # Cycle average of tags in use +system.l2c.tags.total_refs 5723107 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1350729 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.237051 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 6059472500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 12155.679811 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 124.426191 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 138.926128 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3396.773965 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 12605.328956 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 8503.765275 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 300.348884 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 348.970492 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3831.795073 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 12139.257493 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11603.513111 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.185481 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001899 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.002120 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.051831 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.192342 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.129757 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004583 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.005325 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.058469 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.185230 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.177056 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994092 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 12163 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 299 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 48582 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 174 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 318 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 11671 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 297 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1173 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4557 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 42755 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.185593 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.004562 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.741302 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 65194650 # Number of tag accesses +system.l2c.tags.data_accesses 65194650 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 2495189 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2495189 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 165997 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 157094 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 323091 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 44921 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 51888 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 96809 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 41742 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 58696 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 100438 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 7485 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3707 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 366128 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 471159 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 250331 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 11134 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5196 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 423879 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 535784 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 283571 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 2358374 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 108961 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 126093 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 235054 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 7485 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3707 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 366128 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 512901 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 250331 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 11134 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5196 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 423879 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 594480 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 283571 # number of demand (read+write) hits +system.l2c.demand_hits::total 2458812 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 7485 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3707 # number of overall hits +system.l2c.overall_hits::cpu0.inst 366128 # number of overall hits +system.l2c.overall_hits::cpu0.data 512901 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 250331 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 11134 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5196 # number of overall hits +system.l2c.overall_hits::cpu1.inst 423879 # number of overall hits +system.l2c.overall_hits::cpu1.data 594480 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 283571 # number of overall hits +system.l2c.overall_hits::total 2458812 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 21704 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 22525 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 44229 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 639 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 868 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1507 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 68872 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 49716 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 118588 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 981 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 934 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 45283 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 111817 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 200821 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1691 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1806 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 46161 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 105560 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 172390 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 687444 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 412236 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu1.data 90358 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 502594 # number of InvalidateReq misses +system.l2c.demand_misses::cpu0.dtb.walker 981 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 934 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 45283 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 180689 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 200821 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 1691 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1806 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 46161 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 155276 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 172390 # number of demand (read+write) misses +system.l2c.demand_misses::total 806032 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 981 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 934 # number of overall misses +system.l2c.overall_misses::cpu0.inst 45283 # number of overall misses +system.l2c.overall_misses::cpu0.data 180689 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 200821 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 1691 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1806 # number of overall misses +system.l2c.overall_misses::cpu1.inst 46161 # number of overall misses +system.l2c.overall_misses::cpu1.data 155276 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 172390 # number of overall misses +system.l2c.overall_misses::total 806032 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 123357500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 137680500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 261038000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 7905500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 10002000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 17907500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 7461780500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 5660273500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 13122054000 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 100552000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 104158000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5195669500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 12454113000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 27350729041 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 176942500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 186194000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 5476488000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 12376112000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 22911003373 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 86331961414 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 100552000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 104158000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 5195669500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 19915893500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 27350729041 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 176942500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 186194000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 5476488000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 18036385500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 22911003373 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 99454015414 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 100552000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 104158000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 5195669500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 19915893500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 27350729041 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 176942500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 186194000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 5476488000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 18036385500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 22911003373 # number of overall miss cycles +system.l2c.overall_miss_latency::total 99454015414 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 2495189 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 2495189 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 187701 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 179619 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 367320 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 45560 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 52756 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 98316 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 110614 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 108412 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 219026 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8466 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 4641 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 411411 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 582976 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 451152 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 12825 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7002 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 470040 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 641344 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 455961 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 3045818 # number of ReadSharedReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu0.data 521197 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu1.data 216451 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::total 737648 # number of InvalidateReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8466 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 4641 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 411411 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 693590 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 451152 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 12825 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7002 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 470040 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 749756 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 455961 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3264844 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8466 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 4641 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 411411 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 693590 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 451152 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 12825 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7002 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 470040 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 749756 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 455961 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3264844 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.115631 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.125404 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.120410 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.014025 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.016453 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.015328 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.622634 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.458584 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.541433 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.115875 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.201250 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.110068 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.191804 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.445129 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.131852 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.257926 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.098207 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.164592 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.378081 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.225701 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.790941 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu1.data 0.417452 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.681347 # miss rate for InvalidateReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.115875 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.201250 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.110068 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.260513 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.445129 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.131852 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.257926 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.098207 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.207102 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.378081 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.246882 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.115875 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.201250 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.110068 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.260513 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.445129 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.131852 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.257926 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.098207 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.207102 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.378081 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.246882 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5683.629746 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6112.341842 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 5901.964774 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 12371.674491 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11523.041475 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 11882.879894 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 108342.729992 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 113852.150213 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 110652.460620 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 102499.490316 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 111518.201285 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 114737.749266 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 111379.423522 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 136194.566509 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 104637.788291 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 103097.452935 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 118638.850978 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 117242.440318 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 132902.160061 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 125583.991444 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 102499.490316 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 111518.201285 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 114737.749266 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 110221.947656 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 136194.566509 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 104637.788291 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 103097.452935 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 118638.850978 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 116156.943121 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132902.160061 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 123387.179931 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 102499.490316 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 111518.201285 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 114737.749266 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 110221.947656 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 136194.566509 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 104637.788291 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 103097.452935 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 118638.850978 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 116156.943121 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132902.160061 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 123387.179931 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 70 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 3 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 71 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 23.333333 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 1061178 # number of writebacks -system.l2c.writebacks::total 1061178 # number of writebacks -system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 79 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0.data 77 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 76 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.data 37 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 269 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 79 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 77 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 76 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 37 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 269 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 79 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 77 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 76 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 37 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 269 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 55507 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 55507 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 21760 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 23268 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 45028 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 910 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 658 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1568 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 75776 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 50200 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 125976 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1546 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1542 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 53116 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 142520 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 239651 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2105 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2105 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 39528 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 101593 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 169145 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 752851 # number of ReadSharedReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::cpu0.data 431914 # number of InvalidateReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::cpu1.data 78834 # number of InvalidateReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::total 510748 # number of InvalidateReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 1546 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 1542 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 53116 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 218296 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 239651 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 2105 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 2105 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 39528 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 151793 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 169145 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 878827 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 1546 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 1542 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 53116 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 218296 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 239651 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 2105 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 2105 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 39528 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 151793 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 169145 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 878827 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 29828 # number of ReadReq MSHR uncacheable +system.l2c.writebacks::writebacks 1000492 # number of writebacks +system.l2c.writebacks::total 1000492 # number of writebacks +system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 125 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0.data 495 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher 3 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 176 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.data 174 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.l2cache.prefetcher 1 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 975 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 125 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 495 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 176 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 174 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 975 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 125 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 495 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 176 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 174 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 975 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 48951 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 48951 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 21704 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 22525 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 44229 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 639 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 868 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1507 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 68872 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 49716 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 118588 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 981 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 934 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 45158 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 111322 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 200818 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1690 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1806 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 45985 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 105386 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 172389 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 686469 # number of ReadSharedReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::cpu0.data 412236 # number of InvalidateReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::cpu1.data 90358 # number of InvalidateReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::total 502594 # number of InvalidateReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 981 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 934 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 45158 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 180194 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 200818 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 1690 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1806 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 45985 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 155102 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 172389 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 805057 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 981 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 934 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 45158 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 180194 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 200818 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 1690 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1806 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 45985 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 155102 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 172389 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 805057 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 4725 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 15891 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 8722 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 81785 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 29359 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 9055 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 38414 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 59187 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 22370 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 43096 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16800 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 21343 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 38143 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 4725 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 32691 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 17777 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 120199 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 441512500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 483331000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 924843500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22384000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 16407000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 38791000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7434596046 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4997490093 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 12432086139 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 140998500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 140574501 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5355219542 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14279847185 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 30067523219 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 194506509 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 196268502 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 4312153532 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 10767710172 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 20750290788 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 86205092450 # number of ReadSharedReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8509679500 # number of InvalidateReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1503443500 # number of InvalidateReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::total 10013123000 # number of InvalidateReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 140998500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 140574501 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 5355219542 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 21714443231 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 30067523219 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 194506509 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 196268502 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 4312153532 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 15765200265 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 20750290788 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 98637178589 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 140998500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 140574501 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 5355219542 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 21714443231 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 30067523219 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 194506509 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 196268502 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 4312153532 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 15765200265 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 20750290788 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 98637178589 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3016846000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4911881502 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 8111000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1045413500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 8982252002 # number of ReadReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3016846000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4911881502 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 8111000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1045413500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 8982252002 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 43713 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 81239 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 437084000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 466716500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 903800500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 15328000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 21488000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 36816000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6773036549 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5163079069 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 11936115618 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 90742000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 94817501 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 4733313024 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 11297480109 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 25342213838 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 159957502 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 168133501 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5000535031 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 11306213655 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 21186861799 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 79380267960 # number of ReadSharedReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8132910000 # number of InvalidateReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1724009500 # number of InvalidateReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::total 9856919500 # number of InvalidateReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 90742000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 94817501 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 4733313024 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 18070516658 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 25342213838 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 159957502 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 168133501 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 5000535031 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 16469292724 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 21186861799 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 91316383578 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 90742000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 94817501 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 4733313024 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 18070516658 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 25342213838 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 159957502 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 168133501 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 5000535031 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 16469292724 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 21186861799 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 91316383578 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 343198000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2516105003 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7788000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3411021500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6278112503 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 343198000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2516105003 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7788000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3411021500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 6278112503 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.109628 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.129863 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.119228 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.018606 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.012489 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.015434 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.624905 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.450366 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541308 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.148070 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.286991 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.119931 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.217934 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.485468 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.155042 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.266963 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.085217 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.159232 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.372521 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.236471 # mshr miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.793801 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.380093 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::total 0.679624 # mshr miss rate for InvalidateReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.148070 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.286991 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.119931 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.281593 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.485468 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.155042 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.266963 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.085217 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.202530 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.372521 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.257236 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.148070 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.286991 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.119931 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.281593 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.485468 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.155042 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.266963 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.085217 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.202530 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.372521 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.257236 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20290.096507 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20772.348289 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20539.297770 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24597.802198 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24934.650456 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24739.158163 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98112.806773 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99551.595478 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 98686.147671 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 91202.134541 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 91163.749027 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 100821.212855 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 100195.391419 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 125463.792010 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 92402.142043 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93239.193349 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 109091.113439 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 105988.701702 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122677.529859 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114504.852155 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19702.254384 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19071.003628 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19604.820773 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 91202.134541 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 91163.749027 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 100821.212855 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99472.474214 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 125463.792010 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 92402.142043 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93239.193349 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 109091.113439 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 103859.863531 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122677.529859 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 112237.310175 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 91202.134541 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 91163.749027 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 100821.212855 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99472.474214 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 125463.792010 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 92402.142043 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93239.193349 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 109091.113439 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 103859.863531 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122677.529859 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 112237.310175 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164673.511533 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 73736.363636 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 119859.378583 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 109827.621226 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82989.195296 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 73736.363636 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 58807.082185 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 74728.175792 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 3514896 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2065226 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3253 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.115631 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.125404 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.120410 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.014025 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.016453 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.015328 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.622634 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.458584 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541433 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.115875 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.201250 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.109764 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.190955 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.445123 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.131774 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.257926 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.097832 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.164321 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.378078 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.225381 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.790941 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.417452 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.681347 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.115875 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.201250 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.109764 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.259799 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.445123 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.131774 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.257926 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.097832 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.206870 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.378078 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.246584 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.115875 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.201250 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.109764 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.259799 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.445123 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.131774 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.257926 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.097832 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.206870 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.378078 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.246584 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20138.407667 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20719.933407 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20434.567817 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 23987.480438 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24755.760369 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24429.993364 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98342.382231 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 103851.457660 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 100651.968310 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 92499.490316 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 101517.667024 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 104816.710749 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 101484.703015 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 126194.931918 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 94649.409467 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93097.176633 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 108742.742873 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 107283.829493 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122901.471666 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 115635.619321 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19728.771869 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19079.766042 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19612.091469 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 92499.490316 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 101517.667024 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 104816.710749 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 100283.675694 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 126194.931918 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 94649.409467 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93097.176633 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 108742.742873 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 106183.625769 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122901.471666 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 113428.469758 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 92499.490316 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 101517.667024 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 104816.710749 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 100283.675694 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 126194.931918 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 94649.409467 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93097.176633 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 108742.742873 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 106183.625769 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122901.471666 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 113428.469758 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 72634.497354 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158335.221383 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70800 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152481.962450 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 145677.383121 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 72634.497354 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 76966.290508 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70800 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 78032.198659 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 77279.539421 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3361893 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1995718 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3092 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 81785 # Transaction distribution -system.membus.trans_dist::ReadResp 843578 # Transaction distribution -system.membus.trans_dist::WriteReq 38414 # Transaction distribution -system.membus.trans_dist::WriteResp 38414 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1167872 # Transaction distribution -system.membus.trans_dist::CleanEvict 225685 # Transaction distribution -system.membus.trans_dist::UpgradeReq 305919 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 282864 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 43096 # Transaction distribution +system.membus.trans_dist::ReadResp 738496 # Transaction distribution +system.membus.trans_dist::WriteReq 38143 # Transaction distribution +system.membus.trans_dist::WriteResp 38143 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1107186 # Transaction distribution +system.membus.trans_dist::CleanEvict 202416 # Transaction distribution +system.membus.trans_dist::UpgradeReq 304555 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 296744 # Transaction distribution system.membus.trans_dist::UpgradeResp 23 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 142258 # Transaction distribution -system.membus.trans_dist::ReadExResp 125306 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 761793 # Transaction distribution -system.membus.trans_dist::InvalidateReq 628104 # Transaction distribution -system.membus.trans_dist::InvalidateResp 29933 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122692 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution +system.membus.trans_dist::ReadExReq 135023 # Transaction distribution +system.membus.trans_dist::ReadExResp 117908 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 695400 # Transaction distribution +system.membus.trans_dist::InvalidateReq 620101 # Transaction distribution +system.membus.trans_dist::InvalidateResp 29545 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122272 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26016 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4252247 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4401047 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238098 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238098 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4639145 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155799 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25316 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3948606 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4096286 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238208 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238208 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4334494 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155379 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52032 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124265196 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 124473231 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7264320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7264320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 131737551 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 601899 # Total snoops (count) -system.membus.snoopTraffic 182272 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2241138 # Request fanout histogram -system.membus.snoop_fanout::mean 0.014818 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.120825 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50632 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 115505708 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 115711923 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7271808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7271808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 122983731 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 615067 # Total snoops (count) +system.membus.snoopTraffic 174144 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2133066 # Request fanout histogram +system.membus.snoop_fanout::mean 0.015313 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.122793 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2207928 98.52% 98.52% # Request fanout histogram -system.membus.snoop_fanout::1 33210 1.48% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2100403 98.47% 98.47% # Request fanout histogram +system.membus.snoop_fanout::1 32663 1.53% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2241138 # Request fanout histogram -system.membus.reqLayer0.occupancy 100391998 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2133066 # Request fanout histogram +system.membus.reqLayer0.occupancy 100156000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21648500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21088500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7995026443 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7525887071 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4845345366 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4366874131 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 80706575 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 80052408 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3291,78 +3325,78 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 10666038 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5633070 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2010769 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 207058 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 187933 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 19125 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405080882500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 81787 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4013883 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38414 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38414 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3649317 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2329332 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 637884 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 382893 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1020777 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 101 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 286710 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 286710 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 3932744 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 861229 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 844497 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8425616 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7143072 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15568688 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 207061181 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 177741330 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 384802511 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2851175 # Total snoops (count) -system.toL2Bus.snoopTraffic 119274320 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 7603509 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.379635 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.490452 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 10343091 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5462203 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1986792 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 195863 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 175744 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 20119 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 43098 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3851068 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38143 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38143 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3495681 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2217175 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 626966 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 393553 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1020519 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 123 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 123 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 273712 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 273712 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 3808446 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 849023 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 832010 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7676666 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7311446 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 14988112 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 187677530 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 181320537 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 368998067 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2787811 # Total snoops (count) +system.toL2Bus.snoopTraffic 116317008 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 7322753 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.391714 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.493730 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4736073 62.29% 62.29% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 2848311 37.46% 99.75% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 19125 0.25% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4474450 61.10% 61.10% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2828184 38.62% 99.73% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 20119 0.27% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7603509 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8403909954 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 7322753 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8114772770 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 9629111 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 9310827 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3830991948 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3511032286 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3536553815 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3606444627 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index 9261f2548..69f18b388 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.821872 # Number of seconds simulated -sim_ticks 51821872017500 # Number of ticks simulated -final_tick 51821872017500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.818011 # Number of seconds simulated +sim_ticks 51818010617500 # Number of ticks simulated +final_tick 51818010617500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1130306 # Simulator instruction rate (inst/s) -host_op_rate 1328204 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68135685678 # Simulator tick rate (ticks/s) -host_mem_usage 679252 # Number of bytes of host memory used -host_seconds 760.57 # Real time elapsed on the host -sim_insts 859675526 # Number of instructions simulated -sim_ops 1010190283 # Number of ops (including micro ops) simulated +host_inst_rate 1170120 # Simulator instruction rate (inst/s) +host_op_rate 1392764 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73119251351 # Simulator tick rate (ticks/s) +host_mem_usage 679172 # Number of bytes of host memory used +host_seconds 708.68 # Real time elapsed on the host +sim_insts 829238196 # Number of instructions simulated +sim_ops 987021276 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 215360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 217216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5027508 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 42852104 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 396352 # Number of bytes read from this memory -system.physmem.bytes_read::total 48708540 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5027508 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5027508 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 69916032 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 290880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 276800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5155828 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 53423624 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 392768 # Number of bytes read from this memory +system.physmem.bytes_read::total 59539900 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5155828 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5155828 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 81086784 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 69936612 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 3365 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3394 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 118962 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 669577 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6193 # Number of read requests responded to by this memory -system.physmem.num_reads::total 801491 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1092438 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 81107364 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 4545 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 4325 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 84967 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 834757 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6137 # Number of read requests responded to by this memory +system.physmem.num_reads::total 934731 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1266981 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1095011 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 4156 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 4192 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 97015 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 826912 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 939922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 97015 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 97015 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1349161 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1269554 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 5613 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 5342 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 99499 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1030986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7580 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1149019 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 99499 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 99499 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1564838 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1349558 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1349161 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 4156 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 4192 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 97015 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 827309 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2289480 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 801491 # Number of read requests accepted -system.physmem.writeReqs 1095011 # Number of write requests accepted -system.physmem.readBursts 801491 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1095011 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 51258176 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 37248 # Total number of bytes read from write queue -system.physmem.bytesWritten 69934720 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 48708540 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 69936612 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 582 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2264 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1565235 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1564838 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 5613 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 5342 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 99499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1031383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7580 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2714254 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 934731 # Number of read requests accepted +system.physmem.writeReqs 1269554 # Number of write requests accepted +system.physmem.readBursts 934731 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1269554 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 59774080 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 48704 # Total number of bytes read from write queue +system.physmem.bytesWritten 81104832 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 59539900 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 81107364 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 761 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2263 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 50792 # Per bank write bursts -system.physmem.perBankRdBursts::1 52585 # Per bank write bursts -system.physmem.perBankRdBursts::2 45494 # Per bank write bursts -system.physmem.perBankRdBursts::3 47583 # Per bank write bursts -system.physmem.perBankRdBursts::4 47505 # Per bank write bursts -system.physmem.perBankRdBursts::5 55338 # Per bank write bursts -system.physmem.perBankRdBursts::6 45272 # Per bank write bursts -system.physmem.perBankRdBursts::7 44194 # Per bank write bursts -system.physmem.perBankRdBursts::8 47329 # Per bank write bursts -system.physmem.perBankRdBursts::9 89850 # Per bank write bursts -system.physmem.perBankRdBursts::10 47381 # Per bank write bursts -system.physmem.perBankRdBursts::11 49509 # Per bank write bursts -system.physmem.perBankRdBursts::12 42888 # Per bank write bursts -system.physmem.perBankRdBursts::13 45239 # Per bank write bursts -system.physmem.perBankRdBursts::14 44185 # Per bank write bursts -system.physmem.perBankRdBursts::15 45765 # Per bank write bursts -system.physmem.perBankWrBursts::0 68303 # Per bank write bursts -system.physmem.perBankWrBursts::1 72266 # Per bank write bursts -system.physmem.perBankWrBursts::2 69005 # Per bank write bursts -system.physmem.perBankWrBursts::3 70230 # Per bank write bursts -system.physmem.perBankWrBursts::4 67390 # Per bank write bursts -system.physmem.perBankWrBursts::5 74059 # Per bank write bursts -system.physmem.perBankWrBursts::6 66126 # Per bank write bursts -system.physmem.perBankWrBursts::7 65521 # Per bank write bursts -system.physmem.perBankWrBursts::8 69259 # Per bank write bursts -system.physmem.perBankWrBursts::9 70740 # Per bank write bursts -system.physmem.perBankWrBursts::10 68902 # Per bank write bursts -system.physmem.perBankWrBursts::11 68447 # Per bank write bursts -system.physmem.perBankWrBursts::12 64485 # Per bank write bursts -system.physmem.perBankWrBursts::13 66687 # Per bank write bursts -system.physmem.perBankWrBursts::14 65337 # Per bank write bursts -system.physmem.perBankWrBursts::15 65973 # Per bank write bursts +system.physmem.perBankRdBursts::0 59992 # Per bank write bursts +system.physmem.perBankRdBursts::1 60310 # Per bank write bursts +system.physmem.perBankRdBursts::2 57698 # Per bank write bursts +system.physmem.perBankRdBursts::3 58037 # Per bank write bursts +system.physmem.perBankRdBursts::4 57948 # Per bank write bursts +system.physmem.perBankRdBursts::5 67620 # Per bank write bursts +system.physmem.perBankRdBursts::6 56261 # Per bank write bursts +system.physmem.perBankRdBursts::7 53370 # Per bank write bursts +system.physmem.perBankRdBursts::8 54837 # Per bank write bursts +system.physmem.perBankRdBursts::9 66514 # Per bank write bursts +system.physmem.perBankRdBursts::10 61956 # Per bank write bursts +system.physmem.perBankRdBursts::11 59662 # Per bank write bursts +system.physmem.perBankRdBursts::12 55006 # Per bank write bursts +system.physmem.perBankRdBursts::13 54479 # Per bank write bursts +system.physmem.perBankRdBursts::14 55622 # Per bank write bursts +system.physmem.perBankRdBursts::15 54658 # Per bank write bursts +system.physmem.perBankWrBursts::0 77492 # Per bank write bursts +system.physmem.perBankWrBursts::1 79625 # Per bank write bursts +system.physmem.perBankWrBursts::2 80003 # Per bank write bursts +system.physmem.perBankWrBursts::3 79967 # Per bank write bursts +system.physmem.perBankWrBursts::4 79681 # Per bank write bursts +system.physmem.perBankWrBursts::5 86821 # Per bank write bursts +system.physmem.perBankWrBursts::6 77332 # Per bank write bursts +system.physmem.perBankWrBursts::7 76109 # Per bank write bursts +system.physmem.perBankWrBursts::8 76222 # Per bank write bursts +system.physmem.perBankWrBursts::9 83393 # Per bank write bursts +system.physmem.perBankWrBursts::10 81152 # Per bank write bursts +system.physmem.perBankWrBursts::11 79739 # Per bank write bursts +system.physmem.perBankWrBursts::12 76657 # Per bank write bursts +system.physmem.perBankWrBursts::13 78391 # Per bank write bursts +system.physmem.perBankWrBursts::14 77174 # Per bank write bursts +system.physmem.perBankWrBursts::15 77505 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 520 # Number of times write queue was full causing retry -system.physmem.totGap 51821869155500 # Total gap between requests +system.physmem.numWrRetry 469 # Number of times write queue was full causing retry +system.physmem.totGap 51818007690500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 43101 # Read request sizes (log2) +system.physmem.readPktSize::2 4701 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 758375 # Read request sizes (log2) +system.physmem.readPktSize::6 930015 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1092438 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 767476 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 27687 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 422 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 585 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 474 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 285 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 188 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 99 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1266981 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 899250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 28995 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 547 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 464 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 936 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 117 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 101 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 80 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 70 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -160,185 +160,189 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 30627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 61921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 65097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 62233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60629 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 62549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 64813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 63194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 67249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 66047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62409 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 60534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 60374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 58755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 32926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 37724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 68102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 72474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 75844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 72834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 71244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 73203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 75560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 73943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 77939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 76725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 72934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 71213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 72289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 71241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 69956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 69529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1159 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 1043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 1037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 1136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1603 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1058 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 494423 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 245.119212 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 147.459226 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 287.994040 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 219027 44.30% 44.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 131709 26.64% 70.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 43564 8.81% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 22937 4.64% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15466 3.13% 87.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9602 1.94% 89.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7396 1.50% 90.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5862 1.19% 92.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 38860 7.86% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 494423 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 57152 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.013543 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 134.391751 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 57148 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 57152 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 57152 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.119716 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.362666 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.513001 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 44632 78.09% 78.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 9484 16.59% 94.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 590 1.03% 95.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 287 0.50% 96.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 876 1.53% 97.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 130 0.23% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 106 0.19% 98.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 28 0.05% 98.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 52 0.09% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 20 0.03% 98.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 16 0.03% 98.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 48 0.08% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 542 0.95% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 77 0.13% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 52 0.09% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 79 0.14% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 35 0.06% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.00% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.01% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.00% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 16 0.03% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.00% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 9 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 18 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 7 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 11 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 4 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::40 900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 1096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1035 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 576881 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 244.207370 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 147.656879 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 284.643014 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 255111 44.22% 44.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 152646 26.46% 70.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 51224 8.88% 79.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 27873 4.83% 84.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18823 3.26% 87.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12144 2.11% 89.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9162 1.59% 91.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7710 1.34% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 42188 7.31% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 576881 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 67805 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 13.773807 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 23.890121 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 67793 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 5 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 3 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5120-5375 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 67805 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 67805 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.689816 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.049494 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.758455 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 55088 81.24% 81.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 9632 14.21% 95.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 629 0.93% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 315 0.46% 96.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 880 1.30% 98.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 141 0.21% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 113 0.17% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 35 0.05% 98.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 64 0.09% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 15 0.02% 98.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 17 0.03% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 38 0.06% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 506 0.75% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 74 0.11% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 50 0.07% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 77 0.11% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 34 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.00% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.00% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 7 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.00% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 13 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 4 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 19 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 9 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 6 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::180-183 2 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::184-187 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 3 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::196-199 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 57152 # Writes before turning the bus around for reads -system.physmem.totQLat 29342800943 # Total ticks spent queuing -system.physmem.totMemAccLat 44359844693 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4004545000 # Total ticks spent in databus transfers -system.physmem.avgQLat 36636.87 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-235 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 67805 # Writes before turning the bus around for reads +system.physmem.totQLat 32840058772 # Total ticks spent queuing +system.physmem.totMemAccLat 50351996272 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4669850000 # Total ticks spent in databus transfers +system.physmem.avgQLat 35161.79 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 55386.87 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.99 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.35 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.94 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.35 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 53911.79 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.15 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.15 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.29 # Average write queue length when enqueuing -system.physmem.readRowHits 600164 # Number of row buffer hits during reads -system.physmem.writeRowHits 799051 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.94 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.12 # Row buffer hit rate for writes -system.physmem.avgGap 27324974.69 # Average gap between requests -system.physmem.pageHitRate 73.89 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1814238300 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 964290525 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2775767820 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 2886138000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 48823313760.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 38608999590 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 3011693280 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 94024683450 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 72592857120 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 12330153384360 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 12595677850665 # Total energy per rank (pJ) -system.physmem_0.averagePower 243.057176 # Core power per rank (mW) -system.physmem_0.totalIdleTime 51728729641480 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 5702683750 # Time in different power states -system.physmem_0.memoryStateTime::REF 20763204000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 51334071775500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 189043780464 # Time in different power states -system.physmem_0.memoryStateTime::ACT 66096536270 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 206194037516 # Time in different power states -system.physmem_1.actEnergy 1715949060 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 912044760 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2942722440 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 2817912600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 46334636400.000008 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 38117726280 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2754271680 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 87558235230 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 69416939040 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 12335402832360 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 12587993852010 # Total energy per rank (pJ) -system.physmem_1.averagePower 242.908898 # Core power per rank (mW) -system.physmem_1.totalIdleTime 51731061753764 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 5083631742 # Time in different power states -system.physmem_1.memoryStateTime::REF 19704542000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 51358275119250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 180773350699 # Time in different power states -system.physmem_1.memoryStateTime::ACT 66022048244 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 192013325565 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing +system.physmem.readRowHits 700734 # Number of row buffer hits during reads +system.physmem.writeRowHits 923617 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.03 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.88 # Row buffer hit rate for writes +system.physmem.avgGap 23507852.97 # Average gap between requests +system.physmem.pageHitRate 73.79 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2121758100 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1127741175 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3364625040 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3325296600 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 53356283760.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 43527513060 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 3305473920 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 105977484840 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 78284868000 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 12316974110865 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 12611384893410 # Total energy per rank (pJ) +system.physmem_0.averagePower 243.378407 # Core power per rank (mW) +system.physmem_0.totalIdleTime 51713320513020 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 6156853750 # Time in different power states +system.physmem_0.memoryStateTime::REF 22684760000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 51277629948750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 203866794298 # Time in different power states +system.physmem_0.memoryStateTime::ACT 75265891230 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 232406369472 # Time in different power states +system.physmem_1.actEnergy 1997179380 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1061522220 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3303920760 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3289816260 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 51035403120.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 42719469090 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3040212960 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 99255699990 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 75177553440 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 12322732679115 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 12603635909925 # Total energy per rank (pJ) +system.physmem_1.averagePower 243.228865 # Core power per rank (mW) +system.physmem_1.totalIdleTime 51716360660558 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 5564281492 # Time in different power states +system.physmem_1.memoryStateTime::REF 21699622000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 51302919507000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 195774926499 # Time in different power states +system.physmem_1.memoryStateTime::ACT 74386011700 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 217666268809 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -355,9 +359,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -365,7 +369,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -395,75 +399,75 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 196189 # Table walker walks requested -system.cpu.dtb.walker.walksLong 196189 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 13637 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 152377 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 216211 # Table walker walks requested +system.cpu.dtb.walker.walksLong 216211 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16346 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 167307 # Level at which table walker walks with long descriptors terminate system.cpu.dtb.walker.walksSquashedBefore 19 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 196170 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 0.152929 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 48.843369 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-2047 196168 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::samples 216192 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 0.138766 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 46.526694 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-2047 216190 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::16384-18431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 196170 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 166033 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 23680.132865 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 19678.566540 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 19257.699461 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 164361 98.99% 98.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 1402 0.84% 99.84% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 64 0.04% 99.88% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 64 0.04% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 59 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 17 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 9 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 48 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkWaitTime::total 216192 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 183672 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 24269.346988 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 20148.872722 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 20272.280127 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 181570 98.86% 98.86% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 1738 0.95% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 90 0.05% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 74 0.04% 99.89% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 86 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 33 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 8 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 8 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 59 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 166033 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples -7075428332 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.933158 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.249747 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 -472932796 6.68% 6.68% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::1 -6602495536 93.32% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total -7075428332 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 152378 91.79% 91.79% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 13637 8.21% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 166015 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 196189 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkCompletionTime::total 183672 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 2036554556 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.701695 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.457514 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 607514500 29.83% 29.83% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::1 1429040056 70.17% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 2036554556 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 167308 91.10% 91.10% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 16346 8.90% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 183654 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 216211 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 196189 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 166015 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 216211 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 183654 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 166015 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 362204 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 183654 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 399865 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 161617169 # DTB read hits -system.cpu.dtb.read_misses 145721 # DTB read misses -system.cpu.dtb.write_hits 146821389 # DTB write hits -system.cpu.dtb.write_misses 50468 # DTB write misses +system.cpu.dtb.read_hits 169128390 # DTB read hits +system.cpu.dtb.read_misses 159496 # DTB read misses +system.cpu.dtb.write_hits 153929844 # DTB write hits +system.cpu.dtb.write_misses 56715 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 40242 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1033 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 72934 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb_mva_asid 43399 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1071 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 75955 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 7326 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 8791 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 19275 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 161762890 # DTB read accesses -system.cpu.dtb.write_accesses 146871857 # DTB write accesses +system.cpu.dtb.perms_faults 20041 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 169287886 # DTB read accesses +system.cpu.dtb.write_accesses 153986559 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 308438558 # DTB hits -system.cpu.dtb.misses 196189 # DTB misses -system.cpu.dtb.accesses 308634747 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 323058234 # DTB hits +system.cpu.dtb.misses 216211 # DTB misses +system.cpu.dtb.accesses 323274445 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -493,833 +497,831 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 120716 # Table walker walks requested -system.cpu.itb.walker.walksLong 120716 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1119 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 108836 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 120716 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 120716 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 120716 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 109955 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 27513.978446 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 23291.832317 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 24606.943327 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 107988 98.21% 98.21% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 1629 1.48% 99.69% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 80 0.07% 99.77% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 85 0.08% 99.84% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 60 0.05% 99.90% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 20 0.02% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 11 0.01% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 77 0.07% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 123370 # Table walker walks requested +system.cpu.itb.walker.walksLong 123370 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1116 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 111000 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 123370 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 123370 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 123370 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 112116 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 27477.773021 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 23151.580183 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 24996.246984 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 109776 97.91% 97.91% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 1925 1.72% 99.63% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 106 0.09% 99.72% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 116 0.10% 99.83% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 77 0.07% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 36 0.03% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 73 0.07% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 109955 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples -556629296 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 -556629296 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total -556629296 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 108836 98.98% 98.98% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1119 1.02% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 109955 # Table walker page sizes translated +system.cpu.itb.walker.walkCompletionTime::total 112116 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 523074000 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 523074000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 523074000 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 111000 99.00% 99.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1116 1.00% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 112116 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 120716 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 120716 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 123370 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 123370 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 109955 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 109955 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 230671 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 860205714 # ITB inst hits -system.cpu.itb.inst_misses 120716 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 112116 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 112116 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 235486 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 829831290 # ITB inst hits +system.cpu.itb.inst_misses 123370 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 40242 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1033 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 52133 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 43399 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1071 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 54054 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 860326430 # ITB inst accesses -system.cpu.itb.hits 860205714 # DTB hits -system.cpu.itb.misses 120716 # DTB misses -system.cpu.itb.accesses 860326430 # DTB accesses -system.cpu.numPwrStateTransitions 32324 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 16162 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3111484469.414615 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 60405660268.224297 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 6871 42.51% 42.51% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9256 57.27% 99.78% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 829954660 # ITB inst accesses +system.cpu.itb.hits 829831290 # DTB hits +system.cpu.itb.misses 123370 # DTB misses +system.cpu.itb.accesses 829954660 # DTB accesses +system.cpu.numPwrStateTransitions 32736 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 16368 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3071765118.618646 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 59759289847.266548 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 7078 43.24% 43.24% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9254 56.54% 99.78% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+10-1e+11 6 0.04% 99.82% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 1988775138696 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 16162 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 1534060022821 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50287811994679 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 103643744035 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::max_value 1988775098960 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 16368 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 1539359155950 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50278651461550 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 103636021235 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16162 # number of quiesce instructions executed -system.cpu.committedInsts 859675526 # Number of instructions committed -system.cpu.committedOps 1010190283 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 928076114 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 896946 # Number of float alu accesses -system.cpu.num_func_calls 51280324 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 130830869 # number of instructions that are conditional controls -system.cpu.num_int_insts 928076114 # number of integer instructions -system.cpu.num_fp_insts 896946 # number of float instructions -system.cpu.num_int_register_reads 1348653813 # number of times the integer registers were read -system.cpu.num_int_register_writes 735932841 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1446833 # number of times the floating registers were read -system.cpu.num_fp_register_writes 759084 # number of times the floating registers were written -system.cpu.num_cc_register_reads 224374440 # number of times the CC registers were read -system.cpu.num_cc_register_writes 223774216 # number of times the CC registers were written -system.cpu.num_mem_refs 308419372 # number of memory refs -system.cpu.num_load_insts 161608555 # Number of load instructions -system.cpu.num_store_insts 146810817 # Number of store instructions -system.cpu.num_idle_cycles 100575623989.356064 # Number of idle cycles -system.cpu.num_busy_cycles 3068120045.643941 # Number of busy cycles -system.cpu.not_idle_fraction 0.029603 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.970397 # Percentage of idle cycles -system.cpu.Branches 191908708 # Number of branches fetched +system.cpu.kern.inst.quiesce 16368 # number of quiesce instructions executed +system.cpu.committedInsts 829238196 # Number of instructions committed +system.cpu.committedOps 987021276 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 918155469 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 894809 # Number of float alu accesses +system.cpu.num_func_calls 53301366 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 119804511 # number of instructions that are conditional controls +system.cpu.num_int_insts 918155469 # number of integer instructions +system.cpu.num_fp_insts 894809 # number of float instructions +system.cpu.num_int_register_reads 1221916718 # number of times the integer registers were read +system.cpu.num_int_register_writes 717363924 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1441242 # number of times the floating registers were read +system.cpu.num_fp_register_writes 760964 # number of times the floating registers were written +system.cpu.num_cc_register_reads 183477837 # number of times the CC registers were read +system.cpu.num_cc_register_writes 182884399 # number of times the CC registers were written +system.cpu.num_mem_refs 323042928 # number of memory refs +system.cpu.num_load_insts 169122320 # Number of load instructions +system.cpu.num_store_insts 153920608 # Number of store instructions +system.cpu.num_idle_cycles 100557302923.098053 # Number of idle cycles +system.cpu.num_busy_cycles 3078718311.901940 # Number of busy cycles +system.cpu.not_idle_fraction 0.029707 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.970293 # Percentage of idle cycles +system.cpu.Branches 183328759 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 699966855 69.25% 69.25% # Class of executed instruction -system.cpu.op_class::IntMult 2168337 0.21% 69.47% # Class of executed instruction -system.cpu.op_class::IntDiv 97451 0.01% 69.48% # Class of executed instruction -system.cpu.op_class::FloatAdd 8 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::FloatCmp 13 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::FloatCvt 21 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction -system.cpu.op_class::FloatMisc 111537 0.01% 69.49% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::MemRead 161496118 15.98% 85.46% # Class of executed instruction -system.cpu.op_class::MemWrite 146137887 14.46% 99.92% # Class of executed instruction -system.cpu.op_class::FloatMemRead 112437 0.01% 99.93% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 672930 0.07% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 662135321 67.04% 67.04% # Class of executed instruction +system.cpu.op_class::IntMult 2232133 0.23% 67.27% # Class of executed instruction +system.cpu.op_class::IntDiv 98376 0.01% 67.28% # Class of executed instruction +system.cpu.op_class::FloatAdd 8 0.00% 67.28% # Class of executed instruction +system.cpu.op_class::FloatCmp 13 0.00% 67.28% # Class of executed instruction +system.cpu.op_class::FloatCvt 21 0.00% 67.28% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.28% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 67.28% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.28% # Class of executed instruction +system.cpu.op_class::FloatMisc 110293 0.01% 67.29% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.29% # Class of executed instruction +system.cpu.op_class::MemRead 169008582 17.11% 84.40% # Class of executed instruction +system.cpu.op_class::MemWrite 153249872 15.52% 99.92% # Class of executed instruction +system.cpu.op_class::FloatMemRead 113738 0.01% 99.93% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 670736 0.07% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1010763595 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9712819 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.962733 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 298526964 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9713331 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 30.733737 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 3801165500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.962733 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999927 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999927 # Average percentage of cache occupancy +system.cpu.op_class::total 987619094 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 10318810 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994503 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 312537175 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 10319322 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 30.286600 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 585910500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994503 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 407 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1243130616 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1243130616 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 151166129 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 151166129 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 139372457 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 139372457 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 383388 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 383388 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 333792 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 333792 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3475542 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3475542 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3766859 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3766859 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 290872378 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 290872378 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 291255766 # number of overall hits -system.cpu.dcache.overall_hits::total 291255766 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 5061632 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 5061632 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2072136 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2072136 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1203806 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1203806 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1225587 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1225587 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 292986 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 292986 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 8359355 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8359355 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9563161 # number of overall misses -system.cpu.dcache.overall_misses::total 9563161 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 86410296000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 86410296000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 64078644000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 64078644000 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 24971401500 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 24971401500 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4471115500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4471115500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 167500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 175460341500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 175460341500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 175460341500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 175460341500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 156227761 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 156227761 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 141444593 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 141444593 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1587194 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1587194 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1559379 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1559379 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3768528 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3768528 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3766861 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3766861 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 299231733 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 299231733 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 300818927 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 300818927 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032399 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032399 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014650 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.014650 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758449 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.758449 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.785946 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.785946 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.077745 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.077745 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.027936 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.027936 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.031790 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.031790 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17071.627491 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17071.627491 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30923.956729 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30923.956729 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 20375.054158 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 20375.054158 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15260.509035 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15260.509035 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83750 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83750 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20989.698547 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20989.698547 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18347.525625 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18347.525625 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 1302212841 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1302212841 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 157972571 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 157972571 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 146050984 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 146050984 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 397864 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 397864 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 335205 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 335205 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3722931 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3722931 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4027066 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4027066 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 304358760 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 304358760 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 304756624 # number of overall hits +system.cpu.dcache.overall_hits::total 304756624 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 5371907 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 5371907 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2231014 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2231014 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1323692 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1323692 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1234314 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1234314 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 305825 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 305825 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 8837235 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8837235 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 10160927 # number of overall misses +system.cpu.dcache.overall_misses::total 10160927 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 92847463000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 92847463000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 76601172000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 76601172000 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 25428557000 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 25428557000 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4806019500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4806019500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 83000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 83000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 194877192000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 194877192000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 194877192000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 194877192000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 163344478 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 163344478 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 148281998 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 148281998 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1721556 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1721556 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1569519 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1569519 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4028756 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4028756 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4027067 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4027067 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 313195995 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 313195995 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 314917551 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 314917551 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032887 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032887 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015046 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015046 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.768893 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.768893 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786428 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.786428 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.075911 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.075911 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.028216 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.028216 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032265 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032265 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17283.892480 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17283.892480 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34334.689070 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34334.689070 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 20601.368047 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 20601.368047 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15714.933377 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15714.933377 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22051.828655 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22051.828655 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19179.076082 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19179.076082 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 7496626 # number of writebacks -system.cpu.dcache.writebacks::total 7496626 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21661 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 21661 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21294 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 21294 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70691 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 70691 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 42955 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 42955 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 42955 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 42955 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5039971 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5039971 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2050842 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2050842 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1203452 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1203452 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1225587 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1225587 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 222295 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 222295 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 8316400 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 8316400 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9519852 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9519852 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 33706 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 67416 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 80495651000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 80495651000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61277537000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 61277537000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21572116000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21572116000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 23745814500 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 23745814500 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3066936500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3066936500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 165500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 165500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165519002500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 165519002500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187091118500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 187091118500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6232858500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6232858500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6232858500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6232858500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032260 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032260 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014499 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014499 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.758226 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.758226 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785946 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785946 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058987 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058987 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027793 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027793 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031646 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031646 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15971.451225 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15971.451225 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29879.209125 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29879.209125 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17925.198512 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17925.198512 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 19375.054158 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 19375.054158 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13796.695832 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13796.695832 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82750 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82750 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19902.722632 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19902.722632 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19652.733940 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19652.733940 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184918.367650 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184918.367650 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92453.697935 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92453.697935 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 13486266 # number of replacements -system.cpu.icache.tags.tagsinuse 511.886684 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 846718931 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 13486778 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 62.781409 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 32464203500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.886684 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999779 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999779 # Average percentage of cache occupancy +system.cpu.dcache.writebacks::writebacks 7954497 # number of writebacks +system.cpu.dcache.writebacks::total 7954497 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22835 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 22835 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21214 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 21214 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 72449 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 72449 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 44049 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 44049 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 44049 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 44049 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5349072 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5349072 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2209800 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2209800 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1323336 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1323336 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1234314 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1234314 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 233376 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 233376 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 8793186 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 8793186 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 10116522 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 10116522 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33620 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 33620 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33624 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 33624 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67244 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 67244 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86573126000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 86573126000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73656101500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 73656101500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23406113500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23406113500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 24194243000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 24194243000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3299673500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3299673500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 82000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 82000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 184423470500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 184423470500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207829584000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 207829584000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6212445000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6212445000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6212445000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6212445000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032747 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032747 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014903 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014903 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.768686 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.768686 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786428 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786428 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057928 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057928 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028076 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028076 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032124 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032124 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16184.700075 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16184.700075 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33331.569147 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33331.569147 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17687.203779 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17687.203779 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 19601.368047 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 19601.368047 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14138.872463 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14138.872463 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20973.452683 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20973.452683 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20543.580491 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20543.580491 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184784.205830 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184784.205830 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92386.606984 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92386.606984 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 13796932 # number of replacements +system.cpu.icache.tags.tagsinuse 511.918468 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 816033841 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 13797444 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.143841 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 29242894500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.918468 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999841 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999841 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 249 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 873692497 # Number of tag accesses -system.cpu.icache.tags.data_accesses 873692497 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 846718931 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 846718931 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 846718931 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 846718931 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 846718931 # number of overall hits -system.cpu.icache.overall_hits::total 846718931 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13486783 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13486783 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13486783 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13486783 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13486783 # number of overall misses -system.cpu.icache.overall_misses::total 13486783 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 183511474500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 183511474500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 183511474500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 183511474500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 183511474500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 183511474500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 860205714 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 860205714 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 860205714 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 860205714 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 860205714 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 860205714 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015679 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.015679 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.015679 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.015679 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.015679 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.015679 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13606.764082 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13606.764082 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13606.764082 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13606.764082 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13606.764082 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13606.764082 # average overall miss latency +system.cpu.icache.tags.tag_accesses 843628739 # Number of tag accesses +system.cpu.icache.tags.data_accesses 843628739 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 816033841 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 816033841 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 816033841 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 816033841 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 816033841 # number of overall hits +system.cpu.icache.overall_hits::total 816033841 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13797449 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13797449 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13797449 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13797449 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13797449 # number of overall misses +system.cpu.icache.overall_misses::total 13797449 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 188051577000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 188051577000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 188051577000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 188051577000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 188051577000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 188051577000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 829831290 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 829831290 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 829831290 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 829831290 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 829831290 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 829831290 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016627 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016627 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016627 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016627 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016627 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016627 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13629.445342 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13629.445342 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13629.445342 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13629.445342 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13629.445342 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13629.445342 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 13486266 # number of writebacks -system.cpu.icache.writebacks::total 13486266 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13486783 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 13486783 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 13486783 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 13486783 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 13486783 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 13486783 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable -system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable -system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170024691500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 170024691500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170024691500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 170024691500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170024691500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 170024691500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3557271000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3557271000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3557271000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 3557271000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015679 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015679 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015679 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.015679 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015679 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.015679 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12606.764082 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12606.764082 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12606.764082 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12606.764082 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12606.764082 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12606.764082 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82487.443478 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82487.443478 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82487.443478 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82487.443478 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1158711 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65407.211772 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 44429708 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1220523 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 36.402188 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6958052500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 10958.963563 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 463.658135 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 540.023475 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6661.801500 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46782.765099 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.167221 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.007075 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.008240 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101651 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.713848 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998035 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 301 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 61511 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 301 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 815 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5756 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54668 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004593 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.938583 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 377726834 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 377726834 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 307081 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 228330 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 535411 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 7496626 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 7496626 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 13484674 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 13484674 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 24887 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 24887 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1607168 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1607168 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13410909 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 13410909 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6209836 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6209836 # number of ReadSharedReq hits -system.cpu.l2cache.InvalidateReq_hits::cpu.data 727975 # number of InvalidateReq hits -system.cpu.l2cache.InvalidateReq_hits::total 727975 # number of InvalidateReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 307081 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 228330 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 13410909 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7817004 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 21763324 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 307081 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 228330 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 13410909 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7817004 # number of overall hits -system.cpu.l2cache.overall_hits::total 21763324 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3365 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3394 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 6759 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 3908 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 3908 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 414879 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 414879 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 75874 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 75874 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 255882 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 255882 # number of ReadSharedReq misses -system.cpu.l2cache.InvalidateReq_misses::cpu.data 497612 # number of InvalidateReq misses -system.cpu.l2cache.InvalidateReq_misses::total 497612 # number of InvalidateReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 3365 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 3394 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 75874 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 670761 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 753394 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 3365 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 3394 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 75874 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 670761 # number of overall misses -system.cpu.l2cache.overall_misses::total 753394 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 447362000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 421528500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 868890500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 69021500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 69021500 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40901099500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 40901099500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 8709565500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 8709565500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30155420000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 30155420000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 447362000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 421528500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 8709565500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 71056519500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 80634975500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 447362000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 421528500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 8709565500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 71056519500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 80634975500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 310446 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 231724 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 542170 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 7496626 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 7496626 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 13484674 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 13484674 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 28795 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 28795 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2022047 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2022047 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 13486783 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 13486783 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6465718 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 6465718 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1225587 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::total 1225587 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 310446 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 231724 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 13486783 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 8487765 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 22516718 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 310446 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 231724 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 13486783 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 8487765 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 22516718 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.010839 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.014647 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.012467 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.135718 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.135718 # miss rate for UpgradeReq accesses +system.cpu.icache.writebacks::writebacks 13796932 # number of writebacks +system.cpu.icache.writebacks::total 13796932 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13797449 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 13797449 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 13797449 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 13797449 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 13797449 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 13797449 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 4725 # number of ReadReq MSHR uncacheable +system.cpu.icache.ReadReq_mshr_uncacheable::total 4725 # number of ReadReq MSHR uncacheable +system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 4725 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::total 4725 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 174254128000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 174254128000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 174254128000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 174254128000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 174254128000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 174254128000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 399607000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 399607000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 399607000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 399607000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016627 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016627 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016627 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016627 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016627 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016627 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12629.445342 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12629.445342 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12629.445342 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12629.445342 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12629.445342 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12629.445342 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 84572.910053 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 84572.910053 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 84572.910053 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 84572.910053 # average overall mshr uncacheable latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 1351080 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65410.698207 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 46116668 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1414341 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 32.606470 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 3738142500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 9967.984706 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 437.366507 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 495.963757 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6246.445194 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48262.938042 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.152099 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006674 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007568 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.095313 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.736434 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998088 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 325 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 62936 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 325 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 808 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5758 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56089 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004959 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.960327 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 392953982 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 392953982 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 349715 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 229342 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 579057 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 7954497 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 7954497 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 13795341 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 13795341 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 26690 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 26690 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1630864 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1630864 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13717170 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 13717170 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6618229 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 6618229 # number of ReadSharedReq hits +system.cpu.l2cache.InvalidateReq_hits::cpu.data 717802 # number of InvalidateReq hits +system.cpu.l2cache.InvalidateReq_hits::total 717802 # number of InvalidateReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 349715 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 229342 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 13717170 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 8249093 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 22545320 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 349715 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 229342 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 13717170 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 8249093 # number of overall hits +system.cpu.l2cache.overall_hits::total 22545320 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 4545 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4325 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 8870 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 3863 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 3863 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 548383 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 548383 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 80279 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 80279 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 287555 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 287555 # number of ReadSharedReq misses +system.cpu.l2cache.InvalidateReq_misses::cpu.data 516512 # number of InvalidateReq misses +system.cpu.l2cache.InvalidateReq_misses::total 516512 # number of InvalidateReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 4545 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 4325 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 80279 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 835938 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 925087 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 4545 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 4325 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 80279 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 835938 # number of overall misses +system.cpu.l2cache.overall_misses::total 925087 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 594871500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 523671500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1118543000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 68752000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 68752000 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 80500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 80500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 52773795000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 52773795000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9248862500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 9248862500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33350772500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 33350772500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 594871500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 523671500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9248862500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 86124567500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 96491973000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 594871500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 523671500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9248862500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 86124567500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 96491973000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 354260 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 233667 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 587927 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 7954497 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 7954497 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 13795341 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 13795341 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 30553 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 30553 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2179247 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2179247 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 13797449 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 13797449 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6905784 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 6905784 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1234314 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::total 1234314 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 354260 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 233667 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 13797449 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9085031 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 23470407 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 354260 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 233667 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 13797449 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9085031 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 23470407 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012830 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.018509 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.015087 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.126436 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.126436 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.205178 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.205178 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005626 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005626 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.039575 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.039575 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.406019 # miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::total 0.406019 # miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.010839 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.014647 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005626 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.079027 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.033459 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.010839 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.014647 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005626 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.079027 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.033459 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 132945.616642 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 124198.143783 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 128553.114366 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17661.591607 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17661.591607 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 81250 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 81250 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98585.610503 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98585.610503 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 114789.855550 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 114789.855550 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 117848.930366 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 117848.930366 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 132945.616642 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 124198.143783 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 114789.855550 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 105934.184456 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 107028.958951 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 132945.616642 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 124198.143783 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 114789.855550 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 105934.184456 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 107028.958951 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.251639 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.251639 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005818 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005818 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.041640 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.041640 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.418461 # miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.418461 # miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012830 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.018509 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005818 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.092013 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.039415 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012830 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.018509 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005818 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.092013 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.039415 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 130884.818482 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 121080.115607 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 126104.058625 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17797.566658 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17797.566658 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80500 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80500 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96235.286287 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96235.286287 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 115208.989898 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 115208.989898 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 115980.499383 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 115980.499383 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 130884.818482 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 121080.115607 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 115208.989898 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 103027.458376 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 104305.836100 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 130884.818482 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 121080.115607 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 115208.989898 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 103027.458376 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 104305.836100 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 985808 # number of writebacks -system.cpu.l2cache.writebacks::total 985808 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3365 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3394 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 6759 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3908 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 3908 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 414879 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 414879 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 75874 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 75874 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 255882 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 255882 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 497612 # number of InvalidateReq MSHR misses -system.cpu.l2cache.InvalidateReq_mshr_misses::total 497612 # number of InvalidateReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3365 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3394 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 75874 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 670761 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 753394 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3365 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3394 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 75874 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 670761 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 753394 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 76831 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 110541 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 413712000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 387588500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 801300500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 74391500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 74391500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 142500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 142500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 36752309500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 36752309500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 7950825500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 7950825500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 27596583533 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 27596583533 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 9287554000 # number of InvalidateReq MSHR miss cycles -system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 9287554000 # number of InvalidateReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 413712000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 387588500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7950825500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 64348893033 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 73101019033 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 413712000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 387588500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7950825500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 64348893033 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 73101019033 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 3018208500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5810725500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8828934000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3018208500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5810725500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 8828934000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.010839 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.014647 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.012467 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.135718 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.135718 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.writebacks::writebacks 1160350 # number of writebacks +system.cpu.l2cache.writebacks::total 1160350 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 4545 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4325 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 8870 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3863 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 3863 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 548383 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 548383 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 80279 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 80279 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 287555 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 287555 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 516512 # number of InvalidateReq MSHR misses +system.cpu.l2cache.InvalidateReq_mshr_misses::total 516512 # number of InvalidateReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 4545 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4325 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 80279 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 835938 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 925087 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 4545 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4325 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 80279 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 835938 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 925087 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 4725 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33620 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 38345 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33624 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33624 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 4725 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67244 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 71969 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 549421500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 480421500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1029843000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 73648000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 73648000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 70500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 70500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 47289965000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 47289965000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8446072500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8446072500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30475204536 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30475204536 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 9640713000 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 9640713000 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 549421500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 480421500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8446072500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 77765169536 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 87241085036 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 549421500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 480421500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8446072500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 77765169536 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 87241085036 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 340544500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5791390500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6131935000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340544500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5791390500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6131935000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.012830 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018509 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015087 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.126436 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.126436 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.205178 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.205178 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005626 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005626 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.039575 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.039575 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.406019 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.406019 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.010839 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.014647 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005626 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.079027 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.033459 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.010839 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.014647 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005626 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.079027 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.033459 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 122945.616642 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 114198.143783 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 118553.114366 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19035.696008 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19035.696008 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88585.610503 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88585.610503 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 104789.855550 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 104789.855550 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 107848.866012 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 107848.866012 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 18664.248451 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 18664.248451 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 122945.616642 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 114198.143783 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 104789.855550 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 95934.159906 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 97028.937094 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 122945.616642 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 114198.143783 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 104789.855550 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 95934.159906 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 97028.937094 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69987.443478 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172394.395657 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114913.693691 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69987.443478 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86192.083482 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 79870.220099 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 46927036 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 23726903 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1749 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1976 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1976 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.251639 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.251639 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005818 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005818 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.041640 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.041640 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.418461 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.418461 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.012830 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018509 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005818 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.092013 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.039415 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.012830 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018509 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005818 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.092013 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.039415 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 120884.818482 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 111080.115607 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 116104.058625 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19064.975408 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19064.975408 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86235.286287 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86235.286287 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 105208.989898 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 105208.989898 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 105980.436911 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 105980.436911 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 18665.031984 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 18665.031984 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 120884.818482 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 111080.115607 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 105208.989898 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 93027.436886 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94305.816681 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 120884.818482 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 111080.115607 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 105208.989898 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 93027.436886 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94305.816681 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 72072.910053 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172260.276621 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 159914.852002 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 72072.910053 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86125.014871 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 85202.448276 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 48796648 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 24679855 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1750 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2089 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2089 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1011319 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 20964705 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8482434 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13486266 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2389096 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 28798 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 28800 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2022047 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2022047 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 13486783 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6468652 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1256381 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1225599 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40546082 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29332849 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 592477 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 884181 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 71355589 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1726447636 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1023248134 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1853792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2483568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2754033130 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1585660 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 66286896 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 25466403 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.019742 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.139111 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1038155 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 21742291 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33624 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33624 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 9114847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13796932 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2555043 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 30556 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 30557 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2179247 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2179247 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 13797449 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6908747 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1261981 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1234328 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41401280 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 31154016 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 602385 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 985352 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 74143033 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1766059284 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1090777710 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1869336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2834080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2861540410 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1794516 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 77615256 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 26600840 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.020202 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.140692 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 24963657 98.03% 98.03% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 502746 1.97% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 26063442 97.98% 97.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 537398 2.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 25466403 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 44736270000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 26600840 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 46435675500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1643382 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1669386 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 20273299500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 20700898500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13409418464 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14310442440 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 360753000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 368718000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 573735000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 631092000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40342 # Transaction distribution -system.iobus.trans_dist::ReadResp 40342 # Transaction distribution -system.iobus.trans_dist::WriteReq 136571 # Transaction distribution -system.iobus.trans_dist::WriteResp 136571 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40260 # Transaction distribution +system.iobus.trans_dist::ReadResp 40260 # Transaction distribution +system.iobus.trans_dist::WriteReq 136485 # Transaction distribution +system.iobus.trans_dist::WriteResp 136485 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47478 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -1332,13 +1334,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231042 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231042 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122360 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231050 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231050 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353826 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353490 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47498 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1351,13 +1353,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334600 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155490 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334632 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334632 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492520 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42151500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 41845500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1379,75 +1381,75 @@ system.iobus.reqLayer16.occupancy 17000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25717000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25729000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38602500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38606000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569022926 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569335764 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92542000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147802000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147810000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115502 # number of replacements -system.iocache.tags.tagsinuse 10.457099 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115507 # number of replacements +system.iocache.tags.tagsinuse 10.457942 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115518 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115523 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13154766854000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.510741 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.946357 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219421 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.434147 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653569 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13151557544000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.511326 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.946616 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219458 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434164 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653621 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040046 # Number of tag accesses -system.iocache.tags.data_accesses 1040046 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1040082 # Number of tag accesses +system.iocache.tags.data_accesses 1040082 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8857 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8894 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8861 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8898 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115521 # number of demand (read+write) misses -system.iocache.demand_misses::total 115561 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115525 # number of demand (read+write) misses +system.iocache.demand_misses::total 115565 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115521 # number of overall misses -system.iocache.overall_misses::total 115561 # number of overall misses +system.iocache.overall_misses::realview.ide 115525 # number of overall misses +system.iocache.overall_misses::total 115565 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5086500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 2023754150 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 2028840650 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1980781165 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1985867665 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13483489276 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13483489276 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13389793099 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13389793099 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5437500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15507243426 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15512680926 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15370574264 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15376011764 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5437500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15507243426 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15512680926 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15370574264 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15376011764 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8857 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8894 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8861 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8898 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115521 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115561 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115525 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115565 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115521 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115561 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115525 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115565 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1462,52 +1464,52 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137472.972973 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 228492.057130 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 228113.407915 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 223539.235414 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 223181.351427 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126410.872234 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126410.872234 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125532.448614 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125532.448614 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 134237.441037 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 134238.029491 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 133049.766406 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 133050.765924 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 134237.441037 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 134238.029491 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 52159 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 133049.766406 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 133050.765924 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 49780 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3349 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3342 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 15.574500 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 14.895272 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106630 # number of writebacks -system.iocache.writebacks::total 106630 # number of writebacks +system.iocache.writebacks::writebacks 106631 # number of writebacks +system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8857 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8894 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8861 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8898 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115521 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115561 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115525 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115565 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115521 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115561 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 115525 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115565 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1580904150 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1584140650 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1537731165 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1540967665 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8144739087 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8144739087 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8050946475 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8050946475 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3437500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9725643237 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9729080737 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9588677640 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9592115140 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3437500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9725643237 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9729080737 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9588677640 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9592115140 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1522,95 +1524,95 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87472.972973 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 178492.057130 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 178113.407915 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 173539.235414 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 173181.351427 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76358.837912 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76358.837912 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75479.510191 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75479.510191 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 84189.396188 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 84190.001272 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 83000.888466 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 83001.904902 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 84189.396188 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 84190.001272 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 2644146 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1308848 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3757 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.overall_avg_mshr_miss_latency::realview.ide 83000.888466 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 83001.904902 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 3026927 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1497963 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3722 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 76831 # Transaction distribution -system.membus.trans_dist::ReadResp 424240 # Transaction distribution -system.membus.trans_dist::WriteReq 33710 # Transaction distribution -system.membus.trans_dist::WriteResp 33710 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1092438 # Transaction distribution -system.membus.trans_dist::CleanEvict 180711 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4469 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 414321 # Transaction distribution -system.membus.trans_dist::ReadExResp 414321 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 347409 # Transaction distribution -system.membus.trans_dist::InvalidateReq 604276 # Transaction distribution -system.membus.trans_dist::InvalidateResp 30630 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 38345 # Transaction distribution +system.membus.trans_dist::ReadResp 423947 # Transaction distribution +system.membus.trans_dist::WriteReq 33624 # Transaction distribution +system.membus.trans_dist::WriteResp 33624 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1266981 # Transaction distribution +system.membus.trans_dist::CleanEvict 198449 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4422 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7 # Transaction distribution +system.membus.trans_dist::ReadExReq 547827 # Transaction distribution +system.membus.trans_dist::ReadExResp 547827 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 385602 # Transaction distribution +system.membus.trans_dist::InvalidateReq 623176 # Transaction distribution +system.membus.trans_dist::InvalidateResp 27559 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122360 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3256123 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3385827 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237256 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237256 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3623083 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3733842 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3863202 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237209 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237209 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4100411 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155490 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 111424480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 111594330 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7220672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7220672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 118815002 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 33993 # Total snoops (count) -system.membus.snoopTraffic 214720 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1481018 # Request fanout histogram -system.membus.snoop_fanout::mean 0.023235 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.150648 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 133430112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 133599618 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7217152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7217152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 140816770 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 30980 # Total snoops (count) +system.membus.snoopTraffic 218496 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1632997 # Request fanout histogram +system.membus.snoop_fanout::mean 0.019173 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.137134 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1446607 97.68% 97.68% # Request fanout histogram -system.membus.snoop_fanout::1 34411 2.32% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1601687 98.08% 98.08% # Request fanout histogram +system.membus.snoop_fanout::1 31310 1.92% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1481018 # Request fanout histogram -system.membus.reqLayer0.occupancy 106898000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1632997 # Request fanout histogram +system.membus.reqLayer0.occupancy 106607500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5816000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5784000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7183768776 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8217045206 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4201020680 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5023572568 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 76902808 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 73701370 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1653,28 +1655,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51818010617500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index bf75cb6d5..69b672058 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.062553 # Number of seconds simulated -sim_ticks 62553193500 # Number of ticks simulated -final_tick 62553193500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.062555 # Number of seconds simulated +sim_ticks 62555455500 # Number of ticks simulated +final_tick 62555455500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 434587 # Simulator instruction rate (inst/s) -host_op_rate 436752 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 300043763 # Simulator tick rate (ticks/s) -host_mem_usage 405580 # Number of bytes of host memory used -host_seconds 208.48 # Real time elapsed on the host +host_inst_rate 428742 # Simulator instruction rate (inst/s) +host_op_rate 430877 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 296018745 # Simulator tick rate (ticks/s) +host_mem_usage 404460 # Number of bytes of host memory used +host_seconds 211.32 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 49536 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 947264 # Number of bytes read from this memory -system.physmem.bytes_read::total 996736 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 49472 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 996800 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 49536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 49536 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 774 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14801 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 790879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15143336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15934214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 790879 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 790879 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 790879 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15143336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15934214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15574 # Number of read requests accepted +system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 791873 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15142788 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15934661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 791873 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 791873 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 791873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15142788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15934661 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15575 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 15575 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 996736 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 996800 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 996736 # Total read bytes from the system interface side +system.physmem.bytesReadSys 996800 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -48,7 +48,7 @@ system.physmem.perBankRdBursts::2 949 # Pe system.physmem.perBankRdBursts::3 1027 # Per bank write bursts system.physmem.perBankRdBursts::4 1050 # Per bank write bursts system.physmem.perBankRdBursts::5 1113 # Per bank write bursts -system.physmem.perBankRdBursts::6 1087 # Per bank write bursts +system.physmem.perBankRdBursts::6 1088 # Per bank write bursts system.physmem.perBankRdBursts::7 1088 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 62553092500 # Total gap between requests +system.physmem.totGap 62555354500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 15574 # Read request sizes (log2) +system.physmem.readPktSize::6 15575 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,7 +91,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 15454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 15455 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -189,24 +189,24 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 1540 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 646.524675 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 437.476336 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 402.605762 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 437.465548 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 402.658643 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 259 16.82% 16.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 178 11.56% 28.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 79 5.13% 33.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 177 11.49% 28.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 80 5.19% 33.51% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 62 4.03% 37.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 82 5.32% 42.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 81 5.26% 48.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 41 2.66% 50.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 66 4.29% 55.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 40 2.60% 50.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 67 4.35% 55.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 692 44.94% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation -system.physmem.totQLat 211075250 # Total ticks spent queuing -system.physmem.totMemAccLat 503087750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13553.05 # Average queueing delay per DRAM burst +system.physmem.totQLat 211097500 # Total ticks spent queuing +system.physmem.totMemAccLat 503128750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13553.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32303.05 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 32303.61 # Average memory access latency per DRAM burst system.physmem.avgRdBW 15.93 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.93 # Average system read bandwidth in MiByte/s @@ -217,66 +217,66 @@ system.physmem.busUtilRead 0.12 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14027 # Number of row buffer hits during reads +system.physmem.readRowHits 14028 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.07 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4016507.80 # Average gap between requests +system.physmem.avgGap 4016395.15 # Average gap between requests system.physmem.pageHitRate 90.07 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 6047580 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 3202980 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 58533720 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 58540860 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 210821520.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 136590810 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 8775360 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 736795110 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 212078880 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 14428861800 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 15801707760 # Total energy per rank (pJ) -system.physmem_0.averagePower 252.612326 # Core power per rank (mW) -system.physmem_0.totalIdleTime 62230723750 # Total Idle time Per DRAM Rank +system.physmem_0.actBackEnergy 136590240 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 8764320 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 737385060 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 211641120 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 14429375100 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 15802368780 # Total energy per rank (pJ) +system.physmem_0.averagePower 252.613756 # Core power per rank (mW) +system.physmem_0.totalIdleTime 62232966250 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 9906000 # Time in different power states system.physmem_0.memoryStateTime::REF 89372000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 60062733500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 552254250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 223131000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 1615796750 # Time in different power states +system.physmem_0.memoryStateTime::SREF 60064867500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 551102250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 223150500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 1617057250 # Time in different power states system.physmem_1.actEnergy 4998000 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 2641320 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 52664640 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 256919520.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 136418100 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 13273920 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 827375520 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 248165280 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 14377479765 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 15920005755 # Total energy per rank (pJ) -system.physmem_1.averagePower 254.503484 # Core power per rank (mW) -system.physmem_1.totalIdleTime 62218080000 # Total Idle time Per DRAM Rank +system.physmem_1.actBackEnergy 136410120 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 13262400 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 827323080 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 248273280 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 14377994265 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 15920556885 # Total energy per rank (pJ) +system.physmem_1.averagePower 254.503090 # Core power per rank (mW) +system.physmem_1.totalIdleTime 62220218000 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 20713000 # Time in different power states system.physmem_1.memoryStateTime::REF 109118000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 59758619500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 646225750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 203975250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1814542000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 20808248 # Number of BP lookups -system.cpu.branchPred.condPredicted 17115636 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8965663 # Number of BTB lookups -system.cpu.branchPred.BTBHits 8840828 # Number of BTB hits +system.physmem_1.memoryStateTime::SREF 59760759500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 646525750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 203991750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1814347500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 20806620 # Number of BP lookups +system.cpu.branchPred.condPredicted 17114048 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 756880 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8968258 # Number of BTB lookups +system.cpu.branchPred.BTBHits 8843232 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.607632 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 61995 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 98.605905 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 61975 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 26211 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 24795 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1416 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectHits 24793 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1418 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 666 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -306,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -336,7 +336,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -366,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -397,16 +397,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 62553193500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 125106387 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 62555455500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 125110911 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602850 # Number of instructions committed system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2182224 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2181045 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.380822 # CPI: cycles per instruction -system.cpu.ipc 0.724206 # IPC: instructions per cycle +system.cpu.cpi 1.380872 # CPI: cycles per instruction +system.cpu.ipc 0.724180 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction @@ -446,60 +446,60 @@ system.cpu.op_class_0::FloatMemWrite 22 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 91054081 # Class of committed instruction -system.cpu.tickCycles 110521789 # Number of cycles that the object actually ticked -system.cpu.idleCycles 14584598 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 946101 # number of replacements -system.cpu.dcache.tags.tagsinuse 3621.109986 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26274729 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 950197 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.651875 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20754063500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3621.109986 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.884060 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.884060 # Average percentage of cache occupancy +system.cpu.tickCycles 110528679 # Number of cycles that the object actually ticked +system.cpu.idleCycles 14582232 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 946104 # number of replacements +system.cpu.dcache.tags.tagsinuse 3621.120784 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26274613 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 950200 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.651666 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20754332500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3621.120784 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.884063 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.884063 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2202 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1662 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2198 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1666 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55461283 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55461283 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 21605780 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21605780 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4660667 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4660667 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 55461064 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55461064 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 21605665 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21605665 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4660666 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4660666 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26266447 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26266447 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26266955 # number of overall hits -system.cpu.dcache.overall_hits::total 26266955 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 906496 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 906496 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 74314 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 74314 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 26266331 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26266331 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26266839 # number of overall hits +system.cpu.dcache.overall_hits::total 26266839 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 906500 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 906500 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 74315 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 74315 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 980810 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 980810 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 980814 # number of overall misses -system.cpu.dcache.overall_misses::total 980814 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11832179000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11832179000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2760205500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2760205500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14592384500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14592384500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14592384500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14592384500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22512276 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22512276 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 980815 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 980815 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 980819 # number of overall misses +system.cpu.dcache.overall_misses::total 980819 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11832236000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11832236000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2760278000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2760278000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14592514000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14592514000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14592514000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14592514000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22512165 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22512165 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) @@ -508,10 +508,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27247257 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27247257 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27247769 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27247769 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 27247146 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27247146 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27247658 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27247658 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040267 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.040267 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015695 # miss rate for WriteReq accesses @@ -522,50 +522,50 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.035997 system.cpu.dcache.demand_miss_rate::total 0.035997 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.035996 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.035996 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13052.654397 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13052.654397 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.469790 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.469790 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14877.891233 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14877.891233 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14877.830557 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14877.830557 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13052.659680 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13052.659680 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.945570 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.945570 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14877.947421 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14877.947421 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14877.886746 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14877.886746 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 943282 # number of writebacks -system.cpu.dcache.writebacks::total 943282 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3066 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3066 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27550 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 27550 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 30616 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 30616 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 30616 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 30616 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903430 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903430 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 943285 # number of writebacks +system.cpu.dcache.writebacks::total 943285 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3067 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3067 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27551 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27551 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 30618 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 30618 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 30618 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 30618 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903433 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903433 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 950194 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 950194 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 950197 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 950197 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10889871500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10889871500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1596189500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1596189500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 950197 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 950197 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 950200 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 950200 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10889912000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10889912000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1596274500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1596274500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 170000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 170000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12486061000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12486061000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12486231000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12486231000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12486186500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12486186500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12486356500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12486356500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040131 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040131 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses @@ -574,73 +574,73 @@ system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034873 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.034873 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12053.918400 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12053.918400 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34132.869301 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34132.869301 # average WriteReq mshr miss latency +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034873 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034873 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12053.923202 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12053.923202 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34134.686939 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34134.686939 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 56666.666667 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 56666.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.538669 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.538669 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.676091 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.676091 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.629259 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.629259 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.766681 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.766681 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.tagsinuse 689.568187 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27835083 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34750.415730 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 689.583421 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27839479 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 34712.567332 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 689.568187 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.336703 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.336703 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 689.583421 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.336711 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.336711 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 797 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55672569 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55672569 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 27835083 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27835083 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27835083 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27835083 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27835083 # number of overall hits -system.cpu.icache.overall_hits::total 27835083 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 801 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 801 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 801 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 801 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 801 # number of overall misses -system.cpu.icache.overall_misses::total 801 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 71410500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 71410500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 71410500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 71410500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 71410500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 71410500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27835884 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27835884 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27835884 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27835884 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27835884 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27835884 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_task_id_percent::1024 0.389160 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 55681364 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55681364 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 27839479 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27839479 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27839479 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27839479 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27839479 # number of overall hits +system.cpu.icache.overall_hits::total 27839479 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses +system.cpu.icache.overall_misses::total 802 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 71421000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 71421000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 71421000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 71421000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 71421000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 71421000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27840281 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27840281 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27840281 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27840281 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27840281 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27840281 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 89151.685393 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 89151.685393 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 89151.685393 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 89151.685393 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 89151.685393 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 89151.685393 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 89053.615960 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 89053.615960 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 89053.615960 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 89053.615960 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 89053.615960 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 89053.615960 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,132 +649,132 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 5 # number of writebacks system.cpu.icache.writebacks::total 5 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 801 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70609500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 70609500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70609500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 70609500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 70609500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 70609500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70619000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 70619000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70619000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 70619000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 70619000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 70619000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 88151.685393 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 88151.685393 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 88151.685393 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 88151.685393 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 88151.685393 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 88151.685393 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 88053.615960 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 88053.615960 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 88053.615960 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 88053.615960 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 88053.615960 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 88053.615960 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 11307.993669 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1881373 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15574 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 120.802170 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 11308.105127 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1881379 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15575 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 120.794799 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.573080 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 10633.420588 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020586 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.324506 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.345093 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15574 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.588306 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10633.516821 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020587 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.324509 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.345096 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15575 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15454 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475281 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15191206 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15191206 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 943282 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 943282 # number of WritebackDirty hits +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475311 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 15191263 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15191263 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 943285 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 943285 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 4 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 32220 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 32220 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 27 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 27 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 903170 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 903170 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 903173 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 903173 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 935390 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 935417 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 935393 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 935420 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 935390 # number of overall hits -system.cpu.l2cache.overall_hits::total 935417 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 935393 # number of overall hits +system.cpu.l2cache.overall_hits::total 935420 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 774 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 774 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 775 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 775 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 263 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 263 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 774 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 775 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 14807 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15581 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 774 # number of overall misses +system.cpu.l2cache.demand_misses::total 15582 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 775 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14807 # number of overall misses -system.cpu.l2cache.overall_misses::total 15581 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1182247000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1182247000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 69101000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 69101000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49237000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 49237000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 69101000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1231484000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1300585000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 69101000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1231484000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1300585000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 943282 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 943282 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 15582 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1182333500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1182333500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 69109000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 69109000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49239000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 49239000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 69109000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1231572500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1300681500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 69109000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1231572500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1300681500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 943285 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 943285 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 4 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 46764 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 46764 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 801 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 801 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 903433 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 903433 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 801 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 950197 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 950998 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 801 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 950197 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 950998 # number of overall (read+write) accesses +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 802 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 802 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 903436 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 903436 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 950200 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 951002 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 950200 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 951002 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311008 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.311008 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.966292 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.966292 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.966334 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.966334 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000291 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000291 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.966292 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.966334 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.015583 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016384 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966292 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.016385 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966334 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015583 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016384 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81287.610011 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81287.610011 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89277.777778 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89277.777778 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 187212.927757 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 187212.927757 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89277.777778 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83169.041669 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83472.498556 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89277.777778 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83169.041669 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83472.498556 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.016385 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81293.557481 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81293.557481 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89172.903226 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89172.903226 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 187220.532319 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 187220.532319 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89172.903226 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83175.018572 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83473.334617 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89172.903226 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83175.018572 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83473.334617 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -793,122 +793,122 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 6 system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14544 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 773 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 773 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 774 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 774 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 257 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 257 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 773 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 774 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 14801 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15574 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15575 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14801 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1036807000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1036807000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 61297500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 61297500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 46234000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 46234000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61297500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1083041000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1144338500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61297500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1083041000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1144338500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1036893500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1036893500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 61295500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 61295500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 46236000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 46236000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61295500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1083129500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1144425000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61295500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1083129500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1144425000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965044 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965087 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000284 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000284 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71287.610011 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71287.610011 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79298.188875 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79298.188875 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 179898.832685 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 179898.832685 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79298.188875 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73173.501790 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73477.494542 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79298.188875 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73173.501790 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73477.494542 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1897104 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 946122 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71293.557481 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71293.557481 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79193.152455 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79193.152455 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 179906.614786 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 179906.614786 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79193.152455 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73179.481116 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73478.330658 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79193.152455 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73179.481116 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73478.330658 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1897111 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 946125 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 904234 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 943282 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 943285 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 801 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 903433 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1607 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846495 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2848102 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 121234240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 903436 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1609 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846504 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2848113 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 121234688 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 950998 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 951002 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000175 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.013211 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 950832 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 950836 99.98% 99.98% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 166 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 950998 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1891839000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 951002 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1891845500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1201999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1203499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1425298494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1425302994 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 15574 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 15575 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1030 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1031 # Transaction distribution system.membus.trans_dist::ReadExReq 14544 # Transaction distribution system.membus.trans_dist::ReadExResp 14544 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1030 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 1031 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31150 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31150 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 996800 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 15574 # Request fanout histogram +system.membus.snoop_fanout::samples 15575 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 15575 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 15574 # Request fanout histogram -system.membus.reqLayer0.occupancy 21778500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 15575 # Request fanout histogram +system.membus.reqLayer0.occupancy 21782500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 82137500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 82144500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 2da35dc4f..e99ff0d50 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,117 +1,117 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058681 # Number of seconds simulated -sim_ticks 58681066500 # Number of ticks simulated -final_tick 58681066500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058521 # Number of seconds simulated +sim_ticks 58521086000 # Number of ticks simulated +final_tick 58521086000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 243006 # Simulator instruction rate (inst/s) -host_op_rate 244216 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 157411271 # Simulator tick rate (ticks/s) -host_mem_usage 492224 # Number of bytes of host memory used -host_seconds 372.79 # Real time elapsed on the host +host_inst_rate 243648 # Simulator instruction rate (inst/s) +host_op_rate 244862 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 157397000 # Simulator tick rate (ticks/s) +host_mem_usage 492140 # Number of bytes of host memory used +host_seconds 371.81 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 44800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 219520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 922368 # Number of bytes read from this memory -system.physmem.bytes_read::total 1186688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44800 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6784 # Number of bytes written to this memory -system.physmem.bytes_written::total 6784 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 700 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3430 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14412 # Number of read requests responded to by this memory -system.physmem.num_reads::total 18542 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 106 # Number of write requests responded to by this memory -system.physmem.num_writes::total 106 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 763449 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3740900 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 15718324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 20222673 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 763449 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 763449 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 115608 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 115608 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 115608 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 763449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3740900 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 15718324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 20338281 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 18543 # Number of read requests accepted -system.physmem.writeReqs 106 # Number of write requests accepted -system.physmem.readBursts 18543 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 106 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1180544 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue -system.physmem.bytesWritten 4608 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1186752 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6784 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 220224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 921920 # Number of bytes read from this memory +system.physmem.bytes_read::total 1186880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4736 # Number of bytes written to this memory +system.physmem.bytes_written::total 4736 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3441 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14405 # Number of read requests responded to by this memory +system.physmem.num_reads::total 18545 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 74 # Number of write requests responded to by this memory +system.physmem.num_writes::total 74 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 764442 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3763156 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 15753638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 20281237 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 764442 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 764442 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 80928 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 80928 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 80928 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 764442 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3763156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 15753638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 20362165 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 18546 # Number of read requests accepted +system.physmem.writeReqs 74 # Number of write requests accepted +system.physmem.readBursts 18546 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 74 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1183360 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3584 # Total number of bytes read from write queue +system.physmem.bytesWritten 3328 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1186944 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4736 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 56 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 3245 # Per bank write bursts -system.physmem.perBankRdBursts::1 921 # Per bank write bursts -system.physmem.perBankRdBursts::2 954 # Per bank write bursts +system.physmem.perBankRdBursts::0 3297 # Per bank write bursts +system.physmem.perBankRdBursts::1 920 # Per bank write bursts +system.physmem.perBankRdBursts::2 949 # Per bank write bursts system.physmem.perBankRdBursts::3 1031 # Per bank write bursts -system.physmem.perBankRdBursts::4 1065 # Per bank write bursts -system.physmem.perBankRdBursts::5 1115 # Per bank write bursts +system.physmem.perBankRdBursts::4 1067 # Per bank write bursts +system.physmem.perBankRdBursts::5 1119 # Per bank write bursts system.physmem.perBankRdBursts::6 1093 # Per bank write bursts -system.physmem.perBankRdBursts::7 1100 # Per bank write bursts +system.physmem.perBankRdBursts::7 1097 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts -system.physmem.perBankRdBursts::9 962 # Per bank write bursts -system.physmem.perBankRdBursts::10 933 # Per bank write bursts +system.physmem.perBankRdBursts::9 961 # Per bank write bursts +system.physmem.perBankRdBursts::10 934 # Per bank write bursts system.physmem.perBankRdBursts::11 899 # Per bank write bursts -system.physmem.perBankRdBursts::12 904 # Per bank write bursts +system.physmem.perBankRdBursts::12 902 # Per bank write bursts system.physmem.perBankRdBursts::13 895 # Per bank write bursts -system.physmem.perBankRdBursts::14 1401 # Per bank write bursts -system.physmem.perBankRdBursts::15 904 # Per bank write bursts -system.physmem.perBankWrBursts::0 2 # Per bank write bursts +system.physmem.perBankRdBursts::14 1399 # Per bank write bursts +system.physmem.perBankRdBursts::15 903 # Per bank write bursts +system.physmem.perBankWrBursts::0 1 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 2 # Per bank write bursts system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 12 # Per bank write bursts -system.physmem.perBankWrBursts::5 8 # Per bank write bursts -system.physmem.perBankWrBursts::6 10 # Per bank write bursts -system.physmem.perBankWrBursts::7 7 # Per bank write bursts +system.physmem.perBankWrBursts::4 1 # Per bank write bursts +system.physmem.perBankWrBursts::5 14 # Per bank write bursts +system.physmem.perBankWrBursts::6 9 # Per bank write bursts +system.physmem.perBankWrBursts::7 3 # Per bank write bursts system.physmem.perBankWrBursts::8 1 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 1 # Per bank write bursts +system.physmem.perBankWrBursts::10 2 # Per bank write bursts system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 5 # Per bank write bursts +system.physmem.perBankWrBursts::12 1 # Per bank write bursts system.physmem.perBankWrBursts::13 12 # Per bank write bursts -system.physmem.perBankWrBursts::14 8 # Per bank write bursts -system.physmem.perBankWrBursts::15 6 # Per bank write bursts +system.physmem.perBankWrBursts::14 5 # Per bank write bursts +system.physmem.perBankWrBursts::15 1 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58681058000 # Total gap between requests +system.physmem.totGap 58521077500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 18543 # Read request sizes (log2) +system.physmem.readPktSize::6 18546 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 106 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 12536 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 3413 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 499 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 316 # What read queue length does an incoming req see +system.physmem.writePktSize::6 74 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 12593 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 3390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 500 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 409 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 319 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 299 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 299 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 103 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -149,24 +149,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -198,109 +198,111 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2972 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 398.104980 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 217.970166 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 405.874685 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 839 28.23% 28.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 987 33.21% 61.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 89 2.99% 64.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 64 2.15% 66.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 64 2.15% 68.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 65 2.19% 70.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 54 1.82% 72.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 55 1.85% 74.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 755 25.40% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2972 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 4544.500000 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 1447.547305 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 7502.381200 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 2 50.00% 50.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 1 25.00% 75.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-15871 1 25.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 4 100.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4 # Writes before turning the bus around for reads -system.physmem.totQLat 829373528 # Total ticks spent queuing -system.physmem.totMemAccLat 1175236028 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 92230000 # Total ticks spent in databus transfers -system.physmem.avgQLat 44962.24 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 3004 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 394.652463 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 214.589229 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 405.543781 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 893 29.73% 29.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 965 32.12% 61.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 89 2.96% 64.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 63 2.10% 66.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 67 2.23% 69.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 66 2.20% 71.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 53 1.76% 73.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 47 1.56% 74.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 761 25.33% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 3004 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 6161.333333 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 2123.401593 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 8586.829993 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 1 33.33% 33.33% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 1 33.33% 66.67% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15872-16383 1 33.33% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.333333 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.306995 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.154701 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 1 33.33% 33.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 2 66.67% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3 # Writes before turning the bus around for reads +system.physmem.totQLat 837911216 # Total ticks spent queuing +system.physmem.totMemAccLat 1184598716 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 92450000 # Total ticks spent in databus transfers +system.physmem.avgQLat 45316.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 63712.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 20.12 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.08 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 20.22 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.12 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 64066.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 20.22 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.06 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 20.28 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.08 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.16 # Data bus utilization in percentage system.physmem.busUtilRead 0.16 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.34 # Average write queue length when enqueuing -system.physmem.readRowHits 15527 # Number of row buffer hits during reads -system.physmem.writeRowHits 11 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.18 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 11.00 # Row buffer hit rate for writes -system.physmem.avgGap 3146606.15 # Average gap between requests -system.physmem.pageHitRate 83.78 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 15943620 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8459055 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 75134220 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 203580 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1849451760.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 458311920 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 99516480 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 3997068570 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 3182851200 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 10077393330 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 19767987555 # Total energy per rank (pJ) -system.physmem_0.averagePower 336.871642 # Core power per rank (mW) -system.physmem_0.totalIdleTime 57408712347 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 196273000 # Time in different power states -system.physmem_0.memoryStateTime::REF 786774000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 40354533250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 8288648060 # Time in different power states -system.physmem_0.memoryStateTime::ACT 289307153 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 8765531037 # Time in different power states -system.physmem_1.actEnergy 5333580 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2819685 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 56563080 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 172260 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 259378080.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 131548590 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 14205120 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 785395590 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 262919520 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 13470232590 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 14988765045 # Total energy per rank (pJ) -system.physmem_1.averagePower 255.427603 # Core power per rank (mW) -system.physmem_1.totalIdleTime 58353780091 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 23548250 # Time in different power states -system.physmem_1.memoryStateTime::REF 110212000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 55948105250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 684663397 # Time in different power states -system.physmem_1.memoryStateTime::ACT 192205159 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1722332444 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 28234239 # Number of BP lookups -system.cpu.branchPred.condPredicted 23266690 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 835421 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11829840 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11748052 # Number of BTB hits +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 13.38 # Average write queue length when enqueuing +system.physmem.readRowHits 15512 # Number of row buffer hits during reads +system.physmem.writeRowHits 18 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.89 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 25.71 # Row buffer hit rate for writes +system.physmem.avgGap 3142915.01 # Average gap between requests +system.physmem.pageHitRate 83.67 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 16243500 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8614650 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 75484080 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 156600 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1895549760.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 464945010 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 99199680 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 4173482430 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 3272736480 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 9883191315 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 19894073865 # Total energy per rank (pJ) +system.physmem_0.averagePower 339.947098 # Core power per rank (mW) +system.physmem_0.totalIdleTime 57233116090 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 194944250 # Time in different power states +system.physmem_0.memoryStateTime::REF 806364000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 39558059500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 8522710566 # Time in different power states +system.physmem_0.memoryStateTime::ACT 286661660 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 9152346024 # Time in different power states +system.physmem_1.actEnergy 5255040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2785530 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 56527380 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 114840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 247699920.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 125328180 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 13397280 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 772336890 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 242624160 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 13451278005 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 14917407225 # Total energy per rank (pJ) +system.physmem_1.averagePower 254.906533 # Core power per rank (mW) +system.physmem_1.totalIdleTime 58211272096 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 21634250 # Time in different power states +system.physmem_1.memoryStateTime::REF 105218000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 55885668250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 631842954 # Time in different power states +system.physmem_1.memoryStateTime::ACT 182961654 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1693760892 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 28121660 # Number of BP lookups +system.cpu.branchPred.condPredicted 23134709 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 844714 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11731332 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11630363 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.308630 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 74543 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 96 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 27224 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 25476 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1748 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 99.139322 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 80725 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 95 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 28301 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 25845 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2456 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 243 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +332,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +362,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -390,7 +392,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -421,240 +423,240 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 58681066500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 117362134 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 58521086000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 117042173 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 746504 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 134908625 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28234239 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11848071 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 115710996 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1674249 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 874 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 948 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32275841 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 569 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 117296446 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.155292 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.317650 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 755365 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134380549 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28121660 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11736933 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 115370240 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1692793 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 848 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 1033 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32086744 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 572 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 116973882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.154260 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.318237 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 59759710 50.95% 50.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13934020 11.88% 62.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9230571 7.87% 70.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34372145 29.30% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 59688776 51.03% 51.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13868271 11.86% 62.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9100495 7.78% 70.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34316340 29.34% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 117296446 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.240574 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.149507 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8834504 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 65062525 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33013030 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9560979 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 825408 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4097904 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11817 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114396314 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1984657 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 825408 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15270391 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50319403 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 113009 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35408802 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15359433 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110873352 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1412133 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11133960 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1550028 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2088318 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 507009 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129946854 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483157007 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119448195 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 430 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 116973882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.240269 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.148138 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8865418 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 65026599 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 32710680 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9589004 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 782181 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9831266 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 64876 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 113761457 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2108425 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 782181 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15316274 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50229704 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 114341 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35119945 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15411437 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110456918 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1289549 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11149602 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1576334 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2138216 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 510190 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129202611 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 481340709 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 118978784 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 633 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22633935 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4409 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4401 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21513701 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26805540 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5347415 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 519015 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 253842 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109668195 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8283 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101366364 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1074602 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18635448 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41675725 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 65 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 117296446 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.864190 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.988217 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 21889692 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4408 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4400 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 21529051 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26813393 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5308956 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 540635 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 272789 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109383305 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8282 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 101253910 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 993650 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18350557 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 40868291 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 64 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 116973882 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.865611 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.989909 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55661536 47.45% 47.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 31364227 26.74% 74.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22008293 18.76% 92.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7064324 6.02% 98.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1197751 1.02% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 315 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55502940 47.45% 47.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31207963 26.68% 74.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 21948493 18.76% 92.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7109305 6.08% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1204859 1.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 322 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 117296446 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116973882 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9780929 48.66% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 50 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9614642 47.84% 96.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 702971 3.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9836731 48.84% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 51 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 19 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9605308 47.69% 96.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 697155 3.46% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 3 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 24 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71970702 71.00% 71.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10697 0.01% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 57 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24337480 24.01% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5047270 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71822499 70.93% 70.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10678 0.01% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 184 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24343876 24.04% 94.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5076562 5.01% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 8 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 22 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101366364 # Type of FU issued -system.cpu.iq.rate 0.863706 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20098632 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.198277 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 341201935 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128312613 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99607782 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 473 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 622 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121464746 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 250 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 288157 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 101253910 # Type of FU issued +system.cpu.iq.rate 0.865106 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20139291 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.198899 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 340613998 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 127742533 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99568159 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 645 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 896 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 147 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121392865 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 336 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 289487 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4329629 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1502 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1344 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 602571 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4337482 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2085 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1323 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 564112 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7583 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130792 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7586 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 131115 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 825408 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8297291 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 773487 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109689301 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 782181 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8303656 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 706645 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109404410 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26805540 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5347415 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4395 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 182523 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 427569 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1344 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 435014 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412394 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 847408 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100110032 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23803163 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1256332 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26813393 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5308956 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4394 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 183005 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 362995 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1323 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 354101 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 451870 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 805971 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100068536 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23799476 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1185374 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 12823 # number of nop insts executed -system.cpu.iew.exec_refs 28718949 # number of memory reference insts executed -system.cpu.iew.exec_branches 20621210 # Number of branches executed -system.cpu.iew.exec_stores 4915786 # Number of stores executed -system.cpu.iew.exec_rate 0.853001 # Inst execution rate -system.cpu.iew.wb_sent 99693474 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99607900 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59692176 # num instructions producing a value -system.cpu.iew.wb_consumers 95528763 # num instructions consuming a value -system.cpu.iew.wb_rate 0.848723 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.624861 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 17363908 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 28747002 # number of memory reference insts executed +system.cpu.iew.exec_branches 20644390 # Number of branches executed +system.cpu.iew.exec_stores 4947526 # Number of stores executed +system.cpu.iew.exec_rate 0.854978 # Inst execution rate +system.cpu.iew.wb_sent 99653444 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99568306 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59603520 # num instructions producing a value +system.cpu.iew.wb_consumers 95472454 # num instructions consuming a value +system.cpu.iew.wb_rate 0.850705 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624301 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 17204380 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 823705 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 114608461 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.794476 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.731976 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 780499 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 114317449 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.796498 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.736161 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 78183874 68.22% 68.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18612814 16.24% 84.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7153278 6.24% 90.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3469165 3.03% 93.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1644308 1.43% 95.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 541542 0.47% 95.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 703493 0.61% 96.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 179022 0.16% 96.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4120965 3.60% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 77973404 68.21% 68.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18552037 16.23% 84.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7135846 6.24% 90.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3439776 3.01% 93.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1654311 1.45% 95.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 545783 0.48% 95.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 692568 0.61% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 180777 0.16% 96.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4142947 3.62% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 114608461 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 114317449 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602408 # Number of instructions committed system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -704,80 +706,80 @@ system.cpu.commit.op_class_0::FloatMemWrite 22 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction -system.cpu.commit.bw_lim_events 4120965 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 218899309 # The number of ROB reads -system.cpu.rob.rob_writes 219523661 # The number of ROB writes -system.cpu.timesIdled 582 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 65688 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 4142947 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 218426787 # The number of ROB reads +system.cpu.rob.rob_writes 219173124 # The number of ROB writes +system.cpu.timesIdled 593 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 68291 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589799 # Number of Instructions Simulated system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.295534 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.295534 # CPI: Total CPI of All Threads -system.cpu.ipc 0.771883 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.771883 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108098001 # number of integer regfile reads -system.cpu.int_regfile_writes 58691976 # number of integer regfile writes +system.cpu.cpi 1.292002 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.292002 # CPI: Total CPI of All Threads +system.cpu.ipc 0.773993 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.773993 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108095256 # number of integer regfile reads +system.cpu.int_regfile_writes 58597145 # number of integer regfile writes system.cpu.fp_regfile_reads 58 # number of floating regfile reads -system.cpu.fp_regfile_writes 98 # number of floating regfile writes -system.cpu.cc_regfile_reads 369004563 # number of cc regfile reads -system.cpu.cc_regfile_writes 58686890 # number of cc regfile writes -system.cpu.misc_regfile_reads 28409682 # number of misc regfile reads +system.cpu.fp_regfile_writes 127 # number of floating regfile writes +system.cpu.cc_regfile_reads 368871207 # number of cc regfile reads +system.cpu.cc_regfile_writes 58517884 # number of cc regfile writes +system.cpu.misc_regfile_reads 28439348 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 5470632 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.769242 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18249828 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 511.768178 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18243100 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 5471144 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.335651 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 38122500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.769242 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999549 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999549 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 3.334421 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 38187500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.768178 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999547 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999547 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 334 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 327 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61906996 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61906996 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 13887361 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13887361 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4354163 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4354163 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61896540 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61896540 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 13880582 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13880582 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4354214 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4354214 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18241524 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18241524 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18242046 # number of overall hits -system.cpu.dcache.overall_hits::total 18242046 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9587281 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9587281 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 380818 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 380818 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 18234796 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18234796 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18235318 # number of overall hits +system.cpu.dcache.overall_hits::total 18235318 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9588832 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9588832 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 380767 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 380767 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9968099 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9968099 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9968106 # number of overall misses -system.cpu.dcache.overall_misses::total 9968106 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 89375617500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 89375617500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4089956224 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4089956224 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9969599 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9969599 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9969606 # number of overall misses +system.cpu.dcache.overall_misses::total 9969606 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 89393317500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 89393317500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4103772083 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4103772083 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 302000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 302000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 93465573724 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 93465573724 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 93465573724 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 93465573724 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23474642 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23474642 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 93497089583 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 93497089583 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 93497089583 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 93497089583 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23469414 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23469414 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) @@ -786,475 +788,475 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28209623 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28209623 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28210152 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28210152 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408410 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408410 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080427 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080427 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28204395 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28204395 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28204924 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28204924 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408567 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408567 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080416 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080416 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353358 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353358 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353352 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353352 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9322.311248 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9322.311248 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10739.923596 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10739.923596 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.353477 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353477 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353470 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353470 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9322.649255 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9322.649255 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10777.646390 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10777.646390 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21571.428571 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21571.428571 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9376.469247 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9376.469247 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9376.462662 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9376.462662 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 331655 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 128757 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 121530 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12840 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.728997 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10.027804 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9378.219684 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9378.219684 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9378.213099 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9378.213099 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 331670 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 131340 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 121646 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.726518 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 10.230566 # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 5470632 # number of writebacks system.cpu.dcache.writebacks::total 5470632 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338725 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4338725 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158229 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158229 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4340269 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4340269 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158185 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158185 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4496954 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4496954 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4496954 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4496954 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248556 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5248556 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222589 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222589 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4498454 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4498454 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4498454 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4498454 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248563 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5248563 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222582 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 222582 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 5471145 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 5471145 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 5471149 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 5471149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43819499500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43819499500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2297613115 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2297613115 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43818706500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43818706500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2301862483 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2301862483 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 235500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 235500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46117112615 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 46117112615 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46117348115 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 46117348115 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223584 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223584 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047009 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047009 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46120568983 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 46120568983 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46120804483 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 46120804483 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223634 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223634 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047008 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047008 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193946 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.193946 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193943 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.193943 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.867670 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.867670 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10322.222190 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10322.222190 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193982 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.193982 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193979 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.193979 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.705446 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.705446 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10341.638061 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10341.638061 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58875 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58875 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8429.151963 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8429.151963 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8429.188844 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8429.188844 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 448 # number of replacements -system.cpu.icache.tags.tagsinuse 427.601453 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32274679 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 906 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35623.266004 # Average number of references to valid blocks. +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8429.783708 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8429.783708 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8429.820589 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8429.820589 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 449 # number of replacements +system.cpu.icache.tags.tagsinuse 426.857560 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32085580 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 907 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 35375.501654 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 427.601453 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.835159 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.835159 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 426.857560 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.833706 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.833706 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 458 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.894531 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64552564 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64552564 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 32274679 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32274679 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32274679 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32274679 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32274679 # number of overall hits -system.cpu.icache.overall_hits::total 32274679 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1150 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1150 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1150 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1150 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1150 # number of overall misses -system.cpu.icache.overall_misses::total 1150 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 79102980 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 79102980 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 79102980 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 79102980 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 79102980 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 79102980 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 32275829 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 32275829 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 32275829 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 32275829 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 32275829 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 32275829 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 64174375 # Number of tag accesses +system.cpu.icache.tags.data_accesses 64174375 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 32085580 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 32085580 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 32085580 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 32085580 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 32085580 # number of overall hits +system.cpu.icache.overall_hits::total 32085580 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses +system.cpu.icache.overall_misses::total 1154 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 81624480 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 81624480 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 81624480 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 81624480 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 81624480 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 81624480 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 32086734 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 32086734 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 32086734 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 32086734 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 32086734 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 32086734 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68785.200000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68785.200000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68785.200000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68785.200000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68785.200000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68785.200000 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 21255 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 760 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 230 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 92.413043 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 126.666667 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 448 # number of writebacks -system.cpu.icache.writebacks::total 448 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 243 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 243 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 243 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 243 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 243 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 243 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 907 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 907 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 907 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 907 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 907 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 60408984 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 60408984 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 60408984 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 60408984 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 60408984 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 60408984 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70731.785095 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70731.785095 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70731.785095 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70731.785095 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70731.785095 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70731.785095 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 21770 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 1853 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 229 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 95.065502 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 264.714286 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 449 # number of writebacks +system.cpu.icache.writebacks::total 449 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 246 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 246 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 246 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 246 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 246 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 246 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 908 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 908 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 908 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 908 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 908 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 908 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61609984 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 61609984 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61609984 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 61609984 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61609984 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 61609984 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66603.069460 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66603.069460 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66603.069460 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66603.069460 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66603.069460 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66603.069460 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 4986166 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 5293297 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 266998 # number of redundant prefetches already in prefetch queue +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67852.405286 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67852.405286 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67852.405286 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67852.405286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67852.405286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67852.405286 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 4987667 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 5295978 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 268023 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 14074663 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 148 # number of replacements -system.cpu.l2cache.tags.tagsinuse 11219.998633 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5292017 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 14707 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 359.829809 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 14076270 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 99 # number of replacements +system.cpu.l2cache.tags.tagsinuse 11218.637670 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5292117 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 14656 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 361.088769 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 11153.900503 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 66.098130 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.680780 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004034 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.684814 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 64 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 14495 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 55 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 466 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3398 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9680 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 119 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 832 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.003906 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884705 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 180526200 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 180526200 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 5457195 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 5457195 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 11011 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 11011 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 225669 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 225669 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 205 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 205 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5241856 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 5241856 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 205 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 5467525 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 5467730 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 205 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 5467525 # number of overall hits -system.cpu.l2cache.overall_hits::total 5467730 # number of overall hits +system.cpu.l2cache.tags.occ_blocks::writebacks 11151.920658 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 66.717012 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.680659 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004072 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.684731 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 67 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 14490 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 56 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 454 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3440 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9642 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 120 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 834 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.004089 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884399 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 180525307 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 180525307 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 5460197 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 5460197 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 7956 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 7956 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 225753 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 225753 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 207 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 207 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5241769 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 5241769 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 207 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 5467522 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 5467729 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 207 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 5467522 # number of overall hits +system.cpu.l2cache.overall_hits::total 5467729 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 501 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 501 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 702 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 702 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 3118 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 3118 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 702 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3619 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 4321 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 702 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3619 # number of overall misses -system.cpu.l2cache.overall_misses::total 4321 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 106500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 106500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 63936500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 63936500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58121500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 58121500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 619277500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 619277500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 58121500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 683214000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 741335500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 58121500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 683214000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 741335500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 5457195 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 5457195 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 11011 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 11011 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 499 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 499 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 701 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 701 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 3123 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 3123 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 701 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3622 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 4323 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 701 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3622 # number of overall misses +system.cpu.l2cache.overall_misses::total 4323 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 105500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 105500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66196000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 66196000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59307500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 59307500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 617300000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 617300000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 59307500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 683496000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 742803500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 59307500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 683496000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 742803500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 5460197 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 5460197 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 7956 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 7956 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 226170 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 226170 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 907 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 907 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244974 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 5244974 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 907 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 226252 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 226252 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 908 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 908 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244892 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 5244892 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 5471144 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 5472051 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 907 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 5472052 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 5471144 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 5472051 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 5472052 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002215 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.002215 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.773980 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.773980 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000594 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000594 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.773980 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.000661 # miss rate for demand accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002206 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.002206 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.772026 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.772026 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000595 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000595 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.772026 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.000662 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.000790 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.773980 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.000661 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.772026 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.000662 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.000790 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21300 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21300 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127617.764471 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127617.764471 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82794.159544 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82794.159544 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 198613.694676 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 198613.694676 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82794.159544 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 188785.299807 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 171565.725526 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82794.159544 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 188785.299807 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 171565.725526 # average overall miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21100 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21100 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132657.314629 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132657.314629 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84604.136947 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84604.136947 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 197662.504003 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 197662.504003 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84604.136947 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 188706.791828 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 171825.931066 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84604.136947 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 188706.791828 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 171825.931066 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 3 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 106 # number of writebacks -system.cpu.l2cache.writebacks::total 106 # number of writebacks +system.cpu.l2cache.unused_prefetches 1 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 74 # number of writebacks +system.cpu.l2cache.writebacks::total 74 # number of writebacks system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 30 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 30 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 22 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 22 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 188 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 189 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 180 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 181 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 188 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 189 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316628 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 316628 # number of HardPFReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 180 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 181 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316332 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 316332 # number of HardPFReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 343 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 343 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 701 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 701 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3088 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3088 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 701 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3431 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 4132 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 701 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3431 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316628 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 320760 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1087453464 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1087453464 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 76500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 76500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 45609000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 45609000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 53854500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 53854500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 591148000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 591148000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53854500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 636757000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 690611500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53854500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 636757000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1087453464 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1778064964 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 341 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 700 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 700 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3101 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3101 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 700 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3442 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 4142 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 700 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3442 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316332 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 320474 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1095451507 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1095451507 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 75500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 75500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 46761500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 46761500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 55046500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 55046500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 590692000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 590692000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 55046500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 637453500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 692500000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 55046500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 637453500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1095451507 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1787951507 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001517 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001517 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.772878 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.772878 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000589 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000589 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.772878 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000627 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000755 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.772878 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000627 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001507 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001507 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.770925 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000591 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000591 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000629 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000757 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000629 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.058618 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3434.482939 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3434.482939 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15300 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15300 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 132970.845481 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 132970.845481 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76825.249643 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76825.249643 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 191433.937824 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 191433.937824 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76825.249643 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185589.332556 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167137.342691 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76825.249643 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185589.332556 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3434.482939 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5543.287704 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 10943136 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471098 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2874 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 302216 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302215 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.058566 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3462.980372 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15100 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15100 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 137130.498534 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 137130.498534 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78637.857143 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78637.857143 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 190484.359884 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 190484.359884 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78637.857143 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185198.576409 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167189.763399 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78637.857143 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185198.576409 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5579.084441 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 10943138 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471099 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2928 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 301927 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 301926 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 5245880 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 5457301 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13885 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 42 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 318509 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 5245799 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 5460271 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 10884 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 25 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 318221 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 226170 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 226170 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 907 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244974 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2261 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 226252 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 226252 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 908 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244892 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2264 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16415197 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16415200 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 700360704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 318663 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7168 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 5790713 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.052689 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.223412 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 700360832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 318326 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5120 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 5790377 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.052651 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.223337 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5485610 94.73% 94.73% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 305102 5.27% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5485509 94.73% 94.73% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 304867 5.27% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5790713 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10942648026 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 18.6 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::total 5790377 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10942650026 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 9032 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1361495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1362995 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 8206721993 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 14.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 18697 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 3032 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 18651 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 3037 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 18200 # Transaction distribution -system.membus.trans_dist::WritebackDirty 106 # Transaction distribution -system.membus.trans_dist::CleanEvict 42 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 18205 # Transaction distribution +system.membus.trans_dist::WritebackDirty 74 # Transaction distribution +system.membus.trans_dist::CleanEvict 25 # Transaction distribution system.membus.trans_dist::UpgradeReq 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 342 # Transaction distribution -system.membus.trans_dist::ReadExResp 342 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 18201 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37239 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 37239 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1193472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1193472 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 340 # Transaction distribution +system.membus.trans_dist::ReadExResp 340 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 18206 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37196 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 37196 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1191616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1191616 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 18549 # Request fanout histogram +system.membus.snoop_fanout::samples 18552 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 18549 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 18552 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 18549 # Request fanout histogram -system.membus.reqLayer0.occupancy 29669004 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 18552 # Request fanout histogram +system.membus.reqLayer0.occupancy 29380556 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 97336094 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 97369032 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 716a9adc9..8690264ef 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,77 +1,77 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.065833 # Number of seconds simulated -sim_ticks 65832730500 # Number of ticks simulated -final_tick 65832730500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.065721 # Number of seconds simulated +sim_ticks 65721494500 # Number of ticks simulated +final_tick 65721494500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 190384 # Simulator instruction rate (inst/s) -host_op_rate 335236 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79331786 # Simulator tick rate (ticks/s) -host_mem_usage 416808 # Number of bytes of host memory used -host_seconds 829.84 # Real time elapsed on the host +host_inst_rate 191999 # Simulator instruction rate (inst/s) +host_op_rate 338080 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79869594 # Simulator tick rate (ticks/s) +host_mem_usage 415448 # Number of bytes of host memory used +host_seconds 822.86 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 69952 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 68800 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1892544 # Number of bytes read from this memory -system.physmem.bytes_read::total 1962496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 69952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 69952 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 19776 # Number of bytes written to this memory -system.physmem.bytes_written::total 19776 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1093 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 1961344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 68800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 68800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 19136 # Number of bytes written to this memory +system.physmem.bytes_written::total 19136 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1075 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 29571 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30664 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 309 # Number of write requests responded to by this memory -system.physmem.num_writes::total 309 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1062572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28747767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29810339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1062572 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1062572 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 300398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 300398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 300398 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1062572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28747767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 30110736 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30664 # Number of read requests accepted -system.physmem.writeReqs 309 # Number of write requests accepted -system.physmem.readBursts 30664 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 309 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1954304 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue -system.physmem.bytesWritten 18368 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1962496 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 19776 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 30646 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 299 # Number of write requests responded to by this memory +system.physmem.num_writes::total 299 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1046842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28796424 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29843265 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1046842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1046842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 291168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 291168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 291168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1046842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28796424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 30134433 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30646 # Number of read requests accepted +system.physmem.writeReqs 299 # Number of write requests accepted +system.physmem.readBursts 30646 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 299 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1952832 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8512 # Total number of bytes read from write queue +system.physmem.bytesWritten 17216 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1961344 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 19136 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 133 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1947 # Per bank write bursts -system.physmem.perBankRdBursts::1 2076 # Per bank write bursts -system.physmem.perBankRdBursts::2 2053 # Per bank write bursts -system.physmem.perBankRdBursts::3 1954 # Per bank write bursts -system.physmem.perBankRdBursts::4 2067 # Per bank write bursts +system.physmem.perBankRdBursts::0 1937 # Per bank write bursts +system.physmem.perBankRdBursts::1 2081 # Per bank write bursts +system.physmem.perBankRdBursts::2 2039 # Per bank write bursts +system.physmem.perBankRdBursts::3 1941 # Per bank write bursts +system.physmem.perBankRdBursts::4 2068 # Per bank write bursts system.physmem.perBankRdBursts::5 1911 # Per bank write bursts -system.physmem.perBankRdBursts::6 1975 # Per bank write bursts -system.physmem.perBankRdBursts::7 1868 # Per bank write bursts -system.physmem.perBankRdBursts::8 1952 # Per bank write bursts -system.physmem.perBankRdBursts::9 1938 # Per bank write bursts +system.physmem.perBankRdBursts::6 1977 # Per bank write bursts +system.physmem.perBankRdBursts::7 1878 # Per bank write bursts +system.physmem.perBankRdBursts::8 1945 # Per bank write bursts +system.physmem.perBankRdBursts::9 1939 # Per bank write bursts system.physmem.perBankRdBursts::10 1805 # Per bank write bursts system.physmem.perBankRdBursts::11 1794 # Per bank write bursts system.physmem.perBankRdBursts::12 1792 # Per bank write bursts -system.physmem.perBankRdBursts::13 1799 # Per bank write bursts -system.physmem.perBankRdBursts::14 1826 # Per bank write bursts +system.physmem.perBankRdBursts::13 1800 # Per bank write bursts +system.physmem.perBankRdBursts::14 1827 # Per bank write bursts system.physmem.perBankRdBursts::15 1779 # Per bank write bursts -system.physmem.perBankWrBursts::0 25 # Per bank write bursts -system.physmem.perBankWrBursts::1 120 # Per bank write bursts -system.physmem.perBankWrBursts::2 28 # Per bank write bursts -system.physmem.perBankWrBursts::3 32 # Per bank write bursts +system.physmem.perBankWrBursts::0 8 # Per bank write bursts +system.physmem.perBankWrBursts::1 125 # Per bank write bursts +system.physmem.perBankWrBursts::2 25 # Per bank write bursts +system.physmem.perBankWrBursts::3 26 # Per bank write bursts system.physmem.perBankWrBursts::4 54 # Per bank write bursts -system.physmem.perBankWrBursts::5 2 # Per bank write bursts -system.physmem.perBankWrBursts::6 17 # Per bank write bursts +system.physmem.perBankWrBursts::5 8 # Per bank write bursts +system.physmem.perBankWrBursts::6 14 # Per bank write bursts system.physmem.perBankWrBursts::7 0 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts system.physmem.perBankWrBursts::9 6 # Per bank write bursts @@ -83,28 +83,28 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 65832525500 # Total gap between requests +system.physmem.totGap 65721290500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 30664 # Read request sizes (log2) +system.physmem.readPktSize::6 30646 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 309 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29955 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 437 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 299 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 29942 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 423 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -145,14 +145,14 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see @@ -160,18 +160,18 @@ system.physmem.wrQLenPdf::26 16 # Wh system.physmem.wrQLenPdf::27 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -194,355 +194,353 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2862 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 688.995108 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 484.121076 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 395.829774 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 415 14.50% 14.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 275 9.61% 24.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 149 5.21% 29.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 128 4.47% 33.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 140 4.89% 38.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 122 4.26% 42.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 77 2.69% 45.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 86 3.00% 48.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1470 51.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2862 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 16 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 1905.625000 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 24.516989 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 7552.373489 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 15 93.75% 93.75% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::29696-30719 1 6.25% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 16 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 16 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.937500 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.914548 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.928709 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2 12.50% 12.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 12 75.00% 87.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 6.25% 93.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 6.25% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 16 # Writes before turning the bus around for reads -system.physmem.totQLat 411710000 # Total ticks spent queuing -system.physmem.totMemAccLat 984260000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 152680000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13482.77 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 2852 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 690.064516 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 482.522488 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 397.377699 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 418 14.66% 14.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 289 10.13% 24.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 128 4.49% 29.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 119 4.17% 33.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 133 4.66% 38.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 123 4.31% 42.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 83 2.91% 45.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 90 3.16% 48.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1469 51.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2852 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 15 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2030.466667 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 23.801531 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 7801.447410 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 14 93.33% 93.33% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::29696-30719 1 6.67% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 15 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 15 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.933333 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.931540 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.258199 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1 6.67% 6.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 14 93.33% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 15 # Writes before turning the bus around for reads +system.physmem.totQLat 402617750 # Total ticks spent queuing +system.physmem.totMemAccLat 974736500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 152565000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13194.96 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32232.77 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 29.69 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.28 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 29.81 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.30 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31944.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 29.71 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.26 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 29.84 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.29 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.03 # Average write queue length when enqueuing -system.physmem.readRowHits 27751 # Number of row buffer hits during reads -system.physmem.writeRowHits 206 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.88 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.67 # Row buffer hit rate for writes -system.physmem.avgGap 2125481.08 # Average gap between requests -system.physmem.pageHitRate 90.64 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 11059860 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 5878455 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 113176140 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1451160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 315310320.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 256763340 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 17698560 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 981638610 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 270128640 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 15008515620 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 16981623105 # Total energy per rank (pJ) -system.physmem_0.averagePower 257.950589 # Core power per rank (mW) -system.physmem_0.totalIdleTime 65223686000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 24830750 # Time in different power states -system.physmem_0.memoryStateTime::REF 133713250 # Time in different power states -system.physmem_0.memoryStateTime::SREF 62367507500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 703478750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 450500500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 2152699750 # Time in different power states -system.physmem_1.actEnergy 9403380 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4982835 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 104850900 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 12.51 # Average write queue length when enqueuing +system.physmem.readRowHits 27734 # Number of row buffer hits during reads +system.physmem.writeRowHits 187 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.89 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.54 # Row buffer hit rate for writes +system.physmem.avgGap 2123809.68 # Average gap between requests +system.physmem.pageHitRate 90.62 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 11052720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 5855685 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 113040480 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1357200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 309163920.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 263324610 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 16569120 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 979073610 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 268447200 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 14975920920 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 16943805465 # Total energy per rank (pJ) +system.physmem_0.averagePower 257.812234 # Core power per rank (mW) +system.physmem_0.totalIdleTime 65100637750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 22061500 # Time in different power states +system.physmem_0.memoryStateTime::REF 131194000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 62254705500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 699065250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 467433500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 2147034750 # Time in different power states +system.physmem_1.actEnergy 9374820 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4967655 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 104822340 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 46980 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 389067120.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 256987920 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 20546880 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 1156119600 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 409490400 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 14841811380 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 17194149375 # Total energy per rank (pJ) -system.physmem_1.averagePower 261.179341 # Core power per rank (mW) -system.physmem_1.totalIdleTime 65212352000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 31901000 # Time in different power states -system.physmem_1.memoryStateTime::REF 165222000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 61612056250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1066374000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 421666750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 2535510500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 40426123 # Number of BP lookups -system.cpu.branchPred.condPredicted 40426123 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1402729 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26580139 # Number of BTB lookups +system.physmem_1.refreshEnergy 372471840.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 249536310 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 19488480 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 1119740490 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 403290240 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 14835337125 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 17119488570 # Total energy per rank (pJ) +system.physmem_1.averagePower 260.485370 # Core power per rank (mW) +system.physmem_1.totalIdleTime 65120969250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 28589000 # Time in different power states +system.physmem_1.memoryStateTime::REF 158136000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 61616793750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 1050209250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 412212500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 2455554000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 40406290 # Number of BP lookups +system.cpu.branchPred.condPredicted 40406290 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1431845 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26031629 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6011508 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 87453 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 26580139 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 21161652 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5418487 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 517301 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 6025963 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 91921 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 26031629 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 20992529 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5039100 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 530263 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 65832730500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 131665462 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 65721494500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 131442990 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30553171 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 219967171 # Number of instructions fetch has processed -system.cpu.fetch.Branches 40426123 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 27173160 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 99460538 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2919977 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 306 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 5927 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 105822 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 73 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 157 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 29763575 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 354176 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 15 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 131585982 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.941987 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.406730 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30464048 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 219898668 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40406290 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 27018492 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 99269738 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2979935 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 465 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 7592 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 128961 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 50 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 174 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 29660171 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 359072 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 17 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 131360995 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.946103 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.409063 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 65985920 50.15% 50.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4028379 3.06% 53.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3611314 2.74% 55.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6113229 4.65% 60.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7745533 5.89% 66.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5553246 4.22% 70.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3377028 2.57% 73.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2847646 2.16% 75.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 32323687 24.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 65827184 50.11% 50.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4032527 3.07% 53.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3600376 2.74% 55.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6081929 4.63% 60.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7728911 5.88% 66.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5535416 4.21% 70.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3331669 2.54% 73.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2842658 2.16% 75.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 32380325 24.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 131585982 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.307037 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.670652 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15243618 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64765794 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 40224064 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9892518 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1459988 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 362269877 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1459988 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 20789530 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11237370 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 18362 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 44279240 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53801492 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 352719757 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 16498 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 793095 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 46882908 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5193491 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 355158766 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 934950269 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 575705414 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 24139 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 131360995 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.307405 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.672959 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15255907 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64520496 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 40208811 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9885814 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1489967 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 362265652 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1489967 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 20796133 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11129664 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 23832 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 44255424 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53665975 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 352608748 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 23342 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 777450 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 46732943 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5205031 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 354925639 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 934456502 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 575559102 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 21159 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 75946019 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 487 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 484 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 64820498 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 112428453 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 38501164 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 51645718 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9056873 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 344114716 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4351 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 317908509 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 166833 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 65926603 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 102202913 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3906 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 131585982 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.415976 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.164934 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 75712892 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 482 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 483 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 64647332 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 112313472 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 38475522 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 51426374 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8868395 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343765046 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3883 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 317634440 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 163759 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 65576465 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 101836454 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3438 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 131360995 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.418027 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.167913 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 35686444 27.12% 27.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20105227 15.28% 42.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17162197 13.04% 55.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17623881 13.39% 68.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 15350950 11.67% 80.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12863479 9.78% 90.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6692822 5.09% 95.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4078738 3.10% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2022244 1.54% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 35651981 27.14% 27.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20061286 15.27% 42.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17078933 13.00% 55.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17586289 13.39% 68.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15273572 11.63% 80.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12870930 9.80% 90.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6718617 5.11% 95.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4059315 3.09% 98.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2060072 1.57% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 131585982 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 131360995 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 364988 8.91% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3541451 86.44% 95.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 188937 4.61% 99.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 10 0.00% 99.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 1524 0.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 367555 8.92% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3559749 86.40% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 191317 4.64% 99.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 13 0.00% 99.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 1395 0.03% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 33340 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 181836417 57.20% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11458 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 362 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 334 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101309174 31.87% 89.08% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34711229 10.92% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 553 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 5642 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 33339 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 181647745 57.19% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11501 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 497 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 296 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101245285 31.87% 89.08% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34690277 10.92% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 508 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 4992 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 317908509 # Type of FU issued -system.cpu.iq.rate 2.414517 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4096910 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012887 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 771648435 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 410069961 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 313720076 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 18308 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 36184 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 4316 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 321964016 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8063 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57535034 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 317634440 # Type of FU issued +system.cpu.iq.rate 2.416519 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4120029 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012971 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 770896978 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 409373525 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 313389776 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 16685 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 31480 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3775 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 321713926 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7204 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 57497351 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 21649068 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 67666 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 63141 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7061412 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 21534087 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66072 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 62227 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7035770 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4025 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 141941 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4204 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 141777 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1459988 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8072611 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3068372 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 344119067 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 127232 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 112428453 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 38501164 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1782 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2921 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3074772 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 63141 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 534039 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1041947 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1575986 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 315496434 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100557512 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2412075 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1489967 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8057522 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2987683 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343768929 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 139556 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 112313472 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 38475522 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1604 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2862 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2991864 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 62227 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 520614 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1090823 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1611437 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 315197484 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100490397 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2436956 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 134869578 # number of memory reference insts executed -system.cpu.iew.exec_branches 32108537 # Number of branches executed -system.cpu.iew.exec_stores 34312066 # Number of stores executed -system.cpu.iew.exec_rate 2.396197 # Inst execution rate -system.cpu.iew.wb_sent 314359591 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 313724392 # cumulative count of insts written-back -system.cpu.iew.wb_producers 237724315 # num instructions producing a value -system.cpu.iew.wb_consumers 343443925 # num instructions consuming a value -system.cpu.iew.wb_rate 2.382739 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692178 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 66051294 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 134782236 # number of memory reference insts executed +system.cpu.iew.exec_branches 32089039 # Number of branches executed +system.cpu.iew.exec_stores 34291839 # Number of stores executed +system.cpu.iew.exec_rate 2.397979 # Inst execution rate +system.cpu.iew.wb_sent 314036708 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 313393551 # cumulative count of insts written-back +system.cpu.iew.wb_producers 237399400 # num instructions producing a value +system.cpu.iew.wb_consumers 342887037 # num instructions consuming a value +system.cpu.iew.wb_rate 2.384255 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692355 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 65692241 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1408834 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 122136825 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.277712 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.048100 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1439325 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 121896437 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.282203 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.051706 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57021615 46.69% 46.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16508640 13.52% 60.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11210798 9.18% 69.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8746505 7.16% 76.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2078517 1.70% 78.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1759712 1.44% 79.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 926228 0.76% 80.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 725763 0.59% 81.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23159047 18.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 56939574 46.71% 46.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16454719 13.50% 60.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11025665 9.05% 69.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8756483 7.18% 76.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2109912 1.73% 78.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1768746 1.45% 79.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 935268 0.77% 80.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 726580 0.60% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23179490 19.02% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 122136825 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 121896437 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -592,466 +590,466 @@ system.cpu.commit.op_class_0::FloatMemWrite 14 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction -system.cpu.commit.bw_lim_events 23159047 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 443221536 # The number of ROB reads -system.cpu.rob.rob_writes 698006714 # The number of ROB writes -system.cpu.timesIdled 877 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 79480 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 23179490 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 442601652 # The number of ROB reads +system.cpu.rob.rob_writes 697313320 # The number of ROB writes +system.cpu.timesIdled 909 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 81995 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.833386 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.833386 # CPI: Total CPI of All Threads -system.cpu.ipc 1.199924 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.199924 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 502917784 # number of integer regfile reads -system.cpu.int_regfile_writes 247848787 # number of integer regfile writes -system.cpu.fp_regfile_reads 4075 # number of floating regfile reads -system.cpu.fp_regfile_writes 819 # number of floating regfile writes -system.cpu.cc_regfile_reads 109098841 # number of cc regfile reads -system.cpu.cc_regfile_writes 65494445 # number of cc regfile writes -system.cpu.misc_regfile_reads 201957201 # number of misc regfile reads +system.cpu.cpi 0.831978 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.831978 # CPI: Total CPI of All Threads +system.cpu.ipc 1.201955 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.201955 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 502529726 # number of integer regfile reads +system.cpu.int_regfile_writes 247564665 # number of integer regfile writes +system.cpu.fp_regfile_reads 3566 # number of floating regfile reads +system.cpu.fp_regfile_writes 731 # number of floating regfile writes +system.cpu.cc_regfile_reads 108994485 # number of cc regfile reads +system.cpu.cc_regfile_writes 65428204 # number of cc regfile writes +system.cpu.misc_regfile_reads 201784346 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2073306 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.354566 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 71520008 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2077402 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.427621 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 21024099500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.354566 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993006 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993006 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2073509 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.268199 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 71482624 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2077605 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.406263 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 21075173500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.268199 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992985 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992985 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 500 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3447 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 504 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3445 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 150691296 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 150691296 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 40173982 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40173982 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31346026 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31346026 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71520008 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71520008 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71520008 # number of overall hits -system.cpu.dcache.overall_hits::total 71520008 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2693213 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2693213 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 93726 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 93726 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2786939 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2786939 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2786939 # number of overall misses -system.cpu.dcache.overall_misses::total 2786939 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32416728500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32416728500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3181034987 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3181034987 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35597763487 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35597763487 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35597763487 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35597763487 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 42867195 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 42867195 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 150633517 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 150633517 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 40136683 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40136683 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31345941 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31345941 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71482624 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71482624 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71482624 # number of overall hits +system.cpu.dcache.overall_hits::total 71482624 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2701521 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2701521 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 93811 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 93811 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2795332 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2795332 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2795332 # number of overall misses +system.cpu.dcache.overall_misses::total 2795332 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32454671000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32454671000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3177582491 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3177582491 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35632253491 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35632253491 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35632253491 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35632253491 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 42838204 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 42838204 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74306947 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74306947 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74306947 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74306947 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062827 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.062827 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002981 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002981 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037506 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037506 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037506 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037506 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12036.451814 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12036.451814 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33939.728432 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33939.728432 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12773.068764 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12773.068764 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12773.068764 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12773.068764 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 220832 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 385 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 43178 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.114456 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 96.250000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2066926 # number of writebacks -system.cpu.dcache.writebacks::total 2066926 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 697625 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 697625 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11912 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 11912 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 709537 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 709537 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 709537 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 709537 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995588 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1995588 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81814 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 81814 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2077402 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2077402 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2077402 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2077402 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24271228500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24271228500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3023849487 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3023849487 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27295077987 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27295077987 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27295077987 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27295077987 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046553 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046553 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002602 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002602 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027957 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027957 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027957 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027957 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12162.444603 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12162.444603 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36960.049466 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36960.049466 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13139.044820 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13139.044820 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13139.044820 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13139.044820 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 93 # number of replacements -system.cpu.icache.tags.tagsinuse 878.108473 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 29762089 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1121 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26549.588760 # Average number of references to valid blocks. +system.cpu.dcache.demand_accesses::cpu.data 74277956 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74277956 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74277956 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74277956 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.063063 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.063063 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002984 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002984 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12013.480924 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12013.480924 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33872.173743 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33872.173743 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12747.055982 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12747.055982 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12747.055982 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12747.055982 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 219709 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 682 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 43158 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 6 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.090806 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 113.666667 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2066902 # number of writebacks +system.cpu.dcache.writebacks::total 2066902 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 705827 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 705827 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11900 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11900 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 717727 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 717727 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 717727 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 717727 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995694 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1995694 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81911 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 81911 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2077605 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2077605 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2077605 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2077605 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24272933500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24272933500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3020316491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3020316491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27293249991 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27293249991 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27293249991 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27293249991 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046587 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046587 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002605 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002605 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027971 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027971 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027971 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027971 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12162.652942 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12162.652942 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36873.148796 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36873.148796 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13136.881164 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13136.881164 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13136.881164 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13136.881164 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 86 # number of replacements +system.cpu.icache.tags.tagsinuse 865.699388 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 29658716 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1101 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 26937.980018 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 878.108473 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.428764 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.428764 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1028 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 38 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 910 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.501953 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 59528269 # Number of tag accesses -system.cpu.icache.tags.data_accesses 59528269 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 29762089 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 29762089 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 29762089 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 29762089 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 29762089 # number of overall hits -system.cpu.icache.overall_hits::total 29762089 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1485 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1485 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1485 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1485 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1485 # number of overall misses -system.cpu.icache.overall_misses::total 1485 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 149774999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 149774999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 149774999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 149774999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 149774999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 149774999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 29763574 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 29763574 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 29763574 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 29763574 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 29763574 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 29763574 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000050 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000050 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000050 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000050 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000050 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000050 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100858.585185 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 100858.585185 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 100858.585185 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 100858.585185 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 100858.585185 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 100858.585185 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2965 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 865.699388 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.422705 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.422705 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1015 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 900 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.495605 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 59321439 # Number of tag accesses +system.cpu.icache.tags.data_accesses 59321439 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 29658716 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 29658716 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 29658716 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 29658716 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 29658716 # number of overall hits +system.cpu.icache.overall_hits::total 29658716 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1453 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1453 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1453 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1453 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1453 # number of overall misses +system.cpu.icache.overall_misses::total 1453 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 154504998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 154504998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 154504998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 154504998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 154504998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 154504998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 29660169 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 29660169 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 29660169 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 29660169 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 29660169 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 29660169 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000049 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000049 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000049 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000049 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000049 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000049 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 106335.167240 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 106335.167240 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 106335.167240 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 106335.167240 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 106335.167240 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 106335.167240 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4008 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 211.785714 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 235.764706 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 93 # number of writebacks -system.cpu.icache.writebacks::total 93 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 364 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 364 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 364 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 364 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 364 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1121 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1121 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1121 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1121 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1121 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1121 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 114880499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 114880499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 114880499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 114880499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 114880499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 114880499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000038 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000038 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000038 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000038 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000038 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000038 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 102480.373773 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 102480.373773 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 102480.373773 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 102480.373773 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 102480.373773 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 102480.373773 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 694 # number of replacements -system.cpu.l2cache.tags.tagsinuse 21678.088627 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4121221 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 30681 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 134.324859 # Average number of references to valid blocks. +system.cpu.icache.writebacks::writebacks 86 # number of writebacks +system.cpu.icache.writebacks::total 86 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 352 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 352 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 352 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 352 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 352 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1101 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1101 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1101 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1101 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1101 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1101 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 113239998 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 113239998 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 113239998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 113239998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 113239998 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 113239998 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 102851.950954 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 102851.950954 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 102851.950954 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 102851.950954 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 102851.950954 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 102851.950954 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 680 # number of replacements +system.cpu.l2cache.tags.tagsinuse 21650.115816 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4121613 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 30665 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 134.407729 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2.638364 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 712.370564 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 20963.079700 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000081 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.021740 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.639742 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.661563 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29987 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 3.138386 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 704.921194 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 20942.056236 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000096 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.021512 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.639101 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.660709 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29985 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 186 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29624 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.915131 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 33245897 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 33245897 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2066926 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2066926 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 93 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 93 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 52858 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 52858 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 28 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 28 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1994973 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1994973 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2047831 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2047859 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2047831 # number of overall hits -system.cpu.l2cache.overall_hits::total 2047859 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 28990 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 28990 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1093 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1093 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 581 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 581 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1093 # number of demand (read+write) misses +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 172 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 54 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29640 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.915070 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 33248889 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 33248889 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 2066902 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2066902 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 86 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 86 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 52946 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 52946 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 26 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 26 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1995088 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1995088 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2048034 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2048060 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2048034 # number of overall hits +system.cpu.l2cache.overall_hits::total 2048060 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 28996 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 28996 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1075 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1075 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 575 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 575 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1075 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 29571 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 30664 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1093 # number of overall misses +system.cpu.l2cache.demand_misses::total 30646 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1075 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 29571 # number of overall misses -system.cpu.l2cache.overall_misses::total 30664 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2345791000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2345791000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 112890000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 112890000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 92689500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 92689500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 112890000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2438480500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2551370500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 112890000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2438480500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2551370500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2066926 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2066926 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 93 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 93 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 81848 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 81848 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1121 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1121 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1995554 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1995554 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1121 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2077402 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2078523 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1121 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2077402 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2078523 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.354193 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.354193 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.975022 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.975022 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000291 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000291 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.975022 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014235 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014753 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.975022 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014235 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014753 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80917.247327 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80917.247327 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103284.537969 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103284.537969 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 159534.423408 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 159534.423408 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103284.537969 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82461.888337 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83204.099270 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103284.537969 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82461.888337 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83204.099270 # average overall miss latency +system.cpu.l2cache.overall_misses::total 30646 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2341147500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2341147500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 111300000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 111300000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 88414500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 88414500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 111300000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2429562000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2540862000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 111300000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2429562000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2540862000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2066902 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2066902 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 86 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 86 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 81942 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 81942 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1101 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1101 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1995663 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1995663 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1101 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2077605 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2078706 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1101 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2077605 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2078706 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353860 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.353860 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.976385 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.976385 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000288 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000288 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.976385 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014233 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014743 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.976385 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014233 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014743 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80740.360739 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80740.360739 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103534.883721 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103534.883721 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 153764.347826 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 153764.347826 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103534.883721 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82160.292178 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82910.069830 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103534.883721 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82160.292178 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82910.069830 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 309 # number of writebacks -system.cpu.l2cache.writebacks::total 309 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28990 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 28990 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1093 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1093 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 581 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 581 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1093 # number of demand (read+write) MSHR misses +system.cpu.l2cache.writebacks::writebacks 299 # number of writebacks +system.cpu.l2cache.writebacks::total 299 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1075 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1075 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 575 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 575 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1075 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 29571 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30664 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1093 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30646 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1075 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 29571 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30664 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2055891000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2055891000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 101960000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 101960000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 86879500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 86879500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 101960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2142770500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2244730500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 101960000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2142770500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2244730500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.354193 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.354193 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.975022 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.975022 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000291 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000291 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.975022 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014235 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014753 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.975022 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014235 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014753 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70917.247327 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70917.247327 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93284.537969 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93284.537969 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 149534.423408 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 149534.423408 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93284.537969 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72461.888337 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73204.099270 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93284.537969 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72461.888337 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73204.099270 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4151922 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073402 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 20 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 335 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 335 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_misses::total 30646 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2051187500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2051187500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 100550000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 100550000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 82664500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 82664500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 100550000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2133852000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2234402000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 100550000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2133852000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2234402000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353860 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353860 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.976385 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.976385 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000288 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000288 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.976385 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014233 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014743 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.976385 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014233 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014743 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70740.360739 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70740.360739 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93534.883721 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93534.883721 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 143764.347826 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 143764.347826 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93534.883721 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72160.292178 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72910.069830 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93534.883721 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72160.292178 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72910.069830 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4152301 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073596 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 330 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 330 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1996675 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2067235 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 93 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6765 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 81848 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 81848 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1121 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995554 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2335 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228110 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6230445 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265236992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265314688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 694 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 19776 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2079217 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000172 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.013121 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1996764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2067201 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 86 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6988 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 81942 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 81942 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1101 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995663 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2288 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228719 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6231007 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 75968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265248448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265324416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 680 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 19136 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2079386 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000170 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.013047 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2078859 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 358 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2079032 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 354 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2079217 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4142980000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2079386 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4143138500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1681500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1652498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3116103000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3116407500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 31023 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 359 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 30996 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 350 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1674 # Transaction distribution -system.membus.trans_dist::WritebackDirty 309 # Transaction distribution -system.membus.trans_dist::CleanEvict 50 # Transaction distribution -system.membus.trans_dist::ReadExReq 28990 # Transaction distribution -system.membus.trans_dist::ReadExResp 28990 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1674 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61687 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61687 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61687 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1982272 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1982272 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1982272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1650 # Transaction distribution +system.membus.trans_dist::WritebackDirty 299 # Transaction distribution +system.membus.trans_dist::CleanEvict 51 # Transaction distribution +system.membus.trans_dist::ReadExReq 28996 # Transaction distribution +system.membus.trans_dist::ReadExResp 28996 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1650 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61642 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61642 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61642 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1980480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1980480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1980480 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 30664 # Request fanout histogram +system.membus.snoop_fanout::samples 30646 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30664 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 30646 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30664 # Request fanout histogram -system.membus.reqLayer0.occupancy 43676000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 30646 # Request fanout histogram +system.membus.reqLayer0.occupancy 43591500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 161581250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 161486250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 5f5ab2bca..4152fbfe4 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.368600 # Number of seconds simulated -sim_ticks 368600047500 # Number of ticks simulated -final_tick 368600047500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.368651 # Number of seconds simulated +sim_ticks 368651185500 # Number of ticks simulated +final_tick 368651185500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 377886 # Simulator instruction rate (inst/s) -host_op_rate 409300 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 274959159 # Simulator tick rate (ticks/s) -host_mem_usage 276756 # Number of bytes of host memory used -host_seconds 1340.56 # Real time elapsed on the host +host_inst_rate 378825 # Simulator instruction rate (inst/s) +host_op_rate 410318 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 275680946 # Simulator tick rate (ticks/s) +host_mem_usage 276920 # Number of bytes of host memory used +host_seconds 1337.24 # Real time elapsed on the host sim_insts 506579366 # Number of instructions simulated sim_ops 548692589 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 179840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9053376 # Number of bytes read from this memory -system.physmem.bytes_read::total 9233216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 179840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 179840 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6241792 # Number of bytes written to this memory -system.physmem.bytes_written::total 6241792 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2810 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141459 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144269 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97528 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97528 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 487900 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24561516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25049416 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 487900 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 487900 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 16933780 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 16933780 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 16933780 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 487900 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24561516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41983196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 144269 # Number of read requests accepted -system.physmem.writeReqs 97528 # Number of write requests accepted -system.physmem.readBursts 144269 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97528 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9225856 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue -system.physmem.bytesWritten 6240448 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9233216 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6241792 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 179712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9049216 # Number of bytes read from this memory +system.physmem.bytes_read::total 9228928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 179712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 179712 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6241472 # Number of bytes written to this memory +system.physmem.bytes_written::total 6241472 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2808 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141394 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144202 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97523 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97523 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 487485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24546825 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25034310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 487485 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 487485 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 16930563 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 16930563 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 16930563 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 487485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24546825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41964873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144202 # Number of read requests accepted +system.physmem.writeReqs 97523 # Number of write requests accepted +system.physmem.readBursts 144202 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97523 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9222208 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue +system.physmem.bytesWritten 6240000 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9228928 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6241472 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9372 # Per bank write bursts -system.physmem.perBankRdBursts::1 8929 # Per bank write bursts -system.physmem.perBankRdBursts::2 8963 # Per bank write bursts -system.physmem.perBankRdBursts::3 8667 # Per bank write bursts -system.physmem.perBankRdBursts::4 9424 # Per bank write bursts -system.physmem.perBankRdBursts::5 9372 # Per bank write bursts -system.physmem.perBankRdBursts::6 8974 # Per bank write bursts -system.physmem.perBankRdBursts::7 8127 # Per bank write bursts -system.physmem.perBankRdBursts::8 8635 # Per bank write bursts -system.physmem.perBankRdBursts::9 8697 # Per bank write bursts -system.physmem.perBankRdBursts::10 8761 # Per bank write bursts -system.physmem.perBankRdBursts::11 9485 # Per bank write bursts -system.physmem.perBankRdBursts::12 9346 # Per bank write bursts -system.physmem.perBankRdBursts::13 9545 # Per bank write bursts -system.physmem.perBankRdBursts::14 8729 # Per bank write bursts -system.physmem.perBankRdBursts::15 9128 # Per bank write bursts -system.physmem.perBankWrBursts::0 6253 # Per bank write bursts -system.physmem.perBankWrBursts::1 6118 # Per bank write bursts -system.physmem.perBankWrBursts::2 6042 # Per bank write bursts -system.physmem.perBankWrBursts::3 5901 # Per bank write bursts -system.physmem.perBankWrBursts::4 6273 # Per bank write bursts -system.physmem.perBankWrBursts::5 6263 # Per bank write bursts -system.physmem.perBankWrBursts::6 6069 # Per bank write bursts +system.physmem.perBankRdBursts::0 9327 # Per bank write bursts +system.physmem.perBankRdBursts::1 8931 # Per bank write bursts +system.physmem.perBankRdBursts::2 8953 # Per bank write bursts +system.physmem.perBankRdBursts::3 8672 # Per bank write bursts +system.physmem.perBankRdBursts::4 9421 # Per bank write bursts +system.physmem.perBankRdBursts::5 9371 # Per bank write bursts +system.physmem.perBankRdBursts::6 8975 # Per bank write bursts +system.physmem.perBankRdBursts::7 8126 # Per bank write bursts +system.physmem.perBankRdBursts::8 8631 # Per bank write bursts +system.physmem.perBankRdBursts::9 8699 # Per bank write bursts +system.physmem.perBankRdBursts::10 8760 # Per bank write bursts +system.physmem.perBankRdBursts::11 9484 # Per bank write bursts +system.physmem.perBankRdBursts::12 9351 # Per bank write bursts +system.physmem.perBankRdBursts::13 9541 # Per bank write bursts +system.physmem.perBankRdBursts::14 8731 # Per bank write bursts +system.physmem.perBankRdBursts::15 9124 # Per bank write bursts +system.physmem.perBankWrBursts::0 6232 # Per bank write bursts +system.physmem.perBankWrBursts::1 6121 # Per bank write bursts +system.physmem.perBankWrBursts::2 6045 # Per bank write bursts +system.physmem.perBankWrBursts::3 5902 # Per bank write bursts +system.physmem.perBankWrBursts::4 6267 # Per bank write bursts +system.physmem.perBankWrBursts::5 6264 # Per bank write bursts +system.physmem.perBankWrBursts::6 6070 # Per bank write bursts system.physmem.perBankWrBursts::7 5535 # Per bank write bursts system.physmem.perBankWrBursts::8 5819 # Per bank write bursts -system.physmem.perBankWrBursts::9 5920 # Per bank write bursts +system.physmem.perBankWrBursts::9 5921 # Per bank write bursts system.physmem.perBankWrBursts::10 5985 # Per bank write bursts -system.physmem.perBankWrBursts::11 6510 # Per bank write bursts -system.physmem.perBankWrBursts::12 6360 # Per bank write bursts -system.physmem.perBankWrBursts::13 6344 # Per bank write bursts -system.physmem.perBankWrBursts::14 6013 # Per bank write bursts +system.physmem.perBankWrBursts::11 6509 # Per bank write bursts +system.physmem.perBankWrBursts::12 6365 # Per bank write bursts +system.physmem.perBankWrBursts::13 6345 # Per bank write bursts +system.physmem.perBankWrBursts::14 6018 # Per bank write bursts system.physmem.perBankWrBursts::15 6102 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 368600022000 # Total gap between requests +system.physmem.totGap 368651160000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144269 # Read request sizes (log2) +system.physmem.readPktSize::6 144202 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97528 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143801 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97523 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143745 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -145,32 +145,32 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2868 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5746 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 5746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see @@ -194,116 +194,116 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63970 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 241.763327 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 162.115864 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.210402 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22774 35.60% 35.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18302 28.61% 64.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7461 11.66% 75.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8049 12.58% 88.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2117 3.31% 91.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1180 1.84% 93.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 776 1.21% 94.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 623 0.97% 95.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2688 4.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63970 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5740 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.113240 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 375.658190 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5737 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 64014 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 241.533165 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 161.867212 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.438904 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22835 35.67% 35.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18294 28.58% 64.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7516 11.74% 75.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7993 12.49% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2085 3.26% 91.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1176 1.84% 93.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 786 1.23% 94.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 642 1.00% 95.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2687 4.20% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64014 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5742 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.094566 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 375.615355 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5739 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5740 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5740 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.987282 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.957535 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.009458 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2852 49.69% 49.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 159 2.77% 52.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 2701 47.06% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 19 0.33% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 6 0.10% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5740 # Writes before turning the bus around for reads -system.physmem.totQLat 3577410500 # Total ticks spent queuing -system.physmem.totMemAccLat 6280298000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 720770000 # Total ticks spent in databus transfers -system.physmem.avgQLat 24816.59 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5742 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5742 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.980146 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.950575 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.005103 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2875 50.07% 50.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 152 2.65% 52.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 2688 46.81% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 17 0.30% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 6 0.10% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5742 # Writes before turning the bus around for reads +system.physmem.totQLat 3587327500 # Total ticks spent queuing +system.physmem.totMemAccLat 6289146250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 720485000 # Total ticks spent in databus transfers +system.physmem.avgQLat 24895.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43566.59 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.03 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 43645.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.02 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 16.93 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.05 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.03 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 16.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.06 # Average write queue length when enqueuing -system.physmem.readRowHits 110541 # Number of row buffer hits during reads -system.physmem.writeRowHits 67141 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.68 # Row buffer hit rate for reads +system.physmem.avgWrQLen 19.95 # Average write queue length when enqueuing +system.physmem.readRowHits 110436 # Number of row buffer hits during reads +system.physmem.writeRowHits 67138 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.64 # Row buffer hit rate for reads system.physmem.writeRowHitRate 68.84 # Row buffer hit rate for writes -system.physmem.avgGap 1524419.34 # Average gap between requests -system.physmem.pageHitRate 73.52 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229615260 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 122028225 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 512851920 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 252929880 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 7711888080.000002 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3985232520 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 353635200 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 24742392420 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 8329190880 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 68838786810 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 115080429525 # Total energy per rank (pJ) -system.physmem_0.averagePower 312.209478 # Core power per rank (mW) -system.physmem_0.totalIdleTime 358934929250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 533175250 # Time in different power states -system.physmem_0.memoryStateTime::REF 3272498000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 282985158000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 21690772000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5858998750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 54259445500 # Time in different power states -system.physmem_1.actEnergy 227194800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 120737925 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 516407640 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 256056660 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 7588960080.000002 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3990680010 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 342748800 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 24389261460 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 8128903200 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 69135043560 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 114698287785 # Total energy per rank (pJ) -system.physmem_1.averagePower 311.172742 # Core power per rank (mW) -system.physmem_1.totalIdleTime 358951299500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 511434000 # Time in different power states -system.physmem_1.memoryStateTime::REF 3220288000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 284296687500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 21168817000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 5916972250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 53485848750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 132103819 # Number of BP lookups -system.cpu.branchPred.condPredicted 98193306 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5910048 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68601561 # Number of BTB lookups -system.cpu.branchPred.BTBHits 60590477 # Number of BTB hits +system.physmem.avgGap 1525084.95 # Average gap between requests +system.physmem.pageHitRate 73.49 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 229772340 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 122107920 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 512480640 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 252835920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 7717419840.000002 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4012679730 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 354856800 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 24782953050 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8303052480 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 68829850950 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 115120015110 # Total energy per rank (pJ) +system.physmem_0.averagePower 312.273551 # Core power per rank (mW) +system.physmem_0.totalIdleTime 358922434750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 536706250 # Time in different power states +system.physmem_0.memoryStateTime::REF 3274898000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 282951785250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 21622731000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 5916696250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 54348368750 # Time in different power states +system.physmem_1.actEnergy 227351880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 120825210 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 516371940 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 256114080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 7627682400.000002 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3951722790 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 344311680 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 24510614460 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 8148381600 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 69110361900 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 114816583080 # Total energy per rank (pJ) +system.physmem_1.averagePower 311.450463 # Core power per rank (mW) +system.physmem_1.totalIdleTime 359082796500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 515499000 # Time in different power states +system.physmem_1.memoryStateTime::REF 3236866000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 284111116500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 21219892250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 5815970250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 53751841500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 132096754 # Number of BP lookups +system.cpu.branchPred.condPredicted 98183062 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5916233 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68556674 # Number of BTB lookups +system.cpu.branchPred.BTBHits 60606255 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.322301 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 10017121 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 18743 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3891575 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 3883028 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 8547 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 54138 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 88.403144 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 10020256 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 19127 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3891736 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 3883139 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 8597 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 54132 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -333,7 +333,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -363,7 +363,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -393,7 +393,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -424,16 +424,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 368600047500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 737200095 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 368651185500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 737302371 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506579366 # Number of instructions committed system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed -system.cpu.discardedOps 12939783 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 12932918 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.455251 # CPI: cycles per instruction -system.cpu.ipc 0.687167 # IPC: instructions per cycle +system.cpu.cpi 1.455453 # CPI: cycles per instruction +system.cpu.ipc 0.687071 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 375609862 68.46% 68.46% # Class of committed instruction system.cpu.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction @@ -473,346 +473,346 @@ system.cpu.op_class_0::FloatMemWrite 16 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 548692589 # Class of committed instruction -system.cpu.tickCycles 694074449 # Number of cycles that the object actually ticked -system.cpu.idleCycles 43125646 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1141337 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.214598 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171083823 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1145433 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.361703 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5072633500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.214598 # Average occupied blocks per requestor +system.cpu.tickCycles 694166450 # Number of cycles that the object actually ticked +system.cpu.idleCycles 43135921 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1141334 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.216677 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171085721 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1145430 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.363751 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5072789500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.216677 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993705 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993705 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 543 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 548 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3502 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346338043 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346338043 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 114566012 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114566012 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53537935 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53537935 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2794 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2794 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 346341652 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346341652 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 114567880 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114567880 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53537967 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53537967 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2792 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2792 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168103947 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168103947 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168106741 # number of overall hits -system.cpu.dcache.overall_hits::total 168106741 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 811353 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 811353 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 701114 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 701114 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 168105847 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168105847 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168108639 # number of overall hits +system.cpu.dcache.overall_hits::total 168108639 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 811293 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 811293 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 701082 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 701082 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1512467 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1512467 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1512482 # number of overall misses -system.cpu.dcache.overall_misses::total 1512482 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14511839000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14511839000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24015670000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24015670000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 38527509000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 38527509000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 38527509000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 38527509000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115377365 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115377365 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1512375 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1512375 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1512390 # number of overall misses +system.cpu.dcache.overall_misses::total 1512390 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14512864500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14512864500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24025186500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24025186500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 38538051000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 38538051000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 38538051000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 38538051000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115379173 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115379173 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2809 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2809 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2807 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2807 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169616414 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169616414 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169619223 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169619223 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 169618222 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169618222 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169621029 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169621029 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007032 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.007032 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012926 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.012926 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005340 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.005340 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008917 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008917 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008917 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008917 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17885.974416 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17885.974416 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34253.587862 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34253.587862 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25473.289004 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25473.289004 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25473.036373 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25473.036373 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005344 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.005344 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008916 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008916 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008916 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008916 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17888.561223 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17888.561223 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34268.725342 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34268.725342 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25481.809075 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25481.809075 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25481.556345 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25481.556345 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1068942 # number of writebacks -system.cpu.dcache.writebacks::total 1068942 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22320 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 22320 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344726 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344726 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 367046 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 367046 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 367046 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 367046 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 789033 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 789033 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356388 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356388 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 1068964 # number of writebacks +system.cpu.dcache.writebacks::total 1068964 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22242 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 22242 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344715 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344715 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 366957 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 366957 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 366957 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 366957 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 789051 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 789051 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356367 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356367 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1145421 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1145421 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1145433 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1145433 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13416892000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 13416892000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12196191500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12196191500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 4297000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 4297000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25613083500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25613083500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25617380500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 25617380500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1145418 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1145418 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1145430 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1145430 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13418418500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 13418418500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12201205500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12201205500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 4179500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 4179500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25619624000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25619624000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25623803500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 25623803500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006839 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006839 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006571 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006571 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004272 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004272 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006570 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006570 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004275 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004275 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006753 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006753 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17004.221623 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17004.221623 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34221.667116 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34221.667116 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 358083.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 358083.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22361.283319 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22361.283319 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22364.800473 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22364.800473 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 18178 # number of replacements -system.cpu.icache.tags.tagsinuse 1186.508929 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 199149019 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 20050 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 9932.619401 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17005.768322 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17005.768322 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34237.753496 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34237.753496 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 348291.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 348291.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22367.052028 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22367.052028 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22370.466550 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22370.466550 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 18132 # number of replacements +system.cpu.icache.tags.tagsinuse 1186.493230 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 199187334 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 20004 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 9957.375225 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1186.508929 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.579350 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.579350 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1186.493230 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.579342 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.579342 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 311 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1400 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 318 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1398 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 398358188 # Number of tag accesses -system.cpu.icache.tags.data_accesses 398358188 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 199149019 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 199149019 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 199149019 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 199149019 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 199149019 # number of overall hits -system.cpu.icache.overall_hits::total 199149019 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 20050 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 20050 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 20050 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 20050 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 20050 # number of overall misses -system.cpu.icache.overall_misses::total 20050 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 544279500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 544279500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 544279500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 544279500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 544279500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 544279500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 199169069 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 199169069 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 199169069 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 199169069 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 199169069 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 199169069 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000101 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000101 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000101 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000101 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000101 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000101 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27146.109726 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27146.109726 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27146.109726 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27146.109726 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27146.109726 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27146.109726 # average overall miss latency +system.cpu.icache.tags.tag_accesses 398434680 # Number of tag accesses +system.cpu.icache.tags.data_accesses 398434680 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 199187334 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 199187334 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 199187334 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 199187334 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 199187334 # number of overall hits +system.cpu.icache.overall_hits::total 199187334 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 20004 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 20004 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 20004 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 20004 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 20004 # number of overall misses +system.cpu.icache.overall_misses::total 20004 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 543340500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 543340500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 543340500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 543340500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 543340500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 543340500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 199207338 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 199207338 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 199207338 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 199207338 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 199207338 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 199207338 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000100 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000100 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000100 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000100 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000100 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000100 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27161.592681 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27161.592681 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27161.592681 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27161.592681 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27161.592681 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27161.592681 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 18178 # number of writebacks -system.cpu.icache.writebacks::total 18178 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20050 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 20050 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 20050 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 20050 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 20050 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 20050 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 524229500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 524229500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 524229500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 524229500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 524229500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 524229500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000101 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26146.109726 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26146.109726 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26146.109726 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26146.109726 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26146.109726 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26146.109726 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 112761 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29076.848035 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2174458 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 145529 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.941750 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 102118428000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 133.889045 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.541066 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28635.417923 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.004086 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009385 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.873884 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.887355 # Average percentage of cache occupancy +system.cpu.icache.writebacks::writebacks 18132 # number of writebacks +system.cpu.icache.writebacks::total 18132 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20004 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 20004 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 20004 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 20004 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 20004 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 20004 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 523336500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 523336500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 523336500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 523336500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 523336500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 523336500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000100 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000100 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000100 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000100 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000100 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000100 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26161.592681 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26161.592681 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26161.592681 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26161.592681 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26161.592681 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26161.592681 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 112700 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29077.009680 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2174426 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 145468 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.947796 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 102124248000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 135.271970 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 308.139631 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28633.598078 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.004128 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009404 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.873828 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.887360 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 981 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31589 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 114 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 988 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31579 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18705537 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18705537 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 1068942 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 1068942 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 17940 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 17940 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 255660 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255660 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17239 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 17239 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 748301 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 748301 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 17239 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1003961 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1021200 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 17239 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1003961 # number of overall hits -system.cpu.l2cache.overall_hits::total 1021200 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 100978 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 100978 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2811 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2811 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 40494 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 40494 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2811 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 141472 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 144283 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2811 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 141472 # number of overall misses -system.cpu.l2cache.overall_misses::total 144283 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8979653500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8979653500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 312476000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 312476000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4360668500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4360668500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 312476000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13340322000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13652798000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 312476000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13340322000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13652798000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 1068942 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 1068942 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 17940 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 17940 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 356638 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 356638 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 20050 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 20050 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 788795 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 788795 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 20050 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1145433 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1165483 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 20050 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1145433 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1165483 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283139 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.283139 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140200 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140200 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.051337 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.051337 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.140200 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.123510 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123797 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140200 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.123510 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123797 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88926.830597 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88926.830597 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 111161.864105 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 111161.864105 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 107686.780758 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 107686.780758 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111161.864105 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94296.553382 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 94625.132552 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111161.864105 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94296.553382 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 94625.132552 # average overall miss latency +system.cpu.l2cache.tags.tag_accesses 18704732 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18704732 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 1068964 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 1068964 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 17895 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 17895 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 255662 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 255662 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17195 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 17195 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 748361 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 748361 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 17195 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1004023 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1021218 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 17195 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1004023 # number of overall hits +system.cpu.l2cache.overall_hits::total 1021218 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 100957 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 100957 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2809 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2809 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 40450 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 40450 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2809 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 141407 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 144216 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2809 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 141407 # number of overall misses +system.cpu.l2cache.overall_misses::total 144216 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8984700500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8984700500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 312111000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 312111000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4361406500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4361406500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 312111000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13346107000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13658218000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 312111000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13346107000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13658218000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 1068964 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 1068964 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 17895 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 17895 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 356619 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 356619 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 20004 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 20004 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 788811 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 788811 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 20004 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1145430 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1165434 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 20004 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1145430 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1165434 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283095 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.283095 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140422 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140422 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.051280 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.051280 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.140422 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.123453 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123744 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140422 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.123453 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123744 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88995.319790 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88995.319790 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 111111.071556 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 111111.071556 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 107822.163164 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 107822.163164 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111111.071556 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94380.808588 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 94706.676097 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111111.071556 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94380.808588 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 94706.676097 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 97528 # number of writebacks -system.cpu.l2cache.writebacks::total 97528 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 97523 # number of writebacks +system.cpu.l2cache.writebacks::total 97523 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 13 # number of ReadSharedReq MSHR hits @@ -823,126 +823,126 @@ system.cpu.l2cache.demand_mshr_hits::total 14 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100978 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100978 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2810 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2810 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40481 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40481 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2810 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 141459 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 144269 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2810 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 141459 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 144269 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7969873500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7969873500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 284301000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 284301000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3953966500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3953966500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 284301000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11923840000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12208141000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 284301000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11923840000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12208141000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283139 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283139 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140150 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140150 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.051320 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.051320 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140150 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123785 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140150 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123785 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.830597 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.830597 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101174.733096 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101174.733096 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97674.625133 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97674.625133 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101174.733096 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84291.844280 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84620.680812 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101174.733096 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84291.844280 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84620.680812 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 2324998 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159585 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100957 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100957 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2808 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2808 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40437 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40437 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2808 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 141394 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 144202 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2808 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141394 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 144202 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7975130500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7975130500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 283956000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 283956000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3955182000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3955182000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 283956000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11930312500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12214268500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 283956000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11930312500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12214268500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283095 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283095 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140372 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140372 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.051263 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.051263 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140372 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123442 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123732 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140372 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123442 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123732 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78995.319790 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78995.319790 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101123.931624 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101123.931624 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97810.965205 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97810.965205 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101123.931624 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84376.370284 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84702.490257 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101123.931624 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84376.370284 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84702.490257 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 2324900 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159536 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4992 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 2618 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2615 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 808845 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1166470 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 18178 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 87628 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356638 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356638 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 20050 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 788795 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58278 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432203 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3490481 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2446592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141720000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 144166592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 112761 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6241792 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1278244 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.006015 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.077350 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 808815 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1166487 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 18132 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 87547 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356619 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356619 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 20004 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 788811 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58140 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432194 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3490334 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2440704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141721216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 144161920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 112700 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6241472 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1278134 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.006011 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.077328 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1270559 99.40% 99.40% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 7682 0.60% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1270454 99.40% 99.40% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 7677 0.60% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1278244 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2249619000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1278134 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2249546000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 30098453 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 30029453 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1718157983 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1718153483 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 254412 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 110315 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 254284 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 110251 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 43291 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97528 # Transaction distribution -system.membus.trans_dist::CleanEvict 12615 # Transaction distribution -system.membus.trans_dist::ReadExReq 100978 # Transaction distribution -system.membus.trans_dist::ReadExResp 100978 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 43291 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398681 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 398681 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15475008 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15475008 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 43245 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97523 # Transaction distribution +system.membus.trans_dist::CleanEvict 12559 # Transaction distribution +system.membus.trans_dist::ReadExReq 100957 # Transaction distribution +system.membus.trans_dist::ReadExResp 100957 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 43245 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398486 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 398486 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15470400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15470400 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 144269 # Request fanout histogram +system.membus.snoop_fanout::samples 144202 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 144269 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 144202 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 144269 # Request fanout histogram -system.membus.reqLayer0.occupancy 685127000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 144202 # Request fanout histogram +system.membus.reqLayer0.occupancy 684899000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 765884750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 765515250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 3dfc36814..d29a9ad2d 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.236024 # Number of seconds simulated -sim_ticks 236023688000 # Number of ticks simulated -final_tick 236023688000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.235850 # Number of seconds simulated +sim_ticks 235850129000 # Number of ticks simulated +final_tick 235850129000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 256452 # Simulator instruction rate (inst/s) -host_op_rate 277829 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 119803336 # Simulator tick rate (ticks/s) -host_mem_usage 301968 # Number of bytes of host memory used -host_seconds 1970.09 # Real time elapsed on the host +host_inst_rate 254127 # Simulator instruction rate (inst/s) +host_op_rate 275309 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 118629630 # Simulator tick rate (ticks/s) +host_mem_usage 302132 # Number of bytes of host memory used +host_seconds 1988.12 # Real time elapsed on the host sim_insts 505234934 # Number of instructions simulated sim_ops 547348155 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 640832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10509760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16394496 # Number of bytes read from this memory -system.physmem.bytes_read::total 27545088 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 640832 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 640832 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18630208 # Number of bytes written to this memory -system.physmem.bytes_written::total 18630208 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10013 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 164215 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 256164 # Number of read requests responded to by this memory -system.physmem.num_reads::total 430392 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 291097 # Number of write requests responded to by this memory -system.physmem.num_writes::total 291097 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2715117 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 44528412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 69461231 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 116704761 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2715117 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2715117 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 78933637 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 78933637 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 78933637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2715117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 44528412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 69461231 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 195638397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 430392 # Number of read requests accepted -system.physmem.writeReqs 291097 # Number of write requests accepted -system.physmem.readBursts 430392 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 291097 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 27379648 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 165440 # Total number of bytes read from write queue -system.physmem.bytesWritten 18628032 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 27545088 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18630208 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2585 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 651264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10497792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16410048 # Number of bytes read from this memory +system.physmem.bytes_read::total 27559104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 651264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 651264 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18653440 # Number of bytes written to this memory +system.physmem.bytes_written::total 18653440 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10176 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 164028 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 256407 # Number of read requests responded to by this memory +system.physmem.num_reads::total 430611 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 291460 # Number of write requests responded to by this memory +system.physmem.num_writes::total 291460 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2761347 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 44510436 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 69578287 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 116850070 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2761347 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2761347 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 79090226 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 79090226 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 79090226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2761347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 44510436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 69578287 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 195940296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 430611 # Number of read requests accepted +system.physmem.writeReqs 291460 # Number of write requests accepted +system.physmem.readBursts 430611 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 291460 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 27396288 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 162816 # Total number of bytes read from write queue +system.physmem.bytesWritten 18651392 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27559104 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18653440 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2544 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 9 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 27300 # Per bank write bursts -system.physmem.perBankRdBursts::1 26589 # Per bank write bursts -system.physmem.perBankRdBursts::2 25489 # Per bank write bursts -system.physmem.perBankRdBursts::3 32817 # Per bank write bursts -system.physmem.perBankRdBursts::4 28238 # Per bank write bursts -system.physmem.perBankRdBursts::5 30052 # Per bank write bursts -system.physmem.perBankRdBursts::6 25322 # Per bank write bursts -system.physmem.perBankRdBursts::7 24428 # Per bank write bursts -system.physmem.perBankRdBursts::8 25638 # Per bank write bursts -system.physmem.perBankRdBursts::9 25508 # Per bank write bursts -system.physmem.perBankRdBursts::10 25695 # Per bank write bursts -system.physmem.perBankRdBursts::11 26146 # Per bank write bursts -system.physmem.perBankRdBursts::12 27543 # Per bank write bursts -system.physmem.perBankRdBursts::13 26122 # Per bank write bursts -system.physmem.perBankRdBursts::14 24924 # Per bank write bursts -system.physmem.perBankRdBursts::15 25996 # Per bank write bursts -system.physmem.perBankWrBursts::0 18688 # Per bank write bursts -system.physmem.perBankWrBursts::1 18252 # Per bank write bursts -system.physmem.perBankWrBursts::2 17892 # Per bank write bursts -system.physmem.perBankWrBursts::3 17877 # Per bank write bursts -system.physmem.perBankWrBursts::4 18635 # Per bank write bursts -system.physmem.perBankWrBursts::5 18189 # Per bank write bursts -system.physmem.perBankWrBursts::6 17877 # Per bank write bursts -system.physmem.perBankWrBursts::7 17743 # Per bank write bursts -system.physmem.perBankWrBursts::8 17943 # Per bank write bursts -system.physmem.perBankWrBursts::9 17697 # Per bank write bursts -system.physmem.perBankWrBursts::10 18014 # Per bank write bursts -system.physmem.perBankWrBursts::11 18785 # Per bank write bursts -system.physmem.perBankWrBursts::12 18684 # Per bank write bursts -system.physmem.perBankWrBursts::13 18184 # Per bank write bursts -system.physmem.perBankWrBursts::14 18324 # Per bank write bursts -system.physmem.perBankWrBursts::15 18279 # Per bank write bursts +system.physmem.perBankRdBursts::0 27102 # Per bank write bursts +system.physmem.perBankRdBursts::1 26174 # Per bank write bursts +system.physmem.perBankRdBursts::2 25664 # Per bank write bursts +system.physmem.perBankRdBursts::3 33006 # Per bank write bursts +system.physmem.perBankRdBursts::4 27996 # Per bank write bursts +system.physmem.perBankRdBursts::5 29984 # Per bank write bursts +system.physmem.perBankRdBursts::6 25487 # Per bank write bursts +system.physmem.perBankRdBursts::7 24586 # Per bank write bursts +system.physmem.perBankRdBursts::8 25526 # Per bank write bursts +system.physmem.perBankRdBursts::9 25681 # Per bank write bursts +system.physmem.perBankRdBursts::10 25862 # Per bank write bursts +system.physmem.perBankRdBursts::11 26092 # Per bank write bursts +system.physmem.perBankRdBursts::12 27614 # Per bank write bursts +system.physmem.perBankRdBursts::13 26106 # Per bank write bursts +system.physmem.perBankRdBursts::14 25123 # Per bank write bursts +system.physmem.perBankRdBursts::15 26064 # Per bank write bursts +system.physmem.perBankWrBursts::0 18530 # Per bank write bursts +system.physmem.perBankWrBursts::1 18172 # Per bank write bursts +system.physmem.perBankWrBursts::2 17960 # Per bank write bursts +system.physmem.perBankWrBursts::3 17946 # Per bank write bursts +system.physmem.perBankWrBursts::4 18535 # Per bank write bursts +system.physmem.perBankWrBursts::5 18092 # Per bank write bursts +system.physmem.perBankWrBursts::6 17937 # Per bank write bursts +system.physmem.perBankWrBursts::7 17864 # Per bank write bursts +system.physmem.perBankWrBursts::8 17881 # Per bank write bursts +system.physmem.perBankWrBursts::9 17814 # Per bank write bursts +system.physmem.perBankWrBursts::10 18253 # Per bank write bursts +system.physmem.perBankWrBursts::11 18685 # Per bank write bursts +system.physmem.perBankWrBursts::12 18794 # Per bank write bursts +system.physmem.perBankWrBursts::13 18180 # Per bank write bursts +system.physmem.perBankWrBursts::14 18427 # Per bank write bursts +system.physmem.perBankWrBursts::15 18358 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 236023635500 # Total gap between requests +system.physmem.totGap 235850076500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 430392 # Read request sizes (log2) +system.physmem.readPktSize::6 430611 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 291097 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 318668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 60537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8917 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6198 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3249 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 78 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 10 # What read queue length does an incoming req see +system.physmem.writePktSize::6 291460 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 318665 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 60579 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9026 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3288 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 74 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -149,37 +149,37 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 14859 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17602 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 18085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 18833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 14838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17893 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 18126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see @@ -198,127 +198,123 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 328591 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 140.009775 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 98.675291 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 178.430270 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 209431 63.74% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 79588 24.22% 87.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14900 4.53% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7308 2.22% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4939 1.50% 96.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2586 0.79% 97.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1820 0.55% 97.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1543 0.47% 98.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6476 1.97% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 328591 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17028 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.118628 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 145.022717 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17026 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 329170 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 139.885214 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 98.537517 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 178.782393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 210239 63.87% 63.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 79533 24.16% 88.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14816 4.50% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7238 2.20% 94.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4909 1.49% 96.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2469 0.75% 96.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1818 0.55% 97.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1563 0.47% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6585 2.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 329170 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17054 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.096224 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 145.074041 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17052 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17028 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17028 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.093199 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.022957 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.821852 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 10045 58.99% 58.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 6192 36.36% 95.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 538 3.16% 98.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 158 0.93% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 50 0.29% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 18 0.11% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 8 0.05% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 3 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 4 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 3 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::70-71 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::90-91 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-93 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17028 # Writes before turning the bus around for reads -system.physmem.totQLat 14230918095 # Total ticks spent queuing -system.physmem.totMemAccLat 22252299345 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2139035000 # Total ticks spent in databus transfers -system.physmem.avgQLat 33264.81 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17054 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17054 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.088542 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.022727 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.689258 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 9980 58.52% 58.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 6296 36.92% 95.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 558 3.27% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 128 0.75% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 50 0.29% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 15 0.09% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 10 0.06% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 6 0.04% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 2 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 3 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::62-63 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::74-75 2 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17054 # Writes before turning the bus around for reads +system.physmem.totQLat 14249250266 # Total ticks spent queuing +system.physmem.totMemAccLat 22275506516 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2140335000 # Total ticks spent in databus transfers +system.physmem.avgQLat 33287.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 52014.81 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 116.00 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 78.92 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 116.70 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 78.93 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 52037.43 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 116.16 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 79.08 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 116.85 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 79.09 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.52 # Data bus utilization in percentage +system.physmem.busUtil 1.53 # Data bus utilization in percentage system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.62 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.76 # Average write queue length when enqueuing -system.physmem.readRowHits 308090 # Number of row buffer hits during reads -system.physmem.writeRowHits 82180 # Number of row buffer hits during writes -system.physmem.readRowHitRate 72.02 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 28.23 # Row buffer hit rate for writes -system.physmem.avgGap 327134.07 # Average gap between requests -system.physmem.pageHitRate 54.29 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1195143180 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 635214690 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1572477900 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 757698660 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15717574080.000004 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 13455213090 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 610838880 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 46153778370 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 17481507840 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 15586959435 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 113172096165 # Total energy per rank (pJ) -system.physmem_0.averagePower 479.494648 # Core power per rank (mW) -system.physmem_0.totalIdleTime 204913310074 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 902504711 # Time in different power states -system.physmem_0.memoryStateTime::REF 6666906000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 58174043250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 45524259021 # Time in different power states -system.physmem_0.memoryStateTime::ACT 23540851965 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 101215123053 # Time in different power states -system.physmem_1.actEnergy 1151060820 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 611788155 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1482064080 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 761650200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15007050240.000004 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13420176330 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 597461760 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 42655727700 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 16961144160 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 17790500985 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 110444200560 # Total energy per rank (pJ) -system.physmem_1.averagePower 467.936931 # Core power per rank (mW) -system.physmem_1.totalIdleTime 205025277615 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 898721445 # Time in different power states -system.physmem_1.memoryStateTime::REF 6366412000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 67312288506 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 44168958563 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23733276940 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 93544030546 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 174594111 # Number of BP lookups -system.cpu.branchPred.condPredicted 131059017 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7233933 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90232346 # Number of BTB lookups -system.cpu.branchPred.BTBHits 78999638 # Number of BTB hits +system.physmem.avgWrQLen 21.62 # Average write queue length when enqueuing +system.physmem.readRowHits 308139 # Number of row buffer hits during reads +system.physmem.writeRowHits 82177 # Number of row buffer hits during writes +system.physmem.readRowHitRate 71.98 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 28.20 # Row buffer hit rate for writes +system.physmem.avgGap 326630.04 # Average gap between requests +system.physmem.pageHitRate 54.25 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1195207440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 635245050 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1570792860 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 757087920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15735398640.000004 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 13510945980 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 615046560 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 46117601610 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 17430135360 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 15587831640 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 113161874670 # Total energy per rank (pJ) +system.physmem_0.averagePower 479.804155 # Core power per rank (mW) +system.physmem_0.totalIdleTime 204603400415 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 912794276 # Time in different power states +system.physmem_0.memoryStateTime::REF 6674692000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 58078463500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 45390268663 # Time in different power states +system.physmem_0.memoryStateTime::ACT 23659127059 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 101134783502 # Time in different power states +system.physmem_1.actEnergy 1155130620 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 613955100 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1485605520 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 764166240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15039011520.000004 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13474802850 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 604322400 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 42537889890 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 17081497440 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 17718944700 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 110481339780 # Total energy per rank (pJ) +system.physmem_1.averagePower 468.438739 # Core power per rank (mW) +system.physmem_1.totalIdleTime 204713337667 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 914400899 # Time in different power states +system.physmem_1.memoryStateTime::REF 6380142000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 66945121250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 44482448304 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23842248434 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 93285768113 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 174426540 # Number of BP lookups +system.cpu.branchPred.condPredicted 130958868 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7258964 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 89936054 # Number of BTB lookups +system.cpu.branchPred.BTBHits 78903188 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.551351 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12106114 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104453 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 4688512 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 4673325 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 15187 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 53879 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 87.732544 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12071651 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104612 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 4685817 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 4672093 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 13724 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 53795 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -348,7 +344,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -378,7 +374,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -408,7 +404,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -439,134 +435,134 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 472047377 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 471700259 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7665841 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 727531021 # Number of instructions fetch has processed -system.cpu.fetch.Branches 174594111 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95779077 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 455980909 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14521279 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 6370 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 74 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 14846 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 235277273 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 36996 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 470928679 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.672614 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.189870 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7689412 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 726848478 # Number of instructions fetch has processed +system.cpu.fetch.Branches 174426540 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95646932 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 455559849 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14571167 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 7088 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 169 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 15067 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 235109896 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 36736 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 470557168 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.672087 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.189865 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 101212688 21.49% 21.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132055507 28.04% 49.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57355152 12.18% 61.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 180305332 38.29% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 101222144 21.51% 21.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 131885544 28.03% 49.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57421464 12.20% 61.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 180028016 38.26% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 470928679 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.369866 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.541225 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32549304 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 125870927 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 282926168 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22809881 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6772399 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 23857268 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 495900 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 710989368 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29087460 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6772399 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63357486 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 61253040 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40466365 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 273530421 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 25548968 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 682720764 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 12849971 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 10025216 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2519363 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1823930 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 2318589 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 827514324 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3000521547 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 718647704 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 470557168 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.369783 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.540912 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32637512 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 125886415 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 282414401 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22855437 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6763403 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 71909343 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 530427 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 710086582 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29127059 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6763403 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63488458 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 61155779 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40463668 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 273022741 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 25663119 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 681926435 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 12775010 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 10060236 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2531231 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1813266 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 2373970 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 826391408 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2997146717 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 717894841 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654095674 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 173418650 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1545803 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1536177 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 43812625 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 142363196 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67528532 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12884136 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11268568 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 664776091 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2979332 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608934070 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5749195 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 120407268 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 306545068 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1700 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 470928679 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.293049 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.104484 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 172295734 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1545774 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1536126 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 43961162 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 142203026 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67513624 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12913434 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11193544 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 664083030 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2979301 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608560988 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5743597 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 119714176 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 304959820 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1669 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 470557168 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.293277 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.104886 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 154505965 32.81% 32.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 100895056 21.42% 54.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 145511490 30.90% 85.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63049261 13.39% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6966284 1.48% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 623 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 154355830 32.80% 32.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 100909501 21.44% 54.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145256303 30.87% 85.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63003898 13.39% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 7030993 1.49% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 643 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 470928679 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 470557168 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71893204 53.11% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44308845 32.73% 85.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19163928 14.16% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 14 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71776446 52.99% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44249945 32.67% 85.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19436717 14.35% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 9 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 22 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 412595854 67.76% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 352107 0.06% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 412327933 67.75% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 351836 0.06% 67.81% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.81% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued @@ -596,84 +592,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 133581364 21.94% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62404700 10.25% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 26 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 133457436 21.93% 89.74% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62423748 10.26% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 16 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 16 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608934070 # Type of FU issued -system.cpu.iq.rate 1.289985 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135366043 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.222300 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1829911935 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 788191546 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594211471 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 122 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 100 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 608560988 # Type of FU issued +system.cpu.iq.rate 1.290143 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135463169 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222596 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1828885813 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 786805257 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 593918713 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 97 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 70 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 744300035 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 78 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7286788 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 744024094 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 63 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 7272380 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 26479913 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24891 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29414 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10668312 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 26319743 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24134 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29234 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10653404 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 225406 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 23080 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 224604 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 23301 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6772399 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 23806628 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 967662 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 669248404 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6763403 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 23756716 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 981361 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 668554311 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 142363196 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67528532 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1490790 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 256473 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 573815 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29414 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3591193 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3742987 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7334180 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 598436406 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129089013 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10497664 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 142203026 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67513624 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1490759 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 256987 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 586437 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29234 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3560929 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3767464 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7328393 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 598121332 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 128978812 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10439656 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1492981 # number of nop insts executed -system.cpu.iew.exec_refs 190011710 # number of memory reference insts executed -system.cpu.iew.exec_branches 131264327 # Number of branches executed -system.cpu.iew.exec_stores 60922697 # Number of stores executed -system.cpu.iew.exec_rate 1.267746 # Inst execution rate -system.cpu.iew.wb_sent 595457934 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594211487 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349573647 # num instructions producing a value -system.cpu.iew.wb_consumers 571370339 # num instructions consuming a value -system.cpu.iew.wb_rate 1.258796 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611816 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 107140247 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1491980 # number of nop insts executed +system.cpu.iew.exec_refs 189925083 # number of memory reference insts executed +system.cpu.iew.exec_branches 131214447 # Number of branches executed +system.cpu.iew.exec_stores 60946271 # Number of stores executed +system.cpu.iew.exec_rate 1.268011 # Inst execution rate +system.cpu.iew.wb_sent 595160432 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 593918729 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349300209 # num instructions producing a value +system.cpu.iew.wb_consumers 571006140 # num instructions consuming a value +system.cpu.iew.wb_rate 1.259102 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611728 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 106531473 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6745693 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 454265599 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.207866 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.884244 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6736784 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 453954004 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.208695 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.885174 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 225450125 49.63% 49.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116407668 25.63% 75.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43488632 9.57% 84.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23202465 5.11% 89.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11495162 2.53% 92.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7755603 1.71% 94.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8270201 1.82% 95.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4246101 0.93% 96.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13949642 3.07% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 225266208 49.62% 49.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116316093 25.62% 75.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43463338 9.57% 84.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23021553 5.07% 89.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11663985 2.57% 92.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7751412 1.71% 94.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8276330 1.82% 95.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4247049 0.94% 96.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13948036 3.07% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 454265599 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 453954004 # Number of insts commited each cycle system.cpu.commit.committedInsts 506578818 # Number of instructions committed system.cpu.commit.committedOps 548692039 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -723,560 +719,558 @@ system.cpu.commit.op_class_0::FloatMemWrite 16 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548692039 # Class of committed instruction -system.cpu.commit.bw_lim_events 13949642 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1096141105 # The number of ROB reads -system.cpu.rob.rob_writes 1328357052 # The number of ROB writes -system.cpu.timesIdled 14656 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1118698 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 13948036 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1095222342 # The number of ROB reads +system.cpu.rob.rob_writes 1327086117 # The number of ROB writes +system.cpu.timesIdled 14782 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1143091 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505234934 # Number of Instructions Simulated system.cpu.committedOps 547348155 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.934313 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.934313 # CPI: Total CPI of All Threads -system.cpu.ipc 1.070306 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.070306 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 610147261 # number of integer regfile reads -system.cpu.int_regfile_writes 327343686 # number of integer regfile writes +system.cpu.cpi 0.933626 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.933626 # CPI: Total CPI of All Threads +system.cpu.ipc 1.071093 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.071093 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 609897818 # number of integer regfile reads +system.cpu.int_regfile_writes 327085541 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2166295309 # number of cc regfile reads -system.cpu.cc_regfile_writes 376541599 # number of cc regfile writes -system.cpu.misc_regfile_reads 217608578 # number of misc regfile reads +system.cpu.cc_regfile_reads 2165040622 # number of cc regfile reads +system.cpu.cc_regfile_writes 376344417 # number of cc regfile writes +system.cpu.misc_regfile_reads 217537377 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2817163 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.628180 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168869146 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2817675 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 59.932088 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 504794000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.628180 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999274 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999274 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2817480 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.627959 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168773991 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2817992 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 59.891579 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 504701000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.627959 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999273 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999273 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 355269881 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 355269881 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 114167630 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114167630 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51721570 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51721570 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2787 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2787 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488559 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488559 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 355076080 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 355076080 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 114071383 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114071383 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51722665 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51722665 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2778 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2778 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488556 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488556 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 165889200 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 165889200 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 165891987 # number of overall hits -system.cpu.dcache.overall_hits::total 165891987 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4839460 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4839460 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2517479 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2517479 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7356939 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7356939 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7356950 # number of overall misses -system.cpu.dcache.overall_misses::total 7356950 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63959252000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63959252000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19900951428 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19900951428 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1024000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1024000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83860203428 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83860203428 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83860203428 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83860203428 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119007090 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119007090 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 165794048 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 165794048 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 165796826 # number of overall hits +system.cpu.dcache.overall_hits::total 165796826 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4838662 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4838662 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2516384 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2516384 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 10 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 10 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 65 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 65 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 7355046 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7355046 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7355056 # number of overall misses +system.cpu.dcache.overall_misses::total 7355056 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 63735397500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 63735397500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19938555937 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19938555937 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 846000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 846000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83673953437 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83673953437 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83673953437 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83673953437 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 118910045 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 118910045 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2798 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2798 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2788 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2788 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488621 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488621 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173246139 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173246139 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173248937 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173248937 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040665 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040665 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046415 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046415 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003931 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.003931 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 173149094 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173149094 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173151882 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173151882 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040692 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040692 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046394 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046394 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003587 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.003587 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.042465 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.042465 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.042465 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.042465 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13216.196022 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13216.196022 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7905.111196 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7905.111196 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15515.151515 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15515.151515 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11398.790098 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11398.790098 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11398.773055 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11398.773055 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1096029 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.042478 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042478 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042477 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042477 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13172.111939 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13172.111939 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7923.494958 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7923.494958 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13015.384615 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13015.384615 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11376.401104 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11376.401104 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11376.385637 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11376.385637 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 14 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1100252 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 221098 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 4.957209 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2817163 # number of writebacks -system.cpu.dcache.writebacks::total 2817163 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2541567 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2541567 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1997678 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1997678 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4539245 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4539245 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4539245 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4539245 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2297893 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2297893 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519801 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519801 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2817694 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2817694 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2817704 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2817704 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32776399000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32776399000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4786328496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4786328496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1261500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1261500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37562727496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 37562727496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37563988996 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 37563988996 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019309 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019309 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009584 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009584 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003574 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003574 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016264 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016264 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14263.675028 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14263.675028 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9208.001708 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9208.001708 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 126150 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 126150 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13331.017313 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13331.017313 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13331.417706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13331.417706 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 76621 # number of replacements -system.cpu.icache.tags.tagsinuse 466.068009 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 235191085 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 77133 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3049.162939 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 116620130500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 466.068009 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.910289 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.910289 # Average percentage of cache occupancy +system.cpu.dcache.blocked::no_targets 221126 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4.975679 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2817480 # number of writebacks +system.cpu.dcache.writebacks::total 2817480 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2540507 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2540507 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1996523 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1996523 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 65 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 65 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 4537030 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4537030 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4537030 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4537030 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2298155 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2298155 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519861 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519861 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 9 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 9 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2818016 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2818016 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2818025 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2818025 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32727255000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32727255000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4791332496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4791332496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1174000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1174000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37518587496 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 37518587496 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37519761496 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 37519761496 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019327 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019327 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009585 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009585 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003228 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003228 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016275 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016275 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016275 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016275 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14240.664794 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14240.664794 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9216.564612 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9216.564612 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 130444.444444 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 130444.444444 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13313.830545 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13313.830545 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13314.204628 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13314.204628 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 76537 # number of replacements +system.cpu.icache.tags.tagsinuse 465.899675 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 235023805 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 77049 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3050.316098 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 116553680500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 465.899675 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.909960 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.909960 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 118 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 263 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 14 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 470631453 # Number of tag accesses -system.cpu.icache.tags.data_accesses 470631453 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 235191085 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 235191085 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 235191085 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 235191085 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 235191085 # number of overall hits -system.cpu.icache.overall_hits::total 235191085 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 86061 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 86061 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 86061 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 86061 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 86061 # number of overall misses -system.cpu.icache.overall_misses::total 86061 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1945774184 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1945774184 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1945774184 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1945774184 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1945774184 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1945774184 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 235277146 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 235277146 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 235277146 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 235277146 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 235277146 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 235277146 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 470296624 # Number of tag accesses +system.cpu.icache.tags.data_accesses 470296624 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 235023805 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 235023805 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 235023805 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 235023805 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 235023805 # number of overall hits +system.cpu.icache.overall_hits::total 235023805 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 85967 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 85967 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 85967 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 85967 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 85967 # number of overall misses +system.cpu.icache.overall_misses::total 85967 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1954653197 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1954653197 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1954653197 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1954653197 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1954653197 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1954653197 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 235109772 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 235109772 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 235109772 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 235109772 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 235109772 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 235109772 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000366 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000366 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000366 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000366 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000366 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000366 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22609.244420 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22609.244420 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22609.244420 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22609.244420 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22609.244420 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22609.244420 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 200857 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 1531 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 7099 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22737.250305 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22737.250305 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22737.250305 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22737.250305 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22737.250305 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22737.250305 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 201943 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 336 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 7203 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.293703 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 191.375000 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 76621 # number of writebacks -system.cpu.icache.writebacks::total 76621 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8898 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 8898 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 8898 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 8898 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 8898 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 8898 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77163 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 77163 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 77163 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 77163 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 77163 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 77163 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1533201777 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1533201777 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1533201777 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1533201777 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1533201777 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1533201777 # number of overall MSHR miss cycles +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.035957 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 42 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 76537 # number of writebacks +system.cpu.icache.writebacks::total 76537 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8885 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 8885 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 8885 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 8885 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 8885 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 8885 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77082 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 77082 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 77082 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 77082 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 77082 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 77082 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1551815800 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1551815800 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1551815800 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1551815800 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1551815800 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1551815800 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000328 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000328 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000328 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19869.649664 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19869.649664 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19869.649664 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19869.649664 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19869.649664 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19869.649664 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 8513489 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 8514918 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 429 # number of redundant prefetches already in prefetch queue +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20132.012662 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20132.012662 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20132.012662 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20132.012662 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20132.012662 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20132.012662 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 8513754 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 8515198 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 454 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 744218 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 389920 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15006.987953 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2697445 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 405523 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.651768 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 744250 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 390446 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15006.522104 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2698185 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 406039 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.645138 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14934.817227 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 72.170726 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.911549 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004405 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.915954 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 103 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15500 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 15 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 49 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 35 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 249 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 665 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5454 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6553 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2579 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.006287 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946045 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 95362177 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 95362177 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2356317 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2356317 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 513605 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 513605 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 516771 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 516771 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 67113 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 67113 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2130678 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 2130678 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 67113 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2647449 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2714562 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 67113 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2647449 # number of overall hits -system.cpu.l2cache.overall_hits::total 2714562 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 29 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 29 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 5213 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 5213 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10017 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 10017 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 165013 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 165013 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 10017 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 170226 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 180243 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 10017 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 170226 # number of overall misses -system.cpu.l2cache.overall_misses::total 180243 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 21500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 21500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 669742000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 669742000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1015207000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1015207000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 15371129000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 15371129000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1015207000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 16040871000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 17056078000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1015207000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 16040871000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 17056078000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2356317 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2356317 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 513605 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 513605 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 29 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 29 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 521984 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 521984 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 77130 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 77130 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2295691 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 2295691 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 77130 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2817675 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2894805 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 77130 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2817675 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2894805 # number of overall (read+write) accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 14933.160754 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 73.361350 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.911448 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004478 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.915925 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 107 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15486 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 5 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 51 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 51 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 675 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5453 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6496 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2623 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.006531 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.945190 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 95374967 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 95374967 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 2350430 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2350430 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 520007 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 520007 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 516734 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 516734 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 66859 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 66859 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2131098 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 2131098 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 66859 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2647832 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2714691 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 66859 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2647832 # number of overall hits +system.cpu.l2cache.overall_hits::total 2714691 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 33 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 33 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 5281 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 5281 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10187 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 10187 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 164879 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 164879 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 10187 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 170160 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 180347 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 10187 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 170160 # number of overall misses +system.cpu.l2cache.overall_misses::total 180347 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 87000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 87000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 674041000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 674041000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1035576000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1035576000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 15320195500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 15320195500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1035576000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15994236500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 17029812500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1035576000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15994236500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17029812500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2350430 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2350430 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 520007 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 520007 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 33 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 33 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 522015 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 522015 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 77046 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 77046 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2295977 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 2295977 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 77046 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2817992 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2895038 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 77046 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2817992 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2895038 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009987 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.009987 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.129872 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.129872 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.071879 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.071879 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.129872 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.060414 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.062264 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.129872 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.060414 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.062264 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 741.379310 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 741.379310 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 128475.350086 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 128475.350086 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 101348.407707 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 101348.407707 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93151.018405 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93151.018405 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 101348.407707 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94232.790526 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 94628.240764 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 101348.407707 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94232.790526 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 94628.240764 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.010117 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.010117 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.132220 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.132220 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.071812 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.071812 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.132220 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.060383 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.062295 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.132220 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.060383 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.062295 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2636.363636 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2636.363636 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127635.106987 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127635.106987 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 101656.621184 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 101656.621184 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92917.809424 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92917.809424 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 101656.621184 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93995.277974 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 94428.033180 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 101656.621184 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93995.277974 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 94428.033180 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 349 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 349 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 2009 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 291097 # number of writebacks -system.cpu.l2cache.writebacks::total 291097 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1528 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 1528 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 4 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4483 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4483 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 6011 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 6015 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 6011 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 6015 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 355832 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 355832 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 29 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 29 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3685 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3685 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10013 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10013 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 160530 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 160530 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10013 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 164215 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 174228 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10013 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 164215 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 355832 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 530060 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 21330424894 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 21330424894 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 451500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 451500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 469308000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 469308000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 954360500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 954360500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 13996060500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 13996060500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 954360500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14465368500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15419729000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 954360500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14465368500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 21330424894 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 36750153894 # number of overall MSHR miss cycles +system.cpu.l2cache.unused_prefetches 1991 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 291460 # number of writebacks +system.cpu.l2cache.writebacks::total 291460 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1597 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1597 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 11 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4534 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4534 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 6131 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 6142 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 6131 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 6142 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 356126 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 356126 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 33 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3684 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3684 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10176 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10176 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 160345 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 160345 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10176 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 164029 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 174205 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10176 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 164029 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 356126 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 530331 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 21400232213 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 21400232213 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 517000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 517000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 462922500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 462922500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 973097500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 973097500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 13944331500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 13944331500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 973097500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14407254000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15380351500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 973097500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14407254000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 21400232213 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 36780583713 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007060 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007060 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.129820 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.129820 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069927 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069927 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.129820 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058280 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060186 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.129820 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058280 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007057 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007057 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.132077 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.132077 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069837 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069837 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.132077 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058208 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060174 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.132077 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058208 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.183107 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59945.212612 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 59945.212612 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15568.965517 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15568.965517 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 127356.309362 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 127356.309362 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 95312.144213 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 95312.144213 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87186.572603 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87186.572603 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 95312.144213 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88087.985263 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88503.162523 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 95312.144213 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88087.985263 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59945.212612 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69332.064095 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5788651 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893810 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 26608 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 99788 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99240 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 548 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2372852 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2647414 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 537467 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 98823 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 402669 # Transaction distribution +system.cpu.l2cache.overall_mshr_miss_rate::total 0.183186 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60091.743408 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 60091.743408 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15666.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15666.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 125657.573290 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 125657.573290 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 95626.719733 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 95626.719733 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 86964.554554 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 86964.554554 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 95626.719733 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87833.578209 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88288.806291 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 95626.719733 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87833.578209 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60091.743408 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69354.014216 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5789124 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894045 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 26043 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 99823 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99226 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 597 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 2373057 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2641890 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 543587 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 98986 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 403295 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 29 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 29 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 521984 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 521984 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 77163 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295691 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230912 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8452572 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8683484 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9839936 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360629696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 370469632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 792623 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18632384 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3687456 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.034433 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.183151 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 33 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 33 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 522015 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 522015 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 77082 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295977 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230663 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8453531 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8684194 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9829184 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360670272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 370499456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 793778 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 18655808 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 3688848 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.034290 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.182859 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3561035 96.57% 96.57% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 125873 3.41% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 548 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3562956 96.59% 96.59% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 125295 3.40% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 597 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3687456 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5788109505 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3688848 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5788579005 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 115773436 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 115655928 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4226542968 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4227026456 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 820344 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 413808 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 821093 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 414041 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 426709 # Transaction distribution -system.membus.trans_dist::WritebackDirty 291097 # Transaction distribution -system.membus.trans_dist::CleanEvict 98823 # Transaction distribution -system.membus.trans_dist::UpgradeReq 32 # Transaction distribution -system.membus.trans_dist::ReadExReq 3682 # Transaction distribution -system.membus.trans_dist::ReadExResp 3682 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 426710 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1250735 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1250735 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46175232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 46175232 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 426929 # Transaction distribution +system.membus.trans_dist::WritebackDirty 291460 # Transaction distribution +system.membus.trans_dist::CleanEvict 98986 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36 # Transaction distribution +system.membus.trans_dist::ReadExReq 3681 # Transaction distribution +system.membus.trans_dist::ReadExResp 3681 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 426930 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1251703 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1251703 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46212480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 46212480 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 430424 # Request fanout histogram +system.membus.snoop_fanout::samples 430647 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 430424 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 430647 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 430424 # Request fanout histogram -system.membus.reqLayer0.occupancy 2210945378 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 430647 # Request fanout histogram +system.membus.reqLayer0.occupancy 2213026745 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2277916539 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2279181090 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 1d6cdc3c5..eaf30dab2 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.487172 # Number of seconds simulated -sim_ticks 487172057000 # Number of ticks simulated -final_tick 487172057000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.487051 # Number of seconds simulated +sim_ticks 487050729500 # Number of ticks simulated +final_tick 487050729500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 151495 # Simulator instruction rate (inst/s) -host_op_rate 280342 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 89259825 # Simulator tick rate (ticks/s) -host_mem_usage 322228 # Number of bytes of host memory used -host_seconds 5457.91 # Real time elapsed on the host +host_inst_rate 151835 # Simulator instruction rate (inst/s) +host_op_rate 280970 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 89437473 # Simulator tick rate (ticks/s) +host_mem_usage 318556 # Number of bytes of host memory used +host_seconds 5445.71 # Real time elapsed on the host sim_insts 826847303 # Number of instructions simulated sim_ops 1530082520 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 155008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24650432 # Number of bytes read from this memory -system.physmem.bytes_read::total 24805440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 155008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 155008 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18909504 # Number of bytes written to this memory -system.physmem.bytes_written::total 18909504 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2422 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 385163 # Number of read requests responded to by this memory -system.physmem.num_reads::total 387585 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 295461 # Number of write requests responded to by this memory -system.physmem.num_writes::total 295461 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 318179 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 50599027 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50917206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 318179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 318179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 38814837 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 38814837 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 38814837 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 318179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 50599027 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 89732043 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 387585 # Number of read requests accepted -system.physmem.writeReqs 295461 # Number of write requests accepted -system.physmem.readBursts 387585 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 295461 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24785280 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20160 # Total number of bytes read from write queue -system.physmem.bytesWritten 18907584 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24805440 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18909504 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 315 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 156352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24658560 # Number of bytes read from this memory +system.physmem.bytes_read::total 24814912 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 156352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 156352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18911424 # Number of bytes written to this memory +system.physmem.bytes_written::total 18911424 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2443 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 385290 # Number of read requests responded to by this memory +system.physmem.num_reads::total 387733 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 295491 # Number of write requests responded to by this memory +system.physmem.num_writes::total 295491 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 321018 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 50628320 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50949338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 321018 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 321018 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 38828448 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 38828448 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 38828448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 321018 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 50628320 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 89777786 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 387733 # Number of read requests accepted +system.physmem.writeReqs 295491 # Number of write requests accepted +system.physmem.readBursts 387733 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 295491 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24795072 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19840 # Total number of bytes read from write queue +system.physmem.bytesWritten 18909504 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24814912 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18911424 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 310 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24645 # Per bank write bursts -system.physmem.perBankRdBursts::1 26417 # Per bank write bursts -system.physmem.perBankRdBursts::2 24674 # Per bank write bursts -system.physmem.perBankRdBursts::3 24501 # Per bank write bursts -system.physmem.perBankRdBursts::4 23296 # Per bank write bursts -system.physmem.perBankRdBursts::5 23619 # Per bank write bursts -system.physmem.perBankRdBursts::6 24746 # Per bank write bursts -system.physmem.perBankRdBursts::7 24503 # Per bank write bursts -system.physmem.perBankRdBursts::8 23866 # Per bank write bursts -system.physmem.perBankRdBursts::9 23595 # Per bank write bursts -system.physmem.perBankRdBursts::10 24803 # Per bank write bursts -system.physmem.perBankRdBursts::11 23982 # Per bank write bursts -system.physmem.perBankRdBursts::12 23298 # Per bank write bursts -system.physmem.perBankRdBursts::13 23005 # Per bank write bursts -system.physmem.perBankRdBursts::14 24008 # Per bank write bursts -system.physmem.perBankRdBursts::15 24312 # Per bank write bursts -system.physmem.perBankWrBursts::0 19007 # Per bank write bursts -system.physmem.perBankWrBursts::1 19956 # Per bank write bursts -system.physmem.perBankWrBursts::2 19034 # Per bank write bursts -system.physmem.perBankWrBursts::3 18984 # Per bank write bursts -system.physmem.perBankWrBursts::4 18157 # Per bank write bursts -system.physmem.perBankWrBursts::5 18431 # Per bank write bursts -system.physmem.perBankWrBursts::6 19162 # Per bank write bursts -system.physmem.perBankWrBursts::7 19114 # Per bank write bursts -system.physmem.perBankWrBursts::8 18737 # Per bank write bursts -system.physmem.perBankWrBursts::9 17973 # Per bank write bursts -system.physmem.perBankWrBursts::10 18902 # Per bank write bursts -system.physmem.perBankWrBursts::11 17777 # Per bank write bursts -system.physmem.perBankWrBursts::12 17406 # Per bank write bursts -system.physmem.perBankWrBursts::13 16997 # Per bank write bursts -system.physmem.perBankWrBursts::14 17829 # Per bank write bursts +system.physmem.perBankRdBursts::0 24612 # Per bank write bursts +system.physmem.perBankRdBursts::1 26389 # Per bank write bursts +system.physmem.perBankRdBursts::2 24828 # Per bank write bursts +system.physmem.perBankRdBursts::3 24571 # Per bank write bursts +system.physmem.perBankRdBursts::4 23534 # Per bank write bursts +system.physmem.perBankRdBursts::5 23661 # Per bank write bursts +system.physmem.perBankRdBursts::6 24754 # Per bank write bursts +system.physmem.perBankRdBursts::7 24509 # Per bank write bursts +system.physmem.perBankRdBursts::8 23888 # Per bank write bursts +system.physmem.perBankRdBursts::9 23557 # Per bank write bursts +system.physmem.perBankRdBursts::10 24834 # Per bank write bursts +system.physmem.perBankRdBursts::11 24002 # Per bank write bursts +system.physmem.perBankRdBursts::12 23243 # Per bank write bursts +system.physmem.perBankRdBursts::13 22894 # Per bank write bursts +system.physmem.perBankRdBursts::14 23905 # Per bank write bursts +system.physmem.perBankRdBursts::15 24242 # Per bank write bursts +system.physmem.perBankWrBursts::0 18972 # Per bank write bursts +system.physmem.perBankWrBursts::1 19954 # Per bank write bursts +system.physmem.perBankWrBursts::2 19038 # Per bank write bursts +system.physmem.perBankWrBursts::3 19006 # Per bank write bursts +system.physmem.perBankWrBursts::4 18208 # Per bank write bursts +system.physmem.perBankWrBursts::5 18444 # Per bank write bursts +system.physmem.perBankWrBursts::6 19174 # Per bank write bursts +system.physmem.perBankWrBursts::7 19116 # Per bank write bursts +system.physmem.perBankWrBursts::8 18744 # Per bank write bursts +system.physmem.perBankWrBursts::9 17955 # Per bank write bursts +system.physmem.perBankWrBursts::10 18923 # Per bank write bursts +system.physmem.perBankWrBursts::11 17774 # Per bank write bursts +system.physmem.perBankWrBursts::12 17399 # Per bank write bursts +system.physmem.perBankWrBursts::13 16985 # Per bank write bursts +system.physmem.perBankWrBursts::14 17804 # Per bank write bursts system.physmem.perBankWrBursts::15 17965 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 487171969500 # Total gap between requests +system.physmem.totGap 487050613500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 387585 # Read request sizes (log2) +system.physmem.readPktSize::6 387733 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 295461 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 5721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 295491 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381263 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 5754 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 361 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -145,27 +145,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17686 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 17693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -194,360 +194,362 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 146660 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 297.911141 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 176.290070 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.324639 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 53183 36.26% 36.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40977 27.94% 64.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13739 9.37% 73.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7432 5.07% 78.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5223 3.56% 82.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3827 2.61% 84.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2941 2.01% 86.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2699 1.84% 88.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16639 11.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 146660 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17684 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.898835 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 18.149529 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 215.763207 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17677 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 3 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 146416 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 298.484100 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 176.719176 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.748192 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 52816 36.07% 36.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 41066 28.05% 64.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13865 9.47% 73.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7498 5.12% 78.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4985 3.40% 82.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3806 2.60% 84.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2894 1.98% 86.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2818 1.92% 88.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16668 11.38% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 146416 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17678 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.914866 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 18.161180 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 216.039339 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17672 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17684 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17684 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.706119 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.679236 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.959383 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 11362 64.25% 64.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 284 1.61% 65.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5921 33.48% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 108 0.61% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 8 0.05% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17684 # Writes before turning the bus around for reads -system.physmem.totQLat 9753002000 # Total ticks spent queuing -system.physmem.totMemAccLat 17014314500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1936350000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25183.99 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17678 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17678 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.713486 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.686282 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.965426 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 11315 64.01% 64.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 269 1.52% 65.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5957 33.70% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 123 0.70% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 10 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 3 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17678 # Writes before turning the bus around for reads +system.physmem.totQLat 9794922250 # Total ticks spent queuing +system.physmem.totMemAccLat 17059103500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1937115000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25282.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43933.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 50.88 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 38.81 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.92 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 38.81 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44032.24 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 50.91 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 38.82 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.95 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 38.83 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.70 # Data bus utilization in percentage system.physmem.busUtilRead 0.40 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.30 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.76 # Average write queue length when enqueuing -system.physmem.readRowHits 316112 # Number of row buffer hits during reads -system.physmem.writeRowHits 219918 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.43 # Row buffer hit rate for writes -system.physmem.avgGap 713234.50 # Average gap between requests -system.physmem.pageHitRate 78.51 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 536813760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 285300510 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1402303140 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 792630900 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 13522080000.000004 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 8880806910 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 733930560 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 36188602890 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 17013808320 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 84109110615 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 163471886265 # Total energy per rank (pJ) -system.physmem_0.averagePower 335.552673 # Core power per rank (mW) -system.physmem_0.totalIdleTime 465770843500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 1167963000 # Time in different power states -system.physmem_0.memoryStateTime::REF 5742590000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 342103131000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 44306910500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 14490068000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 79361394500 # Time in different power states -system.physmem_1.actEnergy 510417180 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 271274190 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1362804660 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 749518920 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 13134242160.000004 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 8898960840 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 723582720 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 34400258100 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 16618152960 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 85296284295 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 161971426545 # Total energy per rank (pJ) -system.physmem_1.averagePower 332.472734 # Core power per rank (mW) -system.physmem_1.totalIdleTime 465759347500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 1160536750 # Time in different power states -system.physmem_1.memoryStateTime::REF 5578620000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 347043695250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 43276363250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14673424500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 75439417250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 297986094 # Number of BP lookups -system.cpu.branchPred.condPredicted 297986094 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 23626998 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 229902551 # Number of BTB lookups +system.physmem.avgWrQLen 20.96 # Average write queue length when enqueuing +system.physmem.readRowHits 316322 # Number of row buffer hits during reads +system.physmem.writeRowHits 220133 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.65 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.50 # Row buffer hit rate for writes +system.physmem.avgGap 712871.05 # Average gap between requests +system.physmem.pageHitRate 78.55 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 538191780 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 286032945 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1405566120 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 792980640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 13571251200.000004 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 8851881120 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 742850400 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 36305173020 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 16998972000 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 84070895340 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 163568832135 # Total energy per rank (pJ) +system.physmem_0.averagePower 335.835307 # Core power per rank (mW) +system.physmem_0.totalIdleTime 465691902250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 1184996500 # Time in different power states +system.physmem_0.memoryStateTime::REF 5763492000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 341808238000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 44268234250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14409717250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 79616051500 # Time in different power states +system.physmem_1.actEnergy 507311280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 269615775 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1360634100 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 749325780 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 13094905200.000004 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 8819547870 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 717418080 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 34208424030 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 16648938720 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 85396744800 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 161777173725 # Total energy per rank (pJ) +system.physmem_1.averagePower 332.156722 # Core power per rank (mW) +system.physmem_1.totalIdleTime 465831856000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 1145526000 # Time in different power states +system.physmem_1.memoryStateTime::REF 5561926000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 347456670000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 43356567250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14511269750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 75018770500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 299198029 # Number of BP lookups +system.cpu.branchPred.condPredicted 299198029 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 24258277 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 226066805 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 40347150 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4410395 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 229902551 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 119869207 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 110033344 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 11602477 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 40193400 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4437789 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 226066805 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 118144411 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 107922394 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 11883156 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 974344115 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 487050729500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 974101460 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 229691872 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1587782946 # Number of instructions fetch has processed -system.cpu.fetch.Branches 297986094 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 160216357 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 719926348 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 48165553 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1415 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 32240 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 400644 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 8846 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 32 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 216441049 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6311436 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 974144173 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.051993 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.490984 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 230169557 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1594277830 # Number of instructions fetch has processed +system.cpu.fetch.Branches 299198029 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 158337811 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 718471067 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 49469999 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 2698 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 34945 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 480096 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 4714 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 69 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 216546560 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6526632 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 8 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 973898145 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.063667 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.497102 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 482346160 49.51% 49.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 36602331 3.76% 53.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 36258722 3.72% 56.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33122325 3.40% 60.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28552285 2.93% 63.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 29954375 3.07% 66.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40147511 4.12% 70.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 37554957 3.86% 74.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 249605507 25.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 481357803 49.43% 49.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 36544666 3.75% 53.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 36285723 3.73% 56.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 32866211 3.37% 60.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28367371 2.91% 63.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 29577354 3.04% 66.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 39843150 4.09% 70.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 36876934 3.79% 74.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 252178933 25.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 974144173 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.305832 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.629592 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 165741449 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 390914156 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 312062305 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 81343487 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 24082776 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2744526803 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 24082776 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 201646050 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 200648481 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15573 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 351553209 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 196198084 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2627040726 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 843366 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 120856771 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 22890286 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 43959941 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2707701926 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6592856104 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4207544155 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2527327 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 973898145 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.307153 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.636665 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 166490369 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 388298779 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 313723542 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 80650456 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 24734999 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2751923456 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 24734999 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 202899221 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 199700520 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14210 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 351959746 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 194589449 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2631585273 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 503822 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 119585114 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 21729790 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 44646970 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2710512651 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6600728549 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4213051781 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1976674 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1616961572 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1090740354 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1231 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1132 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 368340883 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 608352131 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 244132697 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 253219333 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 76661135 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2419790234 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 118502 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1999387601 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3615961 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 889826216 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1510217601 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 117950 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 974144173 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.052456 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.105356 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1093551079 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 884 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 794 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 367177164 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 608809294 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 243550763 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 252688912 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 75518257 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2418516015 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 104540 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1999668107 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3656750 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 888538035 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1505526254 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 103988 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 973898145 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.053262 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.107501 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 345565196 35.47% 35.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 135254480 13.88% 49.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 130135429 13.36% 62.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 118774957 12.19% 74.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 97965180 10.06% 84.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 67350848 6.91% 91.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 45621638 4.68% 96.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 22618956 2.32% 98.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10857489 1.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 345655298 35.49% 35.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 135232191 13.89% 49.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 129689064 13.32% 62.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119012847 12.22% 74.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 97852872 10.05% 84.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 66913699 6.87% 91.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 45825912 4.71% 96.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 22646304 2.33% 98.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11069958 1.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 974144173 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 973898145 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11247867 43.19% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11962828 45.93% 89.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2737897 10.51% 99.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 96082 0.37% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11137608 43.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11929198 46.06% 89.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2740827 10.58% 99.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 92541 0.36% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2913186 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1333691578 66.71% 66.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 358355 0.02% 66.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 4798525 0.24% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 471253849 23.57% 90.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 185928557 9.30% 99.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 5 0.00% 99.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 443541 0.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2900375 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1333719780 66.70% 66.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 357536 0.02% 66.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 4798411 0.24% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 4 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 471767183 23.59% 90.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 185670018 9.29% 99.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 6 0.00% 99.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 454793 0.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1999387601 # Type of FU issued -system.cpu.iq.rate 2.052034 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26044674 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013026 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5001332322 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3306265401 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1924007332 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1247688 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4044576 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 235696 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2021979456 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 539633 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 179731986 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1999668107 # Type of FU issued +system.cpu.iq.rate 2.052833 # Inst issue rate +system.cpu.iq.fu_busy_cnt 25900174 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012952 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5001578236 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3304560217 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1922724831 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1213047 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 3212370 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 280288 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2022120560 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 547346 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 180407023 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 224269113 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 336817 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 641986 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94974502 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 224726218 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 356451 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 693943 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94392568 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 32014 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 878 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 33314 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 814 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 24082776 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 149888848 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6862033 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2419908736 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1314714 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 608352426 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 244132697 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 41176 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1469227 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4543982 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 641986 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8726699 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 20674839 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 29401538 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1945912356 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 456814163 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 53475245 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 24734999 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 149663879 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6607902 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2418620555 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1417513 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 608809531 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 243550763 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 36150 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1478128 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4302509 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 693943 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8551096 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 21778410 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 30329506 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1944942401 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 457167604 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 54725706 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 635656680 # number of memory reference insts executed -system.cpu.iew.exec_branches 185192217 # Number of branches executed -system.cpu.iew.exec_stores 178842517 # Number of stores executed -system.cpu.iew.exec_rate 1.997151 # Inst execution rate -system.cpu.iew.wb_sent 1934768958 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1924243028 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1457137045 # num instructions producing a value -system.cpu.iew.wb_consumers 2204058928 # num instructions consuming a value -system.cpu.iew.wb_rate 1.974911 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.661115 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 889901292 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 635670117 # number of memory reference insts executed +system.cpu.iew.exec_branches 185387955 # Number of branches executed +system.cpu.iew.exec_stores 178502513 # Number of stores executed +system.cpu.iew.exec_rate 1.996653 # Inst execution rate +system.cpu.iew.wb_sent 1933639401 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1923005119 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1456045504 # num instructions producing a value +system.cpu.iew.wb_consumers 2200626785 # num instructions consuming a value +system.cpu.iew.wb_rate 1.974132 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.661650 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 888612801 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 23658010 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 841376599 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.818547 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.459268 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 24293835 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 840170563 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.821157 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.461954 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 361645102 42.98% 42.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 184788916 21.96% 64.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57757386 6.86% 71.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 87297113 10.38% 82.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 30407785 3.61% 85.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26554015 3.16% 88.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10439709 1.24% 90.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9044560 1.07% 91.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 73442013 8.73% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 361187525 42.99% 42.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 184077910 21.91% 64.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57677028 6.86% 71.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 87256558 10.39% 82.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 30345133 3.61% 85.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26488854 3.15% 88.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10500866 1.25% 90.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9042630 1.08% 91.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 73594059 8.76% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 841376599 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 840170563 # Number of insts commited each cycle system.cpu.commit.committedInsts 826847303 # Number of instructions committed system.cpu.commit.committedOps 1530082520 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -597,495 +599,494 @@ system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction -system.cpu.commit.bw_lim_events 73442013 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3187918398 # The number of ROB reads -system.cpu.rob.rob_writes 4974407602 # The number of ROB writes -system.cpu.timesIdled 2034 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 199942 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 73594059 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3185271825 # The number of ROB reads +system.cpu.rob.rob_writes 4972894886 # The number of ROB writes +system.cpu.timesIdled 2025 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 203315 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826847303 # Number of Instructions Simulated system.cpu.committedOps 1530082520 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.178385 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.178385 # CPI: Total CPI of All Threads -system.cpu.ipc 0.848619 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.848619 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2928729782 # number of integer regfile reads -system.cpu.int_regfile_writes 1576941499 # number of integer regfile writes -system.cpu.fp_regfile_reads 236699 # number of floating regfile reads -system.cpu.fp_regfile_writes 4 # number of floating regfile writes -system.cpu.cc_regfile_reads 617876716 # number of cc regfile reads -system.cpu.cc_regfile_writes 419949697 # number of cc regfile writes -system.cpu.misc_regfile_reads 1064375270 # number of misc regfile reads +system.cpu.cpi 1.178091 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.178091 # CPI: Total CPI of All Threads +system.cpu.ipc 0.848831 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.848831 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2927263565 # number of integer regfile reads +system.cpu.int_regfile_writes 1575987355 # number of integer regfile writes +system.cpu.fp_regfile_reads 281295 # number of floating regfile reads +system.cpu.fp_regfile_writes 5 # number of floating regfile writes +system.cpu.cc_regfile_reads 617980900 # number of cc regfile reads +system.cpu.cc_regfile_writes 419571241 # number of cc regfile writes +system.cpu.misc_regfile_reads 1064489388 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2546054 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.989792 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 421112007 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2550150 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.132250 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1890456500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.989792 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998044 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998044 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2545571 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.077195 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 420813077 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2549667 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.046289 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1863239500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.077195 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998066 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998066 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 594 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3458 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 606 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3449 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 851486020 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 851486020 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 272742549 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 272742549 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148366794 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148366794 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 421109343 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 421109343 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 421109343 # number of overall hits -system.cpu.dcache.overall_hits::total 421109343 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2567175 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2567175 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 791417 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 791417 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3358592 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3358592 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3358592 # number of overall misses -system.cpu.dcache.overall_misses::total 3358592 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63549852500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63549852500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26385909500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26385909500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 89935762000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 89935762000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 89935762000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 89935762000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 275309724 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 275309724 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 850870799 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 850870799 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 272443625 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 272443625 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148366897 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148366897 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 420810522 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 420810522 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 420810522 # number of overall hits +system.cpu.dcache.overall_hits::total 420810522 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2558730 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2558730 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 791314 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 791314 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3350044 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3350044 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3350044 # number of overall misses +system.cpu.dcache.overall_misses::total 3350044 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 62817542000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 62817542000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26367570500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26367570500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 89185112500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 89185112500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 89185112500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 89185112500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 275002355 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 275002355 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 424467935 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 424467935 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 424467935 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 424467935 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009325 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009325 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005306 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007912 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007912 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007912 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007912 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24754.780060 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24754.780060 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33340.084304 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33340.084304 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26777.817014 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26777.817014 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26777.817014 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26777.817014 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12440 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 10775 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 917 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.565976 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 769.642857 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2337949 # number of writebacks -system.cpu.dcache.writebacks::total 2337949 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 800910 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 800910 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5810 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 5810 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 806720 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 806720 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 806720 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 806720 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766265 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1766265 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785607 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 785607 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2551872 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2551872 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2551872 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2551872 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37580006000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 37580006000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25494312000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 25494312000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63074318000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 63074318000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63074318000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 63074318000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006416 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006416 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006012 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006012 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006012 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006012 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21276.538911 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21276.538911 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32451.737319 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32451.737319 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24716.881568 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24716.881568 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24716.881568 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24716.881568 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 4004 # number of replacements -system.cpu.icache.tags.tagsinuse 1085.037164 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 216431030 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5719 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 37844.208778 # Average number of references to valid blocks. +system.cpu.dcache.demand_accesses::cpu.data 424160566 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 424160566 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 424160566 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 424160566 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009304 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009304 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005305 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005305 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.007898 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007898 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007898 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007898 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24550.281585 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24550.281585 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33321.248581 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33321.248581 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26622.071979 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26622.071979 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26622.071979 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26622.071979 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9991 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 13057 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 901 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.088790 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 1004.384615 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2337865 # number of writebacks +system.cpu.dcache.writebacks::total 2337865 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 792851 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 792851 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5950 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 5950 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 798801 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 798801 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 798801 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 798801 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1765879 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1765879 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785364 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 785364 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2551243 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2551243 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2551243 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2551243 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37626062000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 37626062000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25475564000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 25475564000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63101626000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63101626000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63101626000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63101626000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006421 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006421 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005265 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005265 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006015 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006015 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006015 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006015 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21307.270770 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21307.270770 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32437.906499 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32437.906499 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24733.679230 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24733.679230 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24733.679230 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24733.679230 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 3942 # number of replacements +system.cpu.icache.tags.tagsinuse 1083.391017 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 216536709 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5668 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 38203.371383 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1085.037164 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.529803 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.529803 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1715 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1083.391017 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.529000 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.529000 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1726 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1557 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.837402 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 432889551 # Number of tag accesses -system.cpu.icache.tags.data_accesses 432889551 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 216431266 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 216431266 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 216431266 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 216431266 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 216431266 # number of overall hits -system.cpu.icache.overall_hits::total 216431266 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9783 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9783 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9783 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9783 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9783 # number of overall misses -system.cpu.icache.overall_misses::total 9783 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 586259000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 586259000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 586259000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 586259000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 586259000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 586259000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 216441049 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 216441049 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 216441049 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 216441049 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 216441049 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 216441049 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 80 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1564 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.842773 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 433100363 # Number of tag accesses +system.cpu.icache.tags.data_accesses 433100363 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 216536917 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 216536917 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 216536917 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 216536917 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 216536917 # number of overall hits +system.cpu.icache.overall_hits::total 216536917 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9643 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9643 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9643 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9643 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9643 # number of overall misses +system.cpu.icache.overall_misses::total 9643 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 597021000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 597021000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 597021000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 597021000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 597021000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 597021000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 216546560 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 216546560 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 216546560 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 216546560 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 216546560 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 216546560 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59926.300726 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 59926.300726 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 59926.300726 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 59926.300726 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 59926.300726 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 59926.300726 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 654 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 486 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 65.400000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 486 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 4004 # number of writebacks -system.cpu.icache.writebacks::total 4004 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2330 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2330 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2330 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2330 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2330 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2330 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7453 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7453 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7453 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7453 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7453 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7453 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 386965000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 386965000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 386965000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 386965000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 386965000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 386965000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51920.703073 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51920.703073 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51920.703073 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51920.703073 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51920.703073 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51920.703073 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 356023 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30628.268694 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4712326 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 388791 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.120461 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 83034365000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 73.003370 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 193.382004 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30361.883320 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.002228 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005902 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.926571 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.934701 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61912.371669 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61912.371669 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61912.371669 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61912.371669 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61912.371669 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61912.371669 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1205 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 100.416667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 3942 # number of writebacks +system.cpu.icache.writebacks::total 3942 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2400 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2400 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2400 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2400 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2400 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2400 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7243 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7243 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7243 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7243 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7243 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7243 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 398397500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 398397500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 398397500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 398397500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 398397500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 398397500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000033 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55004.487091 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55004.487091 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55004.487091 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 55004.487091 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55004.487091 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 55004.487091 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 356141 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30645.512705 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4711567 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 388909 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.114831 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 82679985000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 70.320646 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 194.041770 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30381.150290 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.002146 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005922 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.927159 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.935227 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 168 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1405 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31129 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 176 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1392 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31134 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 41197863 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41197863 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2337949 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2337949 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 3908 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 3908 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1714 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1714 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 577340 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 577340 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3211 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 3211 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1587646 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1587646 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3211 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2164986 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2168197 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3211 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2164986 # number of overall hits -system.cpu.l2cache.overall_hits::total 2168197 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 8 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 8 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206765 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206765 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2422 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2422 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 178399 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 178399 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2422 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 385164 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 387586 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2422 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 385164 # number of overall misses -system.cpu.l2cache.overall_misses::total 387586 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 61000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 61000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 18232552000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 18232552000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 339097000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 339097000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18206411000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 18206411000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 339097000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 36438963000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 36778060000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 339097000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 36438963000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 36778060000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2337949 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2337949 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 3908 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 3908 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1722 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1722 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 784105 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 784105 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5633 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 5633 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1766045 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1766045 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 5633 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2550150 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2555783 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 5633 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2550150 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2555783 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.004646 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.004646 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.263696 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.263696 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.429966 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.429966 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.101016 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.101016 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.429966 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.151036 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151651 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.429966 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.151036 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151651 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7625 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7625 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88180.069161 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88180.069161 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 140007.018993 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 140007.018993 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102054.445372 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 102054.445372 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 140007.018993 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94606.357292 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 94890.063109 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 140007.018993 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94606.357292 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 94890.063109 # average overall miss latency +system.cpu.l2cache.tags.tag_accesses 41192837 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 41192837 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 2337865 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2337865 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 3849 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 3849 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1570 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1570 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 577208 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 577208 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3147 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 3147 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1587166 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1587166 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3147 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2164374 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2167521 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3147 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2164374 # number of overall hits +system.cpu.l2cache.overall_hits::total 2167521 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 206826 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206826 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2443 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2443 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 178467 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 178467 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2443 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 385293 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 387736 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2443 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 385293 # number of overall misses +system.cpu.l2cache.overall_misses::total 387736 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 30500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 30500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 18217457500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 18217457500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 351826000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 351826000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18259810000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 18259810000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 351826000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 36477267500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 36829093500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 351826000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 36477267500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 36829093500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2337865 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2337865 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 3849 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 3849 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1576 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1576 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 784034 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 784034 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5590 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 5590 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1765633 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1765633 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 5590 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2549667 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2555257 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 5590 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2549667 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2555257 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.003807 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.003807 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.263797 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.263797 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.437030 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.437030 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.101078 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.101078 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.437030 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.151115 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151741 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.437030 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.151115 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151741 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 5083.333333 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 5083.333333 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88081.080232 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88081.080232 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 144013.917315 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 144013.917315 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102314.769677 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 102314.769677 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 144013.917315 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94674.098673 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 94984.973023 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 144013.917315 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94674.098673 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 94984.973023 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 295461 # number of writebacks -system.cpu.l2cache.writebacks::total 295461 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 11 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 11 # number of CleanEvict MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 8 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 8 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206765 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206765 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2422 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2422 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 178399 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 178399 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2422 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 385164 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 387586 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2422 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 385164 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 387586 # number of overall MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 159000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 159000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16164902000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16164902000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 314877000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 314877000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16422421000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16422421000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 314877000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32587323000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 32902200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 314877000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32587323000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 32902200000 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 295491 # number of writebacks +system.cpu.l2cache.writebacks::total 295491 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206826 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206826 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2443 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2443 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 178467 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 178467 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2443 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 385293 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 387736 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2443 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 385293 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 387736 # number of overall MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 120000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 120000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16149197500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16149197500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 327396000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 327396000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16475140000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16475140000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 327396000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32624337500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 32951733500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 327396000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32624337500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 32951733500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.004646 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.004646 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263696 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263696 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.429966 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.429966 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.101016 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.101016 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.429966 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151036 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151651 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.429966 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151036 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151651 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19875 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19875 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78180.069161 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78180.069161 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 130007.018993 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 130007.018993 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92054.445372 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92054.445372 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 130007.018993 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84606.357292 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84890.063109 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 130007.018993 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84606.357292 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84890.063109 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5109383 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2550327 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23034 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3629 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3621 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1773498 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2633410 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4004 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 268667 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 1722 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 1722 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 784105 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 784105 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 7453 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1766045 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17090 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649798 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7666888 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 616768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312838336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 313455104 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 357843 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 19025984 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2915348 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009238 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.095698 # Request fanout histogram +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.003807 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.003807 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263797 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263797 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.437030 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.437030 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.101078 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.101078 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.437030 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151115 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151741 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.437030 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151115 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151741 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78081.080232 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78081.080232 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 134013.917315 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 134013.917315 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92314.769677 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92314.769677 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 134013.917315 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84674.098673 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84984.973023 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 134013.917315 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84674.098673 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84984.973023 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5107999 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2549734 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 19983 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3565 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3558 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1772876 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2633356 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 3942 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 268356 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 1576 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 1576 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 784034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 784034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 7243 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1765633 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16775 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7648057 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7664832 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 610048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312802048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 313412096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 357794 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 19017216 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2914627 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.008154 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.089959 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2888424 99.08% 99.08% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 26916 0.92% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 8 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2890867 99.18% 99.18% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 23753 0.81% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2915348 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4896697394 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2914627 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4895855901 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 11180498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10867494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3826086106 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3825288599 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 740706 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 353592 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 740964 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 353722 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 180821 # Transaction distribution -system.membus.trans_dist::WritebackDirty 295461 # Transaction distribution -system.membus.trans_dist::CleanEvict 57651 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 180910 # Transaction distribution +system.membus.trans_dist::WritebackDirty 295491 # Transaction distribution +system.membus.trans_dist::CleanEvict 57731 # Transaction distribution system.membus.trans_dist::UpgradeReq 9 # Transaction distribution -system.membus.trans_dist::ReadExReq 206764 # Transaction distribution -system.membus.trans_dist::ReadExResp 206764 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 180821 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1128291 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1128291 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1128291 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43714944 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43714944 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43714944 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 206823 # Transaction distribution +system.membus.trans_dist::ReadExResp 206823 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 180910 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1128697 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1128697 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1128697 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43726336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43726336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43726336 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 387594 # Request fanout histogram +system.membus.snoop_fanout::samples 387742 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 387594 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 387742 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 387594 # Request fanout histogram -system.membus.reqLayer0.occupancy 1998981000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 387742 # Request fanout histogram +system.membus.reqLayer0.occupancy 1998138500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 2050982000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2051606500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index b2bc0dd63..812de15cb 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.225207 # Number of seconds simulated -sim_ticks 225206521000 # Number of ticks simulated -final_tick 225206521000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.225185 # Number of seconds simulated +sim_ticks 225184887000 # Number of ticks simulated +final_tick 225184887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 289736 # Simulator instruction rate (inst/s) -host_op_rate 347860 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 238979319 # Simulator tick rate (ticks/s) -host_mem_usage 279872 # Number of bytes of host memory used -host_seconds 942.37 # Real time elapsed on the host +host_inst_rate 292846 # Simulator instruction rate (inst/s) +host_op_rate 351594 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 241521552 # Simulator tick rate (ticks/s) +host_mem_usage 280036 # Number of bytes of host memory used +host_seconds 932.36 # Real time elapsed on the host sim_insts 273037855 # Number of instructions simulated sim_ops 327812212 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory -system.physmem.bytes_read::total 485568 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219136 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 485504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3423 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4163 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7587 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 973045 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1183056 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2156101 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 973045 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 973045 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 973045 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1183056 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2156101 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7587 # Number of read requests accepted +system.physmem.num_reads::total 7586 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 972854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1183170 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2156024 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 972854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 972854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 972854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1183170 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2156024 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7586 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7587 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7586 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 485568 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 485504 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 485568 # Total read bytes from the system interface side +system.physmem.bytesReadSys 485504 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -57,7 +57,7 @@ system.physmem.perBankRdBursts::11 428 # Pe system.physmem.perBankRdBursts::12 553 # Per bank write bursts system.physmem.perBankRdBursts::13 705 # Per bank write bursts system.physmem.perBankRdBursts::14 639 # Per bank write bursts -system.physmem.perBankRdBursts::15 543 # Per bank write bursts +system.physmem.perBankRdBursts::15 542 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 225206267000 # Total gap between requests +system.physmem.totGap 225184633000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7587 # Read request sizes (log2) +system.physmem.readPktSize::6 7586 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,7 +91,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6691 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6690 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 845 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1511 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 320.635341 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 191.281375 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 328.659938 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 540 35.74% 35.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 351 23.23% 58.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 165 10.92% 69.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 80 5.29% 75.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 78 5.16% 80.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 55 3.64% 83.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 33 2.18% 86.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 36 2.38% 88.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 173 11.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1511 # Bytes accessed per row activation -system.physmem.totQLat 232471000 # Total ticks spent queuing -system.physmem.totMemAccLat 374727250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37935000 # Total ticks spent in databus transfers -system.physmem.avgQLat 30640.70 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1509 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 321.017893 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 191.649066 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 328.624854 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 538 35.65% 35.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 351 23.26% 58.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 166 11.00% 69.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 79 5.24% 75.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 78 5.17% 80.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 56 3.71% 84.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 32 2.12% 86.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 36 2.39% 88.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 173 11.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1509 # Bytes accessed per row activation +system.physmem.totQLat 232077250 # Total ticks spent queuing +system.physmem.totMemAccLat 374314750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37930000 # Total ticks spent in databus transfers +system.physmem.avgQLat 30592.84 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 49390.70 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 49342.84 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s @@ -217,66 +217,66 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6073 # Number of row buffer hits during reads +system.physmem.readRowHits 6074 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.04 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.07 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 29683177.41 # Average gap between requests -system.physmem.pageHitRate 80.04 # Row buffer hit rate, read and write combined +system.physmem.avgGap 29684238.47 # Average gap between requests +system.physmem.pageHitRate 80.07 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 4726680 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 2504700 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 27553260 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 284578320.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 100446540 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 15488640 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 721249500 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 385420800 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 53424510300 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 54966478740 # Total energy per rank (pJ) -system.physmem_0.averagePower 244.071435 # Core power per rank (mW) -system.physmem_0.totalIdleTime 224945712750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 29370000 # Time in different power states +system.physmem_0.actBackEnergy 100520070 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 15505920 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 721291110 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 385301760 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 53419321200 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 54961303020 # Total energy per rank (pJ) +system.physmem_0.averagePower 244.071899 # Core power per rank (mW) +system.physmem_0.totalIdleTime 224923904000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 29388000 # Time in different power states system.physmem_0.memoryStateTime::REF 121010000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 222360521000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 1003708750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 110211000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 1581700250 # Time in different power states -system.physmem_1.actEnergy 6083280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3229545 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 26617920 # Energy for read commands per rank (pJ) +system.physmem_0.memoryStateTime::SREF 222338897000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 1003385750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 110367750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 1581838500 # Time in different power states +system.physmem_1.actEnergy 6069000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3221955 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 26610780 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 394598880.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 121237860 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 22348800 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 914380890 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 605052000 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 53195794545 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 55289408190 # Total energy per rank (pJ) -system.physmem_1.averagePower 245.505361 # Core power per rank (mW) -system.physmem_1.totalIdleTime 224881567000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 42133000 # Time in different power states +system.physmem_1.actBackEnergy 121194540 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 22344960 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 914224140 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 605228160 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 53190600045 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 55284153510 # Total energy per rank (pJ) +system.physmem_1.averagePower 245.505612 # Core power per rank (mW) +system.physmem_1.totalIdleTime 224860041750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 42127000 # Time in different power states system.physmem_1.memoryStateTime::REF 167838000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 221301429000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1575669750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 114195250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 2005256000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 32430299 # Number of BP lookups -system.cpu.branchPred.condPredicted 16924101 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 738493 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17494977 # Number of BTB lookups -system.cpu.branchPred.BTBHits 12858505 # Number of BTB hits +system.physmem_1.memoryStateTime::SREF 221279795000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 1576124250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 114092500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 2004910250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 32421416 # Number of BP lookups +system.cpu.branchPred.condPredicted 16919401 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 734831 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17534346 # Number of BTB lookups +system.cpu.branchPred.BTBHits 12860140 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 73.498268 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6523139 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 73.342570 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6521085 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2303930 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2264813 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 39117 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 128237 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 2302887 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2263691 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 39196 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 128438 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -306,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -336,7 +336,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -366,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -397,16 +397,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 225206521000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 450413042 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 225184887000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 450369774 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037855 # Number of instructions committed system.cpu.committedOps 327812212 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2063976 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2044614 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.649636 # CPI: cycles per instruction -system.cpu.ipc 0.606194 # IPC: instructions per cycle +system.cpu.cpi 1.649477 # CPI: cycles per instruction +system.cpu.ipc 0.606253 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 104312542 31.82% 31.82% # Class of committed instruction system.cpu.op_class_0::IntMult 2145905 0.65% 32.48% # Class of committed instruction @@ -446,16 +446,16 @@ system.cpu.op_class_0::FloatMemWrite 27367218 8.35% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 327812212 # Class of committed instruction -system.cpu.tickCycles 434950536 # Number of cycles that the object actually ticked -system.cpu.idleCycles 15462506 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 434912818 # Number of cycles that the object actually ticked +system.cpu.idleCycles 15456956 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1355 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.768110 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168654205 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3085.765100 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168647477 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37379.034796 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37377.543661 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768110 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.765100 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.753361 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.753361 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id @@ -465,23 +465,23 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 7 system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337326812 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337326812 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 86521430 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86521430 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 337313356 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337313356 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 86514704 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86514704 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82047447 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 82047447 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 63538 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 63538 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 63536 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 63536 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168568877 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168568877 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168632415 # number of overall hits -system.cpu.dcache.overall_hits::total 168632415 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 168562151 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168562151 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168625687 # number of overall hits +system.cpu.dcache.overall_hits::total 168625687 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1710 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1710 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 5230 # number of WriteReq misses @@ -492,28 +492,28 @@ system.cpu.dcache.demand_misses::cpu.data 6940 # n system.cpu.dcache.demand_misses::total 6940 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 6945 # number of overall misses system.cpu.dcache.overall_misses::total 6945 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 177324000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 177324000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 487891500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 487891500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 665215500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 665215500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 665215500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 665215500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86523140 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86523140 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 177071500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 177071500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 487051000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 487051000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 664122500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 664122500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 664122500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 664122500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86516414 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86516414 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 63543 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 63543 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 63541 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 63541 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168575817 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168575817 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168639360 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168639360 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168569091 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168569091 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168632632 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168632632 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses @@ -524,14 +524,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000041 system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000041 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103698.245614 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 103698.245614 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93287.093690 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 93287.093690 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 95852.377522 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 95852.377522 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 95783.369330 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 95783.369330 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103550.584795 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 103550.584795 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93126.386233 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 93126.386233 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 95694.884726 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 95694.884726 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 95625.989921 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 95625.989921 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -558,16 +558,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4509 system.cpu.dcache.demand_mshr_misses::total 4509 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4512 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4512 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 172098000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 172098000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 285707500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 285707500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171838500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 171838500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 285292000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 285292000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 259000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 259000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 457805500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 457805500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 458064500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 458064500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 457130500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 457130500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 457389500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 457389500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -578,24 +578,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 105001.830384 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 105001.830384 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99549.651568 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99549.651568 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 104843.502135 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 104843.502135 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99404.878049 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99404.878049 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 86333.333333 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 86333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101531.492570 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 101531.492570 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101521.387411 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 101521.387411 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 38188 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.800722 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 69819801 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 40125 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1740.057346 # Average number of references to valid blocks. +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101381.791972 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 101381.791972 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101371.786348 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 101371.786348 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 38251 # number of replacements +system.cpu.icache.tags.tagsinuse 1924.799688 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 69805458 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 40188 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1736.972678 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.800722 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.799688 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.939844 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.939844 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id @@ -605,179 +605,179 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 32 system.cpu.icache.tags.age_task_id_blocks_1024::3 277 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 139759979 # Number of tag accesses -system.cpu.icache.tags.data_accesses 139759979 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 69819801 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 69819801 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 69819801 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 69819801 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 69819801 # number of overall hits -system.cpu.icache.overall_hits::total 69819801 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 40126 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 40126 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 40126 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 40126 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 40126 # number of overall misses -system.cpu.icache.overall_misses::total 40126 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 817900500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 817900500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 817900500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 817900500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 817900500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 817900500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 69859927 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 69859927 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 69859927 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 69859927 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 69859927 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 69859927 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000574 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000574 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000574 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000574 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000574 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000574 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20383.305089 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20383.305089 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20383.305089 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20383.305089 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20383.305089 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20383.305089 # average overall miss latency +system.cpu.icache.tags.tag_accesses 139731482 # Number of tag accesses +system.cpu.icache.tags.data_accesses 139731482 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 69805458 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 69805458 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 69805458 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 69805458 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 69805458 # number of overall hits +system.cpu.icache.overall_hits::total 69805458 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 40189 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 40189 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 40189 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 40189 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 40189 # number of overall misses +system.cpu.icache.overall_misses::total 40189 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 818936000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 818936000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 818936000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 818936000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 818936000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 818936000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 69845647 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 69845647 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 69845647 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 69845647 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 69845647 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 69845647 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000575 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000575 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000575 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000575 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000575 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000575 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20377.118117 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20377.118117 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20377.118117 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20377.118117 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20377.118117 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20377.118117 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 38188 # number of writebacks -system.cpu.icache.writebacks::total 38188 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 40126 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 40126 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 40126 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 40126 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 40126 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 40126 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 777775500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 777775500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 777775500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 777775500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 777775500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 777775500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000574 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000574 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19383.330010 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19383.330010 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19383.330010 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19383.330010 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19383.330010 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19383.330010 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states +system.cpu.icache.writebacks::writebacks 38251 # number of writebacks +system.cpu.icache.writebacks::total 38251 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 40189 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 40189 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 40189 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 40189 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 40189 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 40189 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 778748000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 778748000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 778748000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 778748000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 778748000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 778748000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000575 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000575 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000575 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000575 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000575 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000575 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19377.142999 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19377.142999 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19377.142999 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19377.142999 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19377.142999 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19377.142999 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 6596.216022 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 61516 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 7587 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 8.108080 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 6596.199570 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 61643 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 7586 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 8.125890 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.840742 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.375280 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096675 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.827893 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.371677 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096674 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.104626 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.201301 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 7587 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::total 0.201300 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 7586 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 789 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 788 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6671 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.231537 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 560755 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 560755 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.231506 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 561762 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 561762 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 1010 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 1010 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 23270 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 23270 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::writebacks 23333 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 23333 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36700 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 36700 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36764 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 36764 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 292 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 292 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 36700 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 36764 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 308 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 37008 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 36700 # number of overall hits +system.cpu.l2cache.demand_hits::total 37072 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 36764 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 308 # number of overall hits -system.cpu.l2cache.overall_hits::total 37008 # number of overall hits +system.cpu.l2cache.overall_hits::total 37072 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 2854 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 2854 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3426 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3426 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3425 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3425 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1350 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 1350 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3426 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 3425 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 4204 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7630 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3426 # number of overall misses +system.cpu.l2cache.demand_misses::total 7629 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3425 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses -system.cpu.l2cache.overall_misses::total 7630 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 281205000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 281205000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 317302500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 317302500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 166631000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 166631000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 317302500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 447836000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 765138500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 317302500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 447836000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 765138500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::total 7629 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 280789500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 280789500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 317508500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 317508500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 166371500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 166371500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 317508500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 447161000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 764669500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 317508500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 447161000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 764669500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 1010 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 1010 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 23270 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 23270 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 23333 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 23333 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 2870 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 40126 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 40126 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 40189 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 40189 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1642 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 1642 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 40126 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 40189 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4512 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 44638 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 40126 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 44701 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 40189 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4512 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 44638 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 44701 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994425 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.994425 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.085381 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.085381 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.085222 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.085222 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.822168 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.822168 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.085381 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.085222 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.931738 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.170931 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085381 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.170667 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085222 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.931738 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.170931 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98530.133146 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98530.133146 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92616.024518 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92616.024518 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123430.370370 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123430.370370 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92616.024518 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106526.165557 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 100280.275229 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92616.024518 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106526.165557 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 100280.275229 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.170667 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98384.548003 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98384.548003 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92703.211679 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92703.211679 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123238.148148 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123238.148148 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92703.211679 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106365.604186 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 100231.943898 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92703.211679 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106365.604186 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 100231.943898 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -796,122 +796,122 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 41 system.cpu.l2cache.overall_mshr_hits::total 43 # number of overall MSHR hits system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2854 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3424 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3424 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3423 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3423 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1309 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1309 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3424 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3423 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 4163 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7587 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3424 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7586 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3423 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4163 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7587 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 252665000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 252665000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 282914000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 282914000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 150580000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 150580000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 282914000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 403245000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 686159000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 282914000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 403245000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 686159000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 7586 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 252249500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 252249500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 283130000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 283130000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 150320500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 150320500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 283130000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 402570000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 685700000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 283130000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 402570000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 685700000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.085331 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085173 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.085173 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.797199 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.797199 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.085173 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.169967 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.169705 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085173 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.169967 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88530.133146 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88530.133146 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82626.752336 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82626.752336 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115034.377387 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115034.377387 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82626.752336 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90438.776855 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82626.752336 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90438.776855 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 84181 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 39645 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.169705 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88384.548003 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88384.548003 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82713.993573 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82713.993573 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114836.134454 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114836.134454 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82713.993573 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96701.897670 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90390.192460 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82713.993573 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96701.897670 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90390.192460 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 84307 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 39708 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15035 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 41767 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 41830 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 38188 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 38251 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 40126 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 40189 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1642 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118439 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118628 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10379 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 128818 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5012032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 129007 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5020096 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 5365440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 5373504 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 44638 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.339106 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.473411 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 44701 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.338628 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.473248 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 29501 66.09% 66.09% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 15137 33.91% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 29564 66.14% 66.14% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 15137 33.86% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 44638 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 81288500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 44701 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 81414500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 60188498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 60282998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6789457 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 7587 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 7586 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4733 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 4732 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution system.membus.trans_dist::ReadExResp 2854 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4733 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15174 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15174 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 485568 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 4732 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15172 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15172 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 485504 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 7587 # Request fanout histogram +system.membus.snoop_fanout::samples 7586 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7587 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7586 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7587 # Request fanout histogram -system.membus.reqLayer0.occupancy 9082500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7586 # Request fanout histogram +system.membus.reqLayer0.occupancy 9076000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 40299000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40293000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index c49c5de69..faffc36d8 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.124349 # Number of seconds simulated -sim_ticks 124348696500 # Number of ticks simulated -final_tick 124348696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.124341 # Number of seconds simulated +sim_ticks 124340889500 # Number of ticks simulated +final_tick 124340889500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 233440 # Simulator instruction rate (inst/s) -host_op_rate 280271 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 106315167 # Simulator tick rate (ticks/s) -host_mem_usage 292792 # Number of bytes of host memory used -host_seconds 1169.62 # Real time elapsed on the host +host_inst_rate 229813 # Simulator instruction rate (inst/s) +host_op_rate 275917 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 104656772 # Simulator tick rate (ticks/s) +host_mem_usage 292960 # Number of bytes of host memory used +host_seconds 1188.08 # Real time elapsed on the host sim_insts 273037218 # Number of instructions simulated sim_ops 327811600 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1887808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 14649536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 167872 # Number of bytes read from this memory -system.physmem.bytes_read::total 16705216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1887808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1887808 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 29497 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 228899 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2623 # Number of read requests responded to by this memory -system.physmem.num_reads::total 261019 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 15181566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 117810129 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1350010 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 134341706 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 15181566 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 15181566 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 15181566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 117810129 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1350010 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 134341706 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 261020 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1894400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 14645312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 169216 # Number of bytes read from this memory +system.physmem.bytes_read::total 16708928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1894400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1894400 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 29600 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 228833 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2644 # Number of read requests responded to by this memory +system.physmem.num_reads::total 261077 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 15235535 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 117783555 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1360904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 134379994 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 15235535 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 15235535 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 15235535 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 117783555 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1360904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 134379994 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 261078 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 261020 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 261078 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 16705280 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 16708992 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 16705280 # Total read bytes from the system interface side +system.physmem.bytesReadSys 16708992 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1258 # Per bank write bursts -system.physmem.perBankRdBursts::1 69987 # Per bank write bursts -system.physmem.perBankRdBursts::2 1297 # Per bank write bursts -system.physmem.perBankRdBursts::3 10756 # Per bank write bursts -system.physmem.perBankRdBursts::4 42907 # Per bank write bursts -system.physmem.perBankRdBursts::5 121816 # Per bank write bursts -system.physmem.perBankRdBursts::6 153 # Per bank write bursts -system.physmem.perBankRdBursts::7 252 # Per bank write bursts -system.physmem.perBankRdBursts::8 224 # Per bank write bursts +system.physmem.perBankRdBursts::0 1259 # Per bank write bursts +system.physmem.perBankRdBursts::1 69989 # Per bank write bursts +system.physmem.perBankRdBursts::2 1294 # Per bank write bursts +system.physmem.perBankRdBursts::3 10805 # Per bank write bursts +system.physmem.perBankRdBursts::4 42847 # Per bank write bursts +system.physmem.perBankRdBursts::5 121814 # Per bank write bursts +system.physmem.perBankRdBursts::6 160 # Per bank write bursts +system.physmem.perBankRdBursts::7 259 # Per bank write bursts +system.physmem.perBankRdBursts::8 225 # Per bank write bursts system.physmem.perBankRdBursts::9 562 # Per bank write bursts -system.physmem.perBankRdBursts::10 7773 # Per bank write bursts +system.physmem.perBankRdBursts::10 7823 # Per bank write bursts system.physmem.perBankRdBursts::11 812 # Per bank write bursts -system.physmem.perBankRdBursts::12 1213 # Per bank write bursts -system.physmem.perBankRdBursts::13 743 # Per bank write bursts -system.physmem.perBankRdBursts::14 657 # Per bank write bursts +system.physmem.perBankRdBursts::12 1216 # Per bank write bursts +system.physmem.perBankRdBursts::13 747 # Per bank write bursts +system.physmem.perBankRdBursts::14 656 # Per bank write bursts system.physmem.perBankRdBursts::15 610 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 124348687000 # Total gap between requests +system.physmem.totGap 124340880000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 261020 # Read request sizes (log2) +system.physmem.readPktSize::6 261078 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,20 +95,20 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 204123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 43351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 303 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 212 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 241 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 204158 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 43358 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 247 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -191,29 +191,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67933 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 245.871432 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.817049 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 200.519544 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18227 26.83% 26.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22195 32.67% 59.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11448 16.85% 76.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6857 10.09% 86.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4767 7.02% 93.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2062 3.04% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1306 1.92% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 411 0.61% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 660 0.97% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67933 # Bytes accessed per row activation -system.physmem.totQLat 4577430956 # Total ticks spent queuing -system.physmem.totMemAccLat 9471555956 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1305100000 # Total ticks spent in databus transfers -system.physmem.avgQLat 17536.71 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 67983 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 245.745201 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.705876 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 200.483366 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18259 26.86% 26.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22263 32.75% 59.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11383 16.74% 76.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6868 10.10% 86.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4760 7.00% 93.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2080 3.06% 96.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1310 1.93% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 394 0.58% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 666 0.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67983 # Bytes accessed per row activation +system.physmem.totQLat 4612072505 # Total ticks spent queuing +system.physmem.totMemAccLat 9507285005 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1305390000 # Total ticks spent in databus transfers +system.physmem.avgQLat 17665.50 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 36286.71 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 134.34 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 36415.50 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 134.38 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 134.34 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 134.38 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.05 # Data bus utilization in percentage @@ -221,66 +221,66 @@ system.physmem.busUtilRead 1.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 193077 # Number of row buffer hits during reads +system.physmem.readRowHits 193085 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.97 # Row buffer hit rate for reads +system.physmem.readRowHitRate 73.96 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 476395.25 # Average gap between requests -system.physmem.pageHitRate 73.97 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 450269820 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 239312700 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1773761640 # Energy for read commands per rank (pJ) +system.physmem.avgGap 476259.51 # Average gap between requests +system.physmem.pageHitRate 73.96 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 450291240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 239324085 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1773768780 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 9689184960.000002 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4649576640 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 227532000 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 45899424420 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 3643060800 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 957889500 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 67530012480 # Total energy per rank (pJ) -system.physmem_0.averagePower 543.069721 # Core power per rank (mW) -system.physmem_0.totalIdleTime 113559853415 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 155359000 # Time in different power states -system.physmem_0.memoryStateTime::REF 4100146000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 3415967750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 9487195385 # Time in different power states -system.physmem_0.memoryStateTime::ACT 6533205335 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 100656823030 # Time in different power states -system.physmem_1.actEnergy 34836060 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 18489240 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 89914020 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 9681809280.000002 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4644193560 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 227236800 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 45907805700 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 3604922400 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 978458700 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 67507810545 # Total energy per rank (pJ) +system.physmem_0.averagePower 542.925264 # Core power per rank (mW) +system.physmem_0.totalIdleTime 113563299646 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 155533000 # Time in different power states +system.physmem_0.memoryStateTime::REF 4097020000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 3501663750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 9387944632 # Time in different power states +system.physmem_0.memoryStateTime::ACT 6524904104 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 100673824014 # Time in different power states +system.physmem_1.actEnergy 35171640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 18667605 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 90321000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3070741440.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 722151240 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 123038400 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 10175174880 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 3785444640 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 22033476180 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 40053946380 # Total energy per rank (pJ) -system.physmem_1.averagePower 322.109899 # Core power per rank (mW) -system.physmem_1.totalIdleTime 122443240524 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 197934000 # Time in different power states -system.physmem_1.memoryStateTime::REF 1303004000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 90271203500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 9858082832 # Time in different power states -system.physmem_1.memoryStateTime::ACT 404517976 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 22313954192 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 35976625 # Number of BP lookups -system.cpu.branchPred.condPredicted 19268286 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 984581 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17895680 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13922117 # Number of BTB hits +system.physmem_1.refreshEnergy 3119298000.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 731861760 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 127236960 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 10304428080 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 3803073120 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 21964091670 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 40194673995 # Total energy per rank (pJ) +system.physmem_1.averagePower 323.261913 # Core power per rank (mW) +system.physmem_1.totalIdleTime 122403387505 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 207240000 # Time in different power states +system.physmem_1.memoryStateTime::REF 1323736000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 89902145500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 9903979079 # Time in different power states +system.physmem_1.memoryStateTime::ACT 406525995 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 22597262926 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 36038003 # Number of BP lookups +system.cpu.branchPred.condPredicted 19334387 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 996297 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17830996 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13933502 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 77.795965 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6952257 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4419 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2517536 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2473662 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 43874 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 129189 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 78.142029 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6950609 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4465 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 2515874 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2470358 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 45516 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 129389 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -310,7 +310,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -340,7 +340,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -370,7 +370,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -401,135 +401,135 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 124348696500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 248697394 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 124340889500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 248681780 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13177926 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 309504909 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35976625 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23348036 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 231160130 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1995425 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1604 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 63 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3168 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 82224377 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 34576 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 245340603 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.517503 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.300446 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13212448 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 309769989 # Number of instructions fetch has processed +system.cpu.fetch.Branches 36038003 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23354469 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 231113604 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2018885 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1934 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 92 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 3406 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 82291256 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 35072 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 245340926 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.517468 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.300338 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 84898952 34.60% 34.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 40504202 16.51% 51.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 28011427 11.42% 62.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 91926022 37.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 84879866 34.60% 34.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 40535888 16.52% 51.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 28014472 11.42% 62.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 91910700 37.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 245340603 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.144660 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.244504 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 27511038 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 94682480 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 97198198 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 25085064 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 863823 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6682260 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 134191 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 348414004 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3355254 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 863823 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 44231004 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38750016 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 289461 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 104525811 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 56680488 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 344543449 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1457117 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7869034 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 94704 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 8433947 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 28409379 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 3429059 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 394730853 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2217537837 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 335903225 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 192790660 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 245340926 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.144916 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.245648 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27542743 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 94606230 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 97234991 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 25081957 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 875005 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 12946400 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 134756 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 348426325 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3406644 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 875005 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44284460 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38724844 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 289442 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 104535895 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 56631280 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 344535849 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1483850 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7863336 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 96546 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 8390481 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 28393613 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 3430855 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 394784790 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2217316444 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 335868704 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 192847846 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230048 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22500805 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11602 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11569 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 59464824 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89978946 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 84398563 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2367642 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1978869 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343240723 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22618 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 339371435 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 952430 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 15451741 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36726619 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 498 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 245340603 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.383266 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.138851 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 22554742 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11609 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11576 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 59430212 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89918066 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 84391902 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2366315 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1969070 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343213178 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22626 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 339325700 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 951900 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 15424204 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36793818 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 506 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 245340926 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.383078 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.139070 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 64256390 26.19% 26.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 77349427 31.53% 57.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 59666013 24.32% 82.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34385256 14.02% 96.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 8895869 3.63% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 775150 0.32% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 12498 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 64299867 26.21% 26.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 77319752 31.52% 57.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 59651654 24.31% 82.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34378652 14.01% 96.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 8900677 3.63% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 777968 0.32% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 12356 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 245340603 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 245340926 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8783262 6.81% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7311 0.01% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 160118 0.12% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 165260 0.13% 7.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 81600 0.06% 7.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 59605 0.05% 7.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 821029 0.64% 7.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 312918 0.24% 8.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 382736 0.30% 8.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 27486319 21.30% 29.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 41316597 32.01% 61.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 30690860 23.78% 85.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 18793838 14.56% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8768859 6.80% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7313 0.01% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 162373 0.13% 6.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 163818 0.13% 7.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 81957 0.06% 7.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 59658 0.05% 7.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 818593 0.63% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 313085 0.24% 8.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 382100 0.30% 8.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 27482783 21.31% 29.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 41323323 32.04% 61.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 30643180 23.76% 85.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 18783688 14.56% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 108168046 31.87% 31.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148103 0.63% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 108181018 31.88% 31.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148109 0.63% 32.51% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.51% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.51% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.51% # Type of FU issued @@ -550,93 +550,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.51% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6799230 2.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8596305 2.53% 37.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3207463 0.95% 37.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592644 0.47% 38.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20838397 6.14% 44.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7175267 2.11% 46.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7140594 2.10% 48.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175297 0.05% 48.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 46512276 13.71% 62.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 55971076 16.49% 79.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 43494028 12.82% 91.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 27552709 8.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6799471 2.00% 34.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8597209 2.53% 37.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3207374 0.95% 38.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592649 0.47% 38.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20858202 6.15% 44.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7175067 2.11% 46.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7140627 2.10% 48.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175298 0.05% 48.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 46505269 13.71% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 55942906 16.49% 79.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 43451689 12.81% 91.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 27550812 8.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 339371435 # Type of FU issued -system.cpu.iq.rate 1.364596 # Inst issue rate -system.cpu.iq.fu_busy_cnt 129061453 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.380296 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 766002730 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 235175743 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 219154982 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 288094626 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 123554211 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 116970856 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 298827396 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 169605492 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5587628 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 339325700 # Type of FU issued +system.cpu.iq.rate 1.364498 # Inst issue rate +system.cpu.iq.fu_busy_cnt 128990730 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.380138 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 765966009 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 235211704 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 219112487 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 287968947 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 123463225 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 116939299 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 298793937 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 169522493 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5585313 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4246671 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7079 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14875 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2022946 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4185791 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7155 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14925 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2016285 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 158625 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 537538 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 158671 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 539433 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 863823 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1349690 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1747618 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343264743 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 875005 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1351770 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1745589 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343237205 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89978946 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 84398563 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11585 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6720 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1741103 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14875 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 437791 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 454404 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 892195 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 337380808 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 89446151 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1990627 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 89918066 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 84391902 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11593 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6365 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1739416 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14925 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 447604 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 457294 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 904898 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 337307001 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 89393919 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2018699 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1402 # number of nop insts executed -system.cpu.iew.exec_refs 172577891 # number of memory reference insts executed -system.cpu.iew.exec_branches 31542264 # Number of branches executed -system.cpu.iew.exec_stores 83131740 # Number of stores executed -system.cpu.iew.exec_rate 1.356592 # Inst execution rate -system.cpu.iew.wb_sent 336269596 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 336125838 # cumulative count of insts written-back -system.cpu.iew.wb_producers 153087171 # num instructions producing a value -system.cpu.iew.wb_consumers 267302196 # num instructions consuming a value -system.cpu.iew.wb_rate 1.351545 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.572712 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 14157457 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1401 # number of nop insts executed +system.cpu.iew.exec_refs 172494904 # number of memory reference insts executed +system.cpu.iew.exec_branches 31547244 # Number of branches executed +system.cpu.iew.exec_stores 83100985 # Number of stores executed +system.cpu.iew.exec_rate 1.356380 # Inst execution rate +system.cpu.iew.wb_sent 336195874 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 336051786 # cumulative count of insts written-back +system.cpu.iew.wb_producers 153071265 # num instructions producing a value +system.cpu.iew.wb_consumers 267284033 # num instructions consuming a value +system.cpu.iew.wb_rate 1.351333 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.572691 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 14115058 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 850692 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 243149020 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.348195 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.043585 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 861860 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 243135580 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.348269 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.043603 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 113393055 46.64% 46.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 66012492 27.15% 73.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 21342156 8.78% 82.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13170021 5.42% 87.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8181798 3.36% 91.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4369731 1.80% 93.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2981979 1.23% 94.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2444680 1.01% 95.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11253108 4.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 113362923 46.63% 46.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 66036162 27.16% 73.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 21343595 8.78% 82.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13169605 5.42% 87.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8174730 3.36% 91.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4365960 1.80% 93.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2981752 1.23% 94.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2446011 1.01% 95.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11254842 4.63% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 243149020 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 243135580 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037830 # Number of instructions committed system.cpu.commit.committedOps 327812212 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -686,555 +686,556 @@ system.cpu.commit.op_class_0::FloatMemWrite 27367218 8.35% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812212 # Class of committed instruction -system.cpu.commit.bw_lim_events 11253108 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 573863058 # The number of ROB reads -system.cpu.rob.rob_writes 686133284 # The number of ROB writes -system.cpu.timesIdled 39270 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3356791 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 11254842 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 573805485 # The number of ROB reads +system.cpu.rob.rob_writes 686062388 # The number of ROB writes +system.cpu.timesIdled 39277 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3340854 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037218 # Number of Instructions Simulated system.cpu.committedOps 327811600 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.910855 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.910855 # CPI: Total CPI of All Threads -system.cpu.ipc 1.097869 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.097869 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 325196483 # number of integer regfile reads -system.cpu.int_regfile_writes 134110146 # number of integer regfile writes -system.cpu.fp_regfile_reads 186451278 # number of floating regfile reads -system.cpu.fp_regfile_writes 131762607 # number of floating regfile writes -system.cpu.cc_regfile_reads 1279524952 # number of cc regfile reads -system.cpu.cc_regfile_writes 79965424 # number of cc regfile writes -system.cpu.misc_regfile_reads 1056166666 # number of misc regfile reads +system.cpu.cpi 0.910798 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.910798 # CPI: Total CPI of All Threads +system.cpu.ipc 1.097938 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.097938 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 325088854 # number of integer regfile reads +system.cpu.int_regfile_writes 134066659 # number of integer regfile writes +system.cpu.fp_regfile_reads 186464530 # number of floating regfile reads +system.cpu.fp_regfile_writes 131741747 # number of floating regfile writes +system.cpu.cc_regfile_reads 1279144313 # number of cc regfile reads +system.cpu.cc_regfile_writes 80001955 # number of cc regfile writes +system.cpu.misc_regfile_reads 1055862294 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1542800 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.844324 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 161972906 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1543312 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 104.951498 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 90889000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.844324 # Average occupied blocks per requestor +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1544317 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.844251 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 161914838 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1544829 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 104.810848 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 91273000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.844251 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999696 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999696 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 333232684 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 333232684 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 80960207 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 80960207 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80921128 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80921128 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 69704 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 69704 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10908 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10908 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 333130269 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 333130269 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 80902071 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 80902071 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80921196 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80921196 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 69698 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 69698 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10906 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10906 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 161881335 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 161881335 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 161951039 # number of overall hits -system.cpu.dcache.overall_hits::total 161951039 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2740251 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2740251 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1131571 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1131571 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 161823267 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 161823267 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 161892965 # number of overall hits +system.cpu.dcache.overall_hits::total 161892965 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2746434 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2746434 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1131503 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1131503 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 13 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 13 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3871822 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3871822 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3871840 # number of overall misses -system.cpu.dcache.overall_misses::total 3871840 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 47426688500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 47426688500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9189520410 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9189520410 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3877937 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3877937 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3877950 # number of overall misses +system.cpu.dcache.overall_misses::total 3877950 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 47498967000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 47498967000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9188860405 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9188860405 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 194000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 194000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 56616208910 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 56616208910 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 56616208910 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 56616208910 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 83700458 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 83700458 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 56687827405 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 56687827405 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 56687827405 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 56687827405 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 83648505 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 83648505 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 69722 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 69722 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10912 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10912 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 69711 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 69711 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10910 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10910 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 165753157 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 165753157 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 165822879 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 165822879 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032739 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032739 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013791 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013791 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000258 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.000258 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 165701204 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 165701204 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 165770915 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 165770915 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032833 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032833 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013790 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013790 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000186 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000186 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000367 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000367 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023359 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023359 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023349 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023349 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17307.424940 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17307.424940 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8121.028561 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8121.028561 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023403 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023403 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023393 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023393 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17294.778247 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17294.778247 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8120.933312 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8120.933312 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14622.626998 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14622.626998 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14622.559018 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14622.559018 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14618.037221 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14618.037221 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14617.988217 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14617.988217 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1097340 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1101938 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 136170 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 136754 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8.058603 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1542800 # number of writebacks -system.cpu.dcache.writebacks::total 1542800 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1417655 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1417655 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910848 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 910848 # number of WriteReq MSHR hits +system.cpu.dcache.avg_blocked_cycles::no_targets 8.057812 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 1544317 # number of writebacks +system.cpu.dcache.writebacks::total 1544317 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1422290 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1422290 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910806 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 910806 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2328503 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2328503 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2328503 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2328503 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322596 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1322596 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220723 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 220723 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1543319 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1543319 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1543330 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1543330 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27069234000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27069234000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1844364193 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1844364193 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1270000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1270000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28913598193 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28913598193 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28914868193 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28914868193 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015802 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015802 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 2333096 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2333096 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2333096 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2333096 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1324144 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1324144 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220697 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 220697 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 7 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 7 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1544841 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1544841 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1544848 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1544848 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27090401500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27090401500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1844259187 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1844259187 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 932500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 932500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28934660687 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28934660687 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28935593187 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28935593187 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015830 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015830 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002690 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002690 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000158 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000158 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009311 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.009311 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009307 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.009307 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20466.744191 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20466.744191 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8356.012708 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8356.012708 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 115454.545455 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 115454.545455 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18734.686862 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18734.686862 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18735.376227 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18735.376227 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 725912 # number of replacements -system.cpu.icache.tags.tagsinuse 511.812539 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 81490807 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 726424 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 112.180775 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 347441500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.812539 # Average occupied blocks per requestor +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000100 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000100 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009323 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.009323 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009319 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.009319 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20458.803197 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20458.803197 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8356.521326 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8356.521326 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 133214.285714 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 133214.285714 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18729.863259 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18729.863259 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18730.382010 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18730.382010 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 727442 # number of replacements +system.cpu.icache.tags.tagsinuse 511.812488 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 81555981 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 727954 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 112.034526 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 348938500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.812488 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999634 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999634 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 97 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 70 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 98 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 67 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 165175152 # Number of tag accesses -system.cpu.icache.tags.data_accesses 165175152 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 81490807 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 81490807 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 81490807 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 81490807 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 81490807 # number of overall hits -system.cpu.icache.overall_hits::total 81490807 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 733549 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 733549 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 733549 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 733549 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 733549 # number of overall misses -system.cpu.icache.overall_misses::total 733549 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 8424023442 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 8424023442 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 8424023442 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 8424023442 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 8424023442 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 8424023442 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 82224356 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 82224356 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 82224356 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 82224356 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 82224356 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 82224356 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008921 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008921 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008921 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008921 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008921 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008921 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11483.927375 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 11483.927375 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 11483.927375 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 11483.927375 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 11483.927375 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 11483.927375 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 138949 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 124 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4383 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 165310431 # Number of tag accesses +system.cpu.icache.tags.data_accesses 165310431 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 81555981 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 81555981 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 81555981 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 81555981 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 81555981 # number of overall hits +system.cpu.icache.overall_hits::total 81555981 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 735249 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 735249 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 735249 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 735249 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 735249 # number of overall misses +system.cpu.icache.overall_misses::total 735249 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8470113937 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8470113937 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8470113937 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8470113937 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8470113937 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8470113937 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 82291230 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 82291230 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 82291230 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 82291230 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 82291230 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 82291230 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008935 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008935 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008935 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008935 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008935 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008935 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11520.061825 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 11520.061825 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 11520.061825 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 11520.061825 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 11520.061825 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 11520.061825 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 144128 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 153 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4365 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 31.701802 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 41.333333 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 725912 # number of writebacks -system.cpu.icache.writebacks::total 725912 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7108 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 7108 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 7108 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 7108 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 7108 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 7108 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726441 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 726441 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 726441 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 726441 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 726441 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 726441 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7897580451 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 7897580451 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7897580451 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 7897580451 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7897580451 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 7897580451 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008835 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008835 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008835 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008835 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008835 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.008835 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10871.606161 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10871.606161 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10871.606161 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 10871.606161 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10871.606161 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 10871.606161 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 403113 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 403204 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 83 # number of redundant prefetches already in prefetch queue +system.cpu.icache.avg_blocked_cycles::no_mshrs 33.019015 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 51 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 727442 # number of writebacks +system.cpu.icache.writebacks::total 727442 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7277 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 7277 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 7277 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 7277 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 7277 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 7277 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 727972 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 727972 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 727972 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 727972 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 727972 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 727972 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7937418446 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 7937418446 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7937418446 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 7937418446 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7937418446 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 7937418446 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008846 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008846 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008846 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.008846 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008846 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.008846 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10903.466680 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10903.466680 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10903.466680 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 10903.466680 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10903.466680 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 10903.466680 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 402290 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 402345 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 51 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 28036 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.pfSpanPage 28015 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 5234.159238 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1826320 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 6292 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 290.260648 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 5251.876732 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1819467 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 6313 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 288.209568 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 5154.317005 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 79.842232 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.314595 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004873 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.319468 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 172 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 6120 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 5160.149937 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 91.726796 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.314951 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005599 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.320549 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 185 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 6128 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 12 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::2 48 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 90 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 542 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 747 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 544 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4124 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.010498 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.373535 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 70559178 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 70559178 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 968252 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 968252 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1046027 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1046027 # number of WritebackClean hits +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 101 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 547 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 740 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 550 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4130 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011292 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.374023 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 70659625 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 70659625 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 968794 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 968794 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1048519 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1048519 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 219941 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 219941 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 696850 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 696850 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1094381 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1094381 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 696850 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1314322 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2011172 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 696850 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1314322 # number of overall hits -system.cpu.l2cache.overall_hits::total 2011172 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 17 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 17 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 789 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 789 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 29509 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 29509 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 228201 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 228201 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 29509 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 228990 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 258499 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 29509 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 228990 # number of overall misses -system.cpu.l2cache.overall_misses::total 258499 # number of overall misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 219908 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 219908 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 698283 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 698283 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1095997 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1095997 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 698283 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1315905 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2014188 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 698283 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1315905 # number of overall hits +system.cpu.l2cache.overall_hits::total 2014188 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 18 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 18 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 790 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 790 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 29612 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 29612 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 228134 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 228134 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 29612 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 228924 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 258536 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 29612 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 228924 # number of overall misses +system.cpu.l2cache.overall_misses::total 258536 # number of overall misses system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 43000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 43000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 69993500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 69993500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2629297500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 2629297500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17936282000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 17936282000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 2629297500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 18006275500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20635573000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2629297500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 18006275500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20635573000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 968252 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 968252 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1046027 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1046027 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 18 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 18 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 220730 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 220730 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 726359 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 726359 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1322582 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1322582 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 726359 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1543312 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2269671 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 726359 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1543312 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2269671 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.944444 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.944444 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003575 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.003575 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.040626 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.040626 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.172542 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.172542 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.040626 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.148376 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.113893 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.040626 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.148376 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.113893 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2529.411765 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2529.411765 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88711.660330 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88711.660330 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89101.545291 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89101.545291 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78598.612627 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78598.612627 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89101.545291 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78633.457793 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79828.444211 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89101.545291 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78633.457793 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79828.444211 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70196000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 70196000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2658292500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 2658292500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17944343500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 17944343500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 2658292500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 18014539500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20672832000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 2658292500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 18014539500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20672832000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 968794 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 968794 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1048519 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1048519 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 19 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 19 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 220698 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 220698 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 727895 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 727895 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1324131 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1324131 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 727895 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1544829 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2272724 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 727895 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1544829 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2272724 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.947368 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.947368 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003580 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.003580 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.040682 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.040682 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.172290 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.172290 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.040682 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.148187 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.113756 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.040682 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.148187 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.113756 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2388.888889 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2388.888889 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88855.696203 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88855.696203 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89770.785492 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89770.785492 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78657.032709 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78657.032709 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89770.785492 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78692.227552 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79961.135006 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89770.785492 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78692.227552 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79961.135006 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 56 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 56 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 55 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 55 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 11 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 35 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 35 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 36 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 36 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 91 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 102 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 91 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 102 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 54181 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 54181 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 17 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 733 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 733 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 29498 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 29498 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 228166 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 228166 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 29498 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 228899 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 258397 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 29498 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 228899 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 54181 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 312578 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 203172843 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 203172843 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 265000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 265000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63769500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63769500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2451726000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2451726000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16564497500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16564497500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2451726000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16628267000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19079993000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2451726000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16628267000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 203172843 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19283165843 # number of overall MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 54077 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 54077 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 18 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 735 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 735 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 29601 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 29601 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 228098 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 228098 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 29601 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 228833 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 258434 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 29601 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 228833 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 54077 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 312511 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 203156315 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 203156315 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 279000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 279000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 64169000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 64169000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2480103000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2480103000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16573484500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16573484500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2480103000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16637653500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19117756500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2480103000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16637653500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 203156315 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19320912815 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.944444 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.944444 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003321 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003321 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040611 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040611 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172516 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172516 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040611 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148317 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.113848 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040611 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148317 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947368 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947368 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003330 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003330 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040667 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040667 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172262 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172262 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040667 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148128 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.113711 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040667 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148128 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.137720 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3749.890977 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3749.890977 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15588.235294 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15588.235294 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86997.953615 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86997.953615 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 83114.990847 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83114.990847 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72598.448060 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72598.448060 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83114.990847 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72644.559391 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73839.839472 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83114.990847 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72644.559391 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3749.890977 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61690.732691 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4538483 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268732 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254880 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 51558 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51557 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.137505 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3756.797067 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3756.797067 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87304.761905 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87304.761905 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 83784.432958 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83784.432958 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72659.490658 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72659.490658 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83784.432958 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72706.530527 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73975.392170 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83784.432958 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72706.530527 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3756.797067 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61824.744777 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4544579 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2271779 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254895 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 51433 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51432 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2049022 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 968252 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1300460 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 55547 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 18 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 18 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 220730 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 220730 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 726441 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322582 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2178711 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629460 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6808171 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92945280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197511168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 290456448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 55629 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5248 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2325318 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.131791 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.338265 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 2052102 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 968794 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1302965 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 55467 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 19 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 19 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 220698 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 220698 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 727972 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1324131 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2183308 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4634013 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6817321 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93141504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197705344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 290846848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 55544 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4928 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2328287 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.131576 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.338031 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2018862 86.82% 86.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 306455 13.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2021941 86.84% 86.84% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 306345 13.16% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2325318 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4537953500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 3.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1089727365 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2328287 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4544048500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 3.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1092026360 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2314999455 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2317274956 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 261037 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 253739 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 261096 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 253777 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 260286 # Transaction distribution -system.membus.trans_dist::UpgradeReq 17 # Transaction distribution -system.membus.trans_dist::ReadExReq 733 # Transaction distribution -system.membus.trans_dist::ReadExResp 733 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 260287 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 522056 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16705216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 16705216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 260342 # Transaction distribution +system.membus.trans_dist::UpgradeReq 18 # Transaction distribution +system.membus.trans_dist::ReadExReq 735 # Transaction distribution +system.membus.trans_dist::ReadExResp 735 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 260343 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522173 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 522173 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16708928 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 16708928 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 261037 # Request fanout histogram +system.membus.snoop_fanout::samples 261096 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 261037 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 261096 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 261037 # Request fanout histogram -system.membus.reqLayer0.occupancy 316168930 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 261096 # Request fanout histogram +system.membus.reqLayer0.occupancy 316188421 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1389509080 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1389693354 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 7545f6451..06d9deeed 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,96 +1,96 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.525654 # Number of seconds simulated -sim_ticks 525654485500 # Number of ticks simulated -final_tick 525654485500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.525648 # Number of seconds simulated +sim_ticks 525647850500 # Number of ticks simulated +final_tick 525647850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 282925 # Simulator instruction rate (inst/s) -host_op_rate 348318 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 232138645 # Simulator tick rate (ticks/s) -host_mem_usage 279272 # Number of bytes of host memory used -host_seconds 2264.40 # Real time elapsed on the host +host_inst_rate 304424 # Simulator instruction rate (inst/s) +host_op_rate 374786 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 249775392 # Simulator tick rate (ticks/s) +host_mem_usage 281156 # Number of bytes of host memory used +host_seconds 2104.48 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 164160 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 164544 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 18474496 # Number of bytes read from this memory -system.physmem.bytes_read::total 18638656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 164160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 164160 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 18639040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 164544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 164544 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2565 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2571 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 288664 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291229 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291235 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 312296 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35145702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 35457999 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 312296 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 312296 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8047628 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8047628 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8047628 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 312296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35145702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 43505627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291229 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 313031 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35146146 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 35459177 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 313031 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 313031 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8047730 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8047730 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8047730 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 313031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35146146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 43506907 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291235 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 291229 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 291235 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18617024 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21632 # Total number of bytes read from write queue -system.physmem.bytesWritten 4229248 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18638656 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18619136 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19904 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228224 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18639040 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 338 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 311 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18281 # Per bank write bursts -system.physmem.perBankRdBursts::1 18133 # Per bank write bursts -system.physmem.perBankRdBursts::2 18221 # Per bank write bursts -system.physmem.perBankRdBursts::3 18176 # Per bank write bursts -system.physmem.perBankRdBursts::4 18285 # Per bank write bursts -system.physmem.perBankRdBursts::5 18412 # Per bank write bursts -system.physmem.perBankRdBursts::6 18178 # Per bank write bursts +system.physmem.perBankRdBursts::0 18288 # Per bank write bursts +system.physmem.perBankRdBursts::1 18134 # Per bank write bursts +system.physmem.perBankRdBursts::2 18217 # Per bank write bursts +system.physmem.perBankRdBursts::3 18185 # Per bank write bursts +system.physmem.perBankRdBursts::4 18292 # Per bank write bursts +system.physmem.perBankRdBursts::5 18424 # Per bank write bursts +system.physmem.perBankRdBursts::6 18179 # Per bank write bursts system.physmem.perBankRdBursts::7 17990 # Per bank write bursts -system.physmem.perBankRdBursts::8 18034 # Per bank write bursts -system.physmem.perBankRdBursts::9 18056 # Per bank write bursts -system.physmem.perBankRdBursts::10 18101 # Per bank write bursts -system.physmem.perBankRdBursts::11 18200 # Per bank write bursts -system.physmem.perBankRdBursts::12 18218 # Per bank write bursts -system.physmem.perBankRdBursts::13 18271 # Per bank write bursts -system.physmem.perBankRdBursts::14 18077 # Per bank write bursts -system.physmem.perBankRdBursts::15 18258 # Per bank write bursts +system.physmem.perBankRdBursts::8 18031 # Per bank write bursts +system.physmem.perBankRdBursts::9 18051 # Per bank write bursts +system.physmem.perBankRdBursts::10 18108 # Per bank write bursts +system.physmem.perBankRdBursts::11 18204 # Per bank write bursts +system.physmem.perBankRdBursts::12 18211 # Per bank write bursts +system.physmem.perBankRdBursts::13 18269 # Per bank write bursts +system.physmem.perBankRdBursts::14 18079 # Per bank write bursts +system.physmem.perBankRdBursts::15 18262 # Per bank write bursts system.physmem.perBankWrBursts::0 4171 # Per bank write bursts system.physmem.perBankWrBursts::1 4099 # Per bank write bursts -system.physmem.perBankWrBursts::2 4135 # Per bank write bursts +system.physmem.perBankWrBursts::2 4134 # Per bank write bursts system.physmem.perBankWrBursts::3 4146 # Per bank write bursts -system.physmem.perBankWrBursts::4 4224 # Per bank write bursts +system.physmem.perBankWrBursts::4 4223 # Per bank write bursts system.physmem.perBankWrBursts::5 4224 # Per bank write bursts -system.physmem.perBankWrBursts::6 4174 # Per bank write bursts +system.physmem.perBankWrBursts::6 4173 # Per bank write bursts system.physmem.perBankWrBursts::7 4094 # Per bank write bursts -system.physmem.perBankWrBursts::8 4096 # Per bank write bursts -system.physmem.perBankWrBursts::9 4096 # Per bank write bursts +system.physmem.perBankWrBursts::8 4093 # Per bank write bursts +system.physmem.perBankWrBursts::9 4093 # Per bank write bursts system.physmem.perBankWrBursts::10 4096 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4096 # Per bank write bursts -system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4140 # Per bank write bursts +system.physmem.perBankWrBursts::12 4095 # Per bank write bursts +system.physmem.perBankWrBursts::13 4095 # Per bank write bursts +system.physmem.perBankWrBursts::14 4095 # Per bank write bursts +system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 525654384500 # Total gap between requests +system.physmem.totGap 525647749500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291229 # Read request sizes (log2) +system.physmem.readPktSize::6 291235 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -98,9 +98,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -146,23 +146,23 @@ system.physmem.wrQLenPdf::12 1 # Wh system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4018 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4019 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4019 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4019 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4019 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 4019 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 4019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4020 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 4020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4021 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 4020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4018 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -194,43 +194,43 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 102767 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 222.307005 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 147.372317 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 261.848294 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 36138 35.16% 35.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 41898 40.77% 75.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13163 12.81% 88.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1012 0.98% 89.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 489 0.48% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1030 1.00% 91.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 399 0.39% 91.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 484 0.47% 92.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8154 7.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 102767 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4019 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.497387 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.151985 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 506.429034 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4017 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 102644 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 222.570282 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 147.559533 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 262.016403 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 36015 35.09% 35.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 41909 40.83% 75.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13148 12.81% 88.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1006 0.98% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 491 0.48% 90.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1034 1.01% 91.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 399 0.39% 91.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 481 0.47% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8161 7.95% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 102644 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4018 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.515182 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.167653 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 506.604541 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4016 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4019 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4019 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.442399 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.422334 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.830212 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3130 77.88% 77.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 889 22.12% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4019 # Writes before turning the bus around for reads -system.physmem.totQLat 15538679500 # Total ticks spent queuing -system.physmem.totMemAccLat 20992885750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1454455000 # Total ticks spent in databus transfers -system.physmem.avgQLat 53417.53 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4018 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4018 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.442509 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.422441 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.830286 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3129 77.87% 77.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 889 22.13% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4018 # Writes before turning the bus around for reads +system.physmem.totQLat 15528676000 # Total ticks spent queuing +system.physmem.totMemAccLat 20983501000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1454620000 # Total ticks spent in databus transfers +system.physmem.avgQLat 53377.09 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 72167.53 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 72127.09 # Average memory access latency per DRAM burst system.physmem.avgRdBW 35.42 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 8.05 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 8.04 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 35.46 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 8.05 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s @@ -238,67 +238,67 @@ system.physmem.busUtil 0.34 # Da system.physmem.busUtilRead 0.28 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.65 # Average write queue length when enqueuing -system.physmem.readRowHits 202495 # Number of row buffer hits during reads -system.physmem.writeRowHits 51707 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.23 # Row buffer hit rate for writes -system.physmem.avgGap 1471073.79 # Average gap between requests -system.physmem.pageHitRate 71.21 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 367124520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 195116130 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1040126640 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 173653740 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 28870255440.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 8266537290 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1634065440 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 57360982710 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 51276223200 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 64953258915 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 214157919585 # Total energy per rank (pJ) -system.physmem_0.averagePower 407.411950 # Core power per rank (mW) -system.physmem_0.totalIdleTime 503225172750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 3206676000 # Time in different power states -system.physmem_0.memoryStateTime::REF 12282762000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 243901523000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 133531907000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 6939814000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 125791803500 # Time in different power states -system.physmem_1.actEnergy 366660420 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 194884635 # Energy for precharge commands per rank (pJ) +system.physmem.avgWrQLen 28.92 # Average write queue length when enqueuing +system.physmem.readRowHits 202546 # Number of row buffer hits during reads +system.physmem.writeRowHits 51789 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.35 # Row buffer hit rate for writes +system.physmem.avgGap 1471030.52 # Average gap between requests +system.physmem.pageHitRate 71.24 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 366410520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 194736630 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1040362260 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 173638080 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 28886236080.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 8300918550 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1634993280 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 57345491820 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 51305938080 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 64928910000 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 214198815120 # Total energy per rank (pJ) +system.physmem_0.averagePower 407.494892 # Core power per rank (mW) +system.physmem_0.totalIdleTime 503139346250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3209706000 # Time in different power states +system.physmem_0.memoryStateTime::REF 12289528000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 243772297750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 133609273250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7009209500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 125757836000 # Time in different power states +system.physmem_1.actEnergy 366546180 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 194797350 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1036835100 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 171294300 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 28737493200.000008 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 8178131430 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1630074720 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 56926536120 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 51134645280 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 65306601210 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 213703234155 # Total energy per rank (pJ) -system.physmem_1.averagePower 406.546781 # Core power per rank (mW) -system.physmem_1.totalIdleTime 503430400500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3200172000 # Time in different power states -system.physmem_1.memoryStateTime::REF 12226116000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 245428473250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 133163073250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 6797797000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 124838854000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 147261657 # Number of BP lookups -system.cpu.branchPred.condPredicted 98231058 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1384734 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 89949365 # Number of BTB lookups -system.cpu.branchPred.BTBHits 63294627 # Number of BTB hits +system.physmem_1.writeEnergy 171226440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 28725815040.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 8187694890 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1628706720 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 56919000150 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 51113801760 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 65311053315 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 213675530385 # Total energy per rank (pJ) +system.physmem_1.averagePower 406.499389 # Core power per rank (mW) +system.physmem_1.totalIdleTime 503405920500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3197022000 # Time in different power states +system.physmem_1.memoryStateTime::REF 12221338000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 245475081750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 133108808000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 6823284750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 124822316000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 147257105 # Number of BP lookups +system.cpu.branchPred.condPredicted 98226689 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1384794 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 89640439 # Number of BTB lookups +system.cpu.branchPred.BTBHits 63297158 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.366953 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19276105 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1312 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 15995155 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 15988941 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 6214 # Number of indirect misses. +system.cpu.branchPred.BTBHitPct 70.612280 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19276056 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1321 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 15995188 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 15989428 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5760 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 1280093 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -328,7 +328,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -358,7 +358,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -388,7 +388,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -419,16 +419,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 525654485500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1051308971 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 525647850500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1051295701 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 640655085 # Number of instructions committed system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed -system.cpu.discardedOps 8621767 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 8620171 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.640991 # CPI: cycles per instruction -system.cpu.ipc 0.609388 # IPC: instructions per cycle +system.cpu.cpi 1.640970 # CPI: cycles per instruction +system.cpu.ipc 0.609396 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 385757467 48.91% 48.91% # Class of committed instruction system.cpu.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction @@ -468,30 +468,30 @@ system.cpu.op_class_0::FloatMemWrite 3830674 0.49% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 788730744 # Class of committed instruction -system.cpu.tickCycles 955911046 # Number of cycles that the object actually ticked -system.cpu.idleCycles 95397925 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 955914808 # Number of cycles that the object actually ticked +system.cpu.idleCycles 95380893 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 778100 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.108689 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 378449407 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4092.107040 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 378447440 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782196 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 483.829382 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 850386500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.108689 # Average occupied blocks per requestor +system.cpu.dcache.tags.avg_refs 483.826867 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 850680500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.107040 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999050 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999050 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 970 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 969 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1388 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1537 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 759383100 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 759383100 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 249620680 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 249620680 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 759379166 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 759379166 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 249618713 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 249618713 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3484 # number of SoftPFReq hits @@ -500,10 +500,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 378434445 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 378434445 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 378437929 # number of overall hits -system.cpu.dcache.overall_hits::total 378437929 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 378432478 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 378432478 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 378435962 # number of overall hits +system.cpu.dcache.overall_hits::total 378435962 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 713192 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 713192 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses @@ -514,16 +514,16 @@ system.cpu.dcache.demand_misses::cpu.data 850904 # n system.cpu.dcache.demand_misses::total 850904 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 851045 # number of overall misses system.cpu.dcache.overall_misses::total 851045 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 37269485500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37269485500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10946218000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10946218000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 48215703500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 48215703500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 48215703500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 48215703500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250333872 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250333872 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 37264745000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37264745000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10940214000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10940214000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 48204959000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 48204959000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 48204959000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 48204959000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250331905 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250331905 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3625 # number of SoftPFReq accesses(hits+misses) @@ -532,10 +532,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 379285349 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 379285349 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 379288974 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 379288974 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 379283382 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 379283382 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 379287007 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 379287007 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002849 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002849 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses @@ -546,22 +546,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002243 system.cpu.dcache.demand_miss_rate::total 0.002243 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002244 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002244 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52257.296072 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 52257.296072 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79486.304752 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 79486.304752 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56664.093129 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56664.093129 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56654.705098 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56654.705098 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52250.649194 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 52250.649194 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79442.706518 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 79442.706518 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56651.465970 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56651.465970 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56642.080031 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56642.080031 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88688 # number of writebacks -system.cpu.dcache.writebacks::total 88688 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88684 # number of writebacks +system.cpu.dcache.writebacks::total 88684 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 457 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 457 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits @@ -580,16 +580,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782057 system.cpu.dcache.demand_mshr_misses::total 782057 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782196 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782196 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36547770500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36547770500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5489520000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5489520000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36543095500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36543095500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5486426000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5486426000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1802000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1802000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42037290500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 42037290500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42039092500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 42039092500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42029521500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 42029521500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42031323500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 42031323500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -600,206 +600,206 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51278.203680 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51278.203680 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79188.713540 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79188.713540 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51271.644440 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51271.644440 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79144.081244 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79144.081244 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12964.028777 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12964.028777 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53752.207959 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53752.207959 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53744.959703 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53744.959703 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 24885 # number of replacements -system.cpu.icache.tags.tagsinuse 1711.889727 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 257789639 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 26636 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 9678.241440 # Average number of references to valid blocks. +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53742.273901 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53742.273901 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53735.027410 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53735.027410 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 24889 # number of replacements +system.cpu.icache.tags.tagsinuse 1710.890314 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 257795451 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 26639 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 9677.369684 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1711.889727 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.835884 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.835884 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1596 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 515659188 # Number of tag accesses -system.cpu.icache.tags.data_accesses 515659188 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 257789639 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 257789639 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 257789639 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 257789639 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 257789639 # number of overall hits -system.cpu.icache.overall_hits::total 257789639 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 26637 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 26637 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 26637 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 26637 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 26637 # number of overall misses -system.cpu.icache.overall_misses::total 26637 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 539890500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 539890500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 539890500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 539890500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 539890500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 539890500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 257816276 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 257816276 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 257816276 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 257816276 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 257816276 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 257816276 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1710.890314 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.835396 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.835396 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1750 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1598 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.854492 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 515670821 # Number of tag accesses +system.cpu.icache.tags.data_accesses 515670821 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 257795451 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 257795451 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 257795451 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 257795451 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 257795451 # number of overall hits +system.cpu.icache.overall_hits::total 257795451 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 26640 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 26640 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 26640 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 26640 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 26640 # number of overall misses +system.cpu.icache.overall_misses::total 26640 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 538801500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 538801500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 538801500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 538801500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 538801500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 538801500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 257822091 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 257822091 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 257822091 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 257822091 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 257822091 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 257822091 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000103 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000103 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000103 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000103 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000103 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000103 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20268.442392 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20268.442392 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20268.442392 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20268.442392 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20268.442392 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20268.442392 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20225.281532 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20225.281532 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20225.281532 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20225.281532 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20225.281532 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20225.281532 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 24885 # number of writebacks -system.cpu.icache.writebacks::total 24885 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 26637 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 26637 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 26637 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 26637 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 26637 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 26637 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 513254500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 513254500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 513254500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 513254500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 513254500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 513254500 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 24889 # number of writebacks +system.cpu.icache.writebacks::total 24889 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 26640 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 26640 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 26640 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 26640 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 26640 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 26640 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 512162500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 512162500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 512162500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 512162500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 512162500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 512162500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000103 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000103 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000103 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19268.479934 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19268.479934 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19268.479934 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19268.479934 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19268.479934 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19268.479934 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 258837 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32651.524409 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1316948 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 291605 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.516205 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 3958369000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 41.514151 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.268254 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32520.742004 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.001267 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002724 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.992454 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996445 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19225.319069 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19225.319069 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19225.319069 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19225.319069 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19225.319069 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19225.319069 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 258839 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32651.545544 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1316953 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 291607 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.516191 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 3958663000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 40.523746 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.271478 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 32520.750321 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.001237 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002755 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.992455 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996446 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 300 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2912 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29221 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29227 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 13160277 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 13160277 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 88688 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88688 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 23552 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 23552 # number of WritebackClean hits +system.cpu.l2cache.tags.tag_accesses 13160335 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 13160335 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 88684 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 88684 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 23557 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 23557 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24067 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 24067 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24064 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 24064 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490275 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 490275 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 24067 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 24064 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 493506 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 517573 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 24067 # number of overall hits +system.cpu.l2cache.demand_hits::total 517570 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 24064 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 493506 # number of overall hits -system.cpu.l2cache.overall_hits::total 517573 # number of overall hits +system.cpu.l2cache.overall_hits::total 517570 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 66091 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2570 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2570 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2576 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2576 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222599 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 222599 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2570 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 2576 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 288690 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 291260 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2570 # number of overall misses +system.cpu.l2cache.demand_misses::total 291266 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2576 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 288690 # number of overall misses -system.cpu.l2cache.overall_misses::total 291260 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5351609000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5351609000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 219318000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 219318000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30330402000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 30330402000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 219318000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 35682011000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35901329000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 219318000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 35682011000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35901329000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88688 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88688 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 23552 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 23552 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 291266 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5348515000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5348515000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 218253000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 218253000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30325726000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 30325726000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 218253000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 35674241000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 35892494000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 218253000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 35674241000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 35892494000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 88684 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 88684 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 23557 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 23557 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 26637 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 26637 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 26640 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 26640 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712874 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 712874 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 26637 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 26640 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 782196 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 808833 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 26637 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 808836 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 26640 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 782196 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 808833 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 808836 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.096482 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.096482 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.096697 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.096697 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312256 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312256 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.096482 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.096697 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.369076 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.360099 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096482 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.360105 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096697 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.369076 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.360099 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80973.339789 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80973.339789 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85337.743191 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85337.743191 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 136255.787313 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 136255.787313 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85337.743191 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 123599.747134 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 123262.133489 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85337.743191 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 123599.747134 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 123262.133489 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.360105 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80926.525548 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80926.525548 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84725.543478 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84725.543478 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 136234.780929 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 136234.780929 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84725.543478 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 123572.832450 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 123229.261225 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84725.543478 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 123572.832450 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 123229.261225 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -820,124 +820,124 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 26 system.cpu.l2cache.overall_mshr_hits::total 30 # number of overall MSHR hits system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2566 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2566 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2572 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2572 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222573 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222573 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2566 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2572 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 288664 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291230 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2566 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291236 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2572 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 288664 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291230 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4690699000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4690699000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 193386000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 193386000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28102659500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28102659500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 193386000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32793358500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 32986744500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 193386000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32793358500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 32986744500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 291236 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4687605000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4687605000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 192261000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 192261000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28098015500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28098015500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192261000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32785620500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 32977881500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192261000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32785620500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 32977881500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096332 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096547 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096547 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312219 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312219 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096547 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.360062 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.360068 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096547 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.360062 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70973.339789 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70973.339789 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75364.770070 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75364.770070 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 126262.662138 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 126262.662138 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75364.770070 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 113603.908004 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 113266.986574 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75364.770070 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 113603.908004 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 113266.986574 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1611818 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 803044 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.360068 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70926.525548 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70926.525548 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74751.555210 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74751.555210 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 126241.797073 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 126241.797073 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74751.555210 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 113577.101752 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 113234.220701 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74751.555210 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 113577.101752 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 113234.220701 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1611825 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 803048 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2036 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2021 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2033 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2018 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 739510 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 154786 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 24885 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 882151 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 739513 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 154782 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 24889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 882157 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 26637 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 26640 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 712874 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 78158 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 78168 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342492 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2420650 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3297344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55736576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 59033920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 258837 # Total snoops (count) +system.cpu.toL2Bus.pkt_count::total 2420660 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3297792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55736320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 59034112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 258839 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 4230272 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1067670 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.005005 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.070770 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1067675 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.005002 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.070750 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1062341 99.50% 99.50% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5314 0.50% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1062349 99.50% 99.50% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5311 0.50% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1067670 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 919482000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1067675 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 919485500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 39955996 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 39960496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1173306974 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 548029 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 256840 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 548040 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 256844 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 225138 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 225144 # Transaction distribution system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution -system.membus.trans_dist::CleanEvict 190702 # Transaction distribution +system.membus.trans_dist::CleanEvict 190707 # Transaction distribution system.membus.trans_dist::ReadExReq 66091 # Transaction distribution system.membus.trans_dist::ReadExResp 66091 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225138 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839258 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 839258 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22868928 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22868928 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225144 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839275 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 839275 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22869312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22869312 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 291229 # Request fanout histogram +system.membus.snoop_fanout::samples 291235 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 291229 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 291235 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 291229 # Request fanout histogram -system.membus.reqLayer0.occupancy 917205000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 291235 # Request fanout histogram +system.membus.reqLayer0.occupancy 917214500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1553500250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1553534250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index bcc6de449..1f99db17b 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.338999 # Number of seconds simulated -sim_ticks 338998876000 # Number of ticks simulated -final_tick 338998876000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.339069 # Number of seconds simulated +sim_ticks 339069355000 # Number of ticks simulated +final_tick 339069355000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 210128 # Simulator instruction rate (inst/s) -host_op_rate 258696 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 111189218 # Simulator tick rate (ticks/s) -host_mem_usage 277020 # Number of bytes of host memory used -host_seconds 3048.85 # Real time elapsed on the host +host_inst_rate 212003 # Simulator instruction rate (inst/s) +host_op_rate 261004 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 112204360 # Simulator tick rate (ticks/s) +host_mem_usage 277184 # Number of bytes of host memory used +host_seconds 3021.89 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 268928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 48012032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12961152 # Number of bytes read from this memory -system.physmem.bytes_read::total 61242112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 268928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 268928 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4244288 # Number of bytes written to this memory -system.physmem.bytes_written::total 4244288 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4202 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 750188 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 202518 # Number of read requests responded to by this memory -system.physmem.num_reads::total 956908 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66317 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66317 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 793301 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 141628883 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 38233613 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 180655797 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 793301 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 793301 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 12520065 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 12520065 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 12520065 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 793301 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 141628883 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 38233613 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 193175862 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 956909 # Number of read requests accepted -system.physmem.writeReqs 66317 # Number of write requests accepted -system.physmem.readBursts 956909 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66317 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61223936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18240 # Total number of bytes read from write queue -system.physmem.bytesWritten 4238080 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 61242176 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4244288 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 285 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 65 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 272000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 48065856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12979392 # Number of bytes read from this memory +system.physmem.bytes_read::total 61317248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 272000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 272000 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4246400 # Number of bytes written to this memory +system.physmem.bytes_written::total 4246400 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4250 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 751029 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 202803 # Number of read requests responded to by this memory +system.physmem.num_reads::total 958082 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66350 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66350 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 802196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 141758184 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 38279461 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 180839840 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 802196 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 802196 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 12523692 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 12523692 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 12523692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 802196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 141758184 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 38279461 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 193363532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 958083 # Number of read requests accepted +system.physmem.writeReqs 66350 # Number of write requests accepted +system.physmem.readBursts 958083 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66350 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 61296960 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20352 # Total number of bytes read from write queue +system.physmem.bytesWritten 4240000 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 61317312 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4246400 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 318 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 71 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19928 # Per bank write bursts -system.physmem.perBankRdBursts::1 19580 # Per bank write bursts -system.physmem.perBankRdBursts::2 657267 # Per bank write bursts -system.physmem.perBankRdBursts::3 20958 # Per bank write bursts -system.physmem.perBankRdBursts::4 19729 # Per bank write bursts -system.physmem.perBankRdBursts::5 20737 # Per bank write bursts -system.physmem.perBankRdBursts::6 19560 # Per bank write bursts -system.physmem.perBankRdBursts::7 19988 # Per bank write bursts -system.physmem.perBankRdBursts::8 19522 # Per bank write bursts -system.physmem.perBankRdBursts::9 20089 # Per bank write bursts -system.physmem.perBankRdBursts::10 19525 # Per bank write bursts -system.physmem.perBankRdBursts::11 19708 # Per bank write bursts -system.physmem.perBankRdBursts::12 19661 # Per bank write bursts -system.physmem.perBankRdBursts::13 21032 # Per bank write bursts -system.physmem.perBankRdBursts::14 19553 # Per bank write bursts -system.physmem.perBankRdBursts::15 19787 # Per bank write bursts -system.physmem.perBankWrBursts::0 4255 # Per bank write bursts -system.physmem.perBankWrBursts::1 4105 # Per bank write bursts -system.physmem.perBankWrBursts::2 4143 # Per bank write bursts -system.physmem.perBankWrBursts::3 4152 # Per bank write bursts -system.physmem.perBankWrBursts::4 4244 # Per bank write bursts -system.physmem.perBankWrBursts::5 4226 # Per bank write bursts +system.physmem.perBankRdBursts::0 19910 # Per bank write bursts +system.physmem.perBankRdBursts::1 19573 # Per bank write bursts +system.physmem.perBankRdBursts::2 657828 # Per bank write bursts +system.physmem.perBankRdBursts::3 21032 # Per bank write bursts +system.physmem.perBankRdBursts::4 19718 # Per bank write bursts +system.physmem.perBankRdBursts::5 21045 # Per bank write bursts +system.physmem.perBankRdBursts::6 19700 # Per bank write bursts +system.physmem.perBankRdBursts::7 20038 # Per bank write bursts +system.physmem.perBankRdBursts::8 19491 # Per bank write bursts +system.physmem.perBankRdBursts::9 20101 # Per bank write bursts +system.physmem.perBankRdBursts::10 19540 # Per bank write bursts +system.physmem.perBankRdBursts::11 19692 # Per bank write bursts +system.physmem.perBankRdBursts::12 19618 # Per bank write bursts +system.physmem.perBankRdBursts::13 21105 # Per bank write bursts +system.physmem.perBankRdBursts::14 19493 # Per bank write bursts +system.physmem.perBankRdBursts::15 19881 # Per bank write bursts +system.physmem.perBankWrBursts::0 4272 # Per bank write bursts +system.physmem.perBankWrBursts::1 4107 # Per bank write bursts +system.physmem.perBankWrBursts::2 4147 # Per bank write bursts +system.physmem.perBankWrBursts::3 4153 # Per bank write bursts +system.physmem.perBankWrBursts::4 4251 # Per bank write bursts +system.physmem.perBankWrBursts::5 4229 # Per bank write bursts system.physmem.perBankWrBursts::6 4174 # Per bank write bursts system.physmem.perBankWrBursts::7 4096 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts -system.physmem.perBankWrBursts::9 4096 # Per bank write bursts -system.physmem.perBankWrBursts::10 4096 # Per bank write bursts +system.physmem.perBankWrBursts::9 4095 # Per bank write bursts +system.physmem.perBankWrBursts::10 4095 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4097 # Per bank write bursts -system.physmem.perBankWrBursts::13 4095 # Per bank write bursts -system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4152 # Per bank write bursts +system.physmem.perBankWrBursts::12 4098 # Per bank write bursts +system.physmem.perBankWrBursts::13 4094 # Per bank write bursts +system.physmem.perBankWrBursts::14 4095 # Per bank write bursts +system.physmem.perBankWrBursts::15 4151 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 338998865500 # Total gap between requests +system.physmem.totGap 339069344500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 956909 # Read request sizes (log2) +system.physmem.readPktSize::6 958083 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66317 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 764114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7783 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 9162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 10166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 6863 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3709 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1088 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 644 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66350 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 765133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 120601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6690 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7738 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 9158 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 10207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 6741 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3672 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1581 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -149,47 +149,47 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 553 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5885 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 22 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see @@ -198,134 +198,137 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 195260 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 335.246789 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 192.210032 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 355.737014 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 64653 33.11% 33.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 60691 31.08% 64.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15519 7.95% 72.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3195 1.64% 73.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3493 1.79% 75.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2388 1.22% 76.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2513 1.29% 78.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 34304 17.57% 95.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8504 4.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 195260 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3991 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 173.742922 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 35.179059 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1709.732000 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 3971 99.50% 99.50% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 9 0.23% 99.72% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-12287 3 0.08% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-16383 3 0.08% 99.87% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16384-20479 1 0.03% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-28671 1 0.03% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::36864-40959 1 0.03% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-49151 1 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::73728-77823 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3991 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3991 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.592333 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.512127 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.873555 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3350 83.94% 83.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 21 0.53% 84.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 395 9.90% 94.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 55 1.38% 95.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 24 0.60% 96.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 19 0.48% 96.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 17 0.43% 97.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 26 0.65% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 20 0.50% 98.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 16 0.40% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 9 0.23% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 11 0.28% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 7 0.18% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 5 0.13% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 4 0.10% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 6 0.15% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.03% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 3 0.08% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3991 # Writes before turning the bus around for reads -system.physmem.totQLat 27417238749 # Total ticks spent queuing -system.physmem.totMemAccLat 45353938749 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4783120000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28660.41 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 196319 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 333.816859 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 191.183939 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 355.380336 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 65406 33.32% 33.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 61086 31.12% 64.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15476 7.88% 72.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3179 1.62% 73.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3479 1.77% 75.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2336 1.19% 76.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2511 1.28% 78.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 34323 17.48% 95.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8523 4.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 196319 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4003 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 214.941294 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 35.155298 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2727.024521 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 3978 99.38% 99.38% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 12 0.30% 99.68% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-12287 3 0.07% 99.75% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-16383 4 0.10% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-20479 1 0.02% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32768-36863 1 0.02% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::36864-40959 1 0.02% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::69632-73727 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::126976-131071 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4003 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4003 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.550087 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.475287 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.816460 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3400 84.94% 84.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 19 0.47% 85.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 373 9.32% 94.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 54 1.35% 96.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 20 0.50% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 27 0.67% 97.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 15 0.37% 97.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 21 0.52% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 14 0.35% 98.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 14 0.35% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 14 0.35% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 6 0.15% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 7 0.17% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 6 0.15% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.02% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 3 0.07% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 4 0.10% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 2 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4003 # Writes before turning the bus around for reads +system.physmem.totQLat 27518767878 # Total ticks spent queuing +system.physmem.totMemAccLat 45476861628 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4788825000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28732.28 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47410.41 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 180.60 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 47482.28 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 180.78 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 12.50 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 180.66 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 180.84 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 12.52 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.51 # Data bus utilization in percentage system.physmem.busUtilRead 1.41 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.10 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.35 # Average write queue length when enqueuing -system.physmem.readRowHits 804753 # Number of row buffer hits during reads -system.physmem.writeRowHits 22823 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.12 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 34.45 # Row buffer hit rate for writes -system.physmem.avgGap 331304.00 # Average gap between requests -system.physmem.pageHitRate 80.91 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 893206860 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 474750705 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5695906440 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 174321900 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 27330582240.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 14459296590 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 677245920 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 138340780680 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 698740320 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 673162065.000000 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 189465949500 # Total energy per rank (pJ) -system.physmem_0.averagePower 558.898453 # Core power per rank (mW) -system.physmem_0.totalIdleTime 305423895331 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 532417778 # Time in different power states -system.physmem_0.memoryStateTime::REF 11568510000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 220427000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 1819753036 # Time in different power states -system.physmem_0.memoryStateTime::ACT 21474052891 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 303383715295 # Time in different power states -system.physmem_1.actEnergy 500999520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 266260995 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1134381780 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 171346500 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 25447939920.000004 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 7069016310 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1362680640 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 70550856240 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 31070458080 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 25392894210 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 162967325295 # Total energy per rank (pJ) -system.physmem_1.averagePower 480.731167 # Core power per rank (mW) -system.physmem_1.totalIdleTime 319946801176 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 2603762514 # Time in different power states -system.physmem_1.memoryStateTime::REF 10820898000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 84317463250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 80912710040 # Time in different power states -system.physmem_1.memoryStateTime::ACT 5627391560 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 154716650636 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 174659469 # Number of BP lookups -system.cpu.branchPred.condPredicted 119114964 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4015677 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 96720579 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67753891 # Number of BTB hits +system.physmem.avgWrQLen 25.37 # Average write queue length when enqueuing +system.physmem.readRowHits 804881 # Number of row buffer hits during reads +system.physmem.writeRowHits 22802 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.04 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 34.40 # Row buffer hit rate for writes +system.physmem.avgGap 330982.45 # Average gap between requests +system.physmem.pageHitRate 80.82 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 901474980 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 479122545 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5703739020 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 174499380 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 27325665120.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 14491103160 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 673386240 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 138371323560 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 679220160 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 661319340.000000 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 189506984115 # Total energy per rank (pJ) +system.physmem_0.averagePower 558.903308 # Core power per rank (mW) +system.physmem_0.totalIdleTime 305432505529 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 523884278 # Time in different power states +system.physmem_0.memoryStateTime::REF 11566244000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 219111500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 1768844578 # Time in different power states +system.physmem_0.memoryStateTime::ACT 21546721193 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 303444549451 # Time in different power states +system.physmem_1.actEnergy 500335500 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 265908060 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1134695940 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 171325620 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 25432573920.000004 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6980276430 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1364879040 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 70621447890 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 30989177760 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 25472740305 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 162933984825 # Total energy per rank (pJ) +system.physmem_1.averagePower 480.532913 # Core power per rank (mW) +system.physmem_1.totalIdleTime 320205691246 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 2610959521 # Time in different power states +system.physmem_1.memoryStateTime::REF 10814464000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 84633345250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 80700935022 # Time in different power states +system.physmem_1.memoryStateTime::ACT 5438217483 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 154871433724 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 175312537 # Number of BP lookups +system.cpu.branchPred.condPredicted 119126010 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4023429 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 95987051 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67762694 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.051164 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18782444 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1299597 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 16716760 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 16702354 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 14406 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 1279517 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 70.595662 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18784914 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1299715 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 16714738 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 16702890 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 11848 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 1279488 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -355,7 +358,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -385,7 +388,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -415,7 +418,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -446,134 +449,134 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 338998876000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 677997753 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 678138711 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 35007390 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 824275552 # Number of instructions fetch has processed -system.cpu.fetch.Branches 174659469 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 103238689 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 638483488 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8068049 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 3174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 35026134 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 824295259 # Number of instructions fetch has processed +system.cpu.fetch.Branches 175312537 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 103250498 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 638595633 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8083491 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2728 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3169 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 247736654 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 13165 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 677531262 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.500399 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.263726 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3109 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 247757876 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 12590 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 677669366 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.498301 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.263018 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 215511441 31.81% 31.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 148279019 21.89% 53.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72933920 10.76% 64.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 240806882 35.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 215620652 31.82% 31.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 148930568 21.98% 53.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72932404 10.76% 64.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 240185742 35.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 677531262 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.257611 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.215750 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 75755548 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 258011846 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 277771746 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 61971111 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4021011 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 20808683 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13107 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 924572936 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 11806711 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4021011 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 118697379 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 157348847 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 212785 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 295131252 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 102119988 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 906539563 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6891328 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 27972681 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2218640 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 49279009 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 483149 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 980928941 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4318000809 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1001835244 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34457090 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 677669366 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258520 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.215526 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 75794919 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 258105460 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 277738151 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 62003234 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4027602 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 64856939 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 14426 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 924580293 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 10545635 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4027602 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 118744370 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 157469679 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 209680 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 295125429 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 102092606 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 906546743 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6881182 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 27980774 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2218296 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 49244088 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 491152 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 980952632 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4318034270 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1001843328 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34457465 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 106150711 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 106174402 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 6852 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6840 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 138234074 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 271880895 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 160585540 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 6163609 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 12157039 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 899825913 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12585 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 860027802 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 9216351 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 111113540 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 244391790 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 431 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 677531262 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.269355 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.103879 # Number of insts issued each cycle +system.cpu.rename.tempSerializingInsts 6837 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 138250974 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 271864033 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 160594184 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 6150346 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 12039275 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 899826395 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12582 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 860048195 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 9222152 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 111114019 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 244270336 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 428 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 677669366 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.269127 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.103925 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 215443123 31.80% 31.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 182412778 26.92% 58.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 173833847 25.66% 84.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 93421038 13.79% 98.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12418164 1.83% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2312 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 215576710 31.81% 31.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 182398349 26.92% 58.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 173866168 25.66% 84.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 93397486 13.78% 98.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12428213 1.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2440 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 677531262 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 677669366 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 66604023 24.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 18144 0.01% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 636889 0.23% 24.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 132902314 47.88% 72.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 66436214 23.93% 96.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 5673709 2.04% 98.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 5298999 1.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 66592795 23.99% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18143 0.01% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 636888 0.23% 24.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 132895197 47.87% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 66486163 23.95% 96.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 5670687 2.04% 98.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 5308776 1.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413088657 48.03% 48.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5187663 0.60% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413112342 48.03% 48.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5187450 0.60% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued @@ -596,91 +599,91 @@ system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.64% # Ty system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.07% 48.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 3187674 0.37% 49.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 2550152 0.30% 49.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.37% 49.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 2550158 0.30% 49.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478195 1.33% 50.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478201 1.33% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 259646328 30.19% 80.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 153400482 17.84% 98.74% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 7019166 0.82% 99.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 3831957 0.45% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 259635092 30.19% 80.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 153408617 17.84% 98.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 7019173 0.82% 99.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 3831959 0.45% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 860027802 # Type of FU issued -system.cpu.iq.rate 1.268482 # Inst issue rate -system.cpu.iq.fu_busy_cnt 277570292 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.322746 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2621725269 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 980329256 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 820080739 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 62648240 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 30641595 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 24878674 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1100471505 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 37126589 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 13986954 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 860048195 # Type of FU issued +system.cpu.iq.rate 1.268248 # Inst issue rate +system.cpu.iq.fu_busy_cnt 277608649 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.322783 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2621941266 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 980329396 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 820105906 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 62655291 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 30642249 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 24878687 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1100523479 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 37133365 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 13978556 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 19639957 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 122 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18816 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 31605044 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 19623095 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 150 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18653 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 31613688 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1918903 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 17949 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1918749 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 18225 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4021011 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10591594 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7946 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 899848641 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 4027602 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10592950 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5943 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 899848973 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 271880895 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 160585540 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6845 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 969 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5082 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18816 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3295133 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3290188 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6585321 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 850172394 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 263373871 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9855408 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 271864033 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 160594184 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6842 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 932 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3107 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18653 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3297561 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3294434 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6591995 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 850188945 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 263367686 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9859250 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10143 # number of nop insts executed -system.cpu.iew.exec_refs 416062863 # number of memory reference insts executed -system.cpu.iew.exec_branches 143380865 # Number of branches executed -system.cpu.iew.exec_stores 152688992 # Number of stores executed -system.cpu.iew.exec_rate 1.253946 # Inst execution rate -system.cpu.iew.wb_sent 846295545 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 844959413 # cumulative count of insts written-back -system.cpu.iew.wb_producers 486195731 # num instructions producing a value -system.cpu.iew.wb_consumers 804663900 # num instructions consuming a value -system.cpu.iew.wb_rate 1.246257 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.604222 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 103166103 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 9996 # number of nop insts executed +system.cpu.iew.exec_refs 416059985 # number of memory reference insts executed +system.cpu.iew.exec_branches 143387028 # Number of branches executed +system.cpu.iew.exec_stores 152692299 # Number of stores executed +system.cpu.iew.exec_rate 1.253710 # Inst execution rate +system.cpu.iew.wb_sent 846316526 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 844984593 # cumulative count of insts written-back +system.cpu.iew.wb_producers 486213090 # num instructions producing a value +system.cpu.iew.wb_consumers 804713496 # num instructions consuming a value +system.cpu.iew.wb_rate 1.246035 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.604206 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 103170323 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4002664 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 662950558 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.189727 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.047510 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 4009286 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 663080037 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.189495 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.047357 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 372609039 56.20% 56.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 137243840 20.70% 76.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 51342182 7.74% 84.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 28218977 4.26% 88.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 14379686 2.17% 91.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14774384 2.23% 93.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7871744 1.19% 94.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6561841 0.99% 95.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29948865 4.52% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 372743600 56.21% 56.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 137229465 20.70% 76.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51343947 7.74% 84.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 28225650 4.26% 88.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 14387181 2.17% 91.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14772519 2.23% 93.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7871150 1.19% 94.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6554658 0.99% 95.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29951867 4.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 662950558 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 663080037 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654411 # Number of instructions committed system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -730,82 +733,82 @@ system.cpu.commit.op_class_0::FloatMemWrite 3830674 0.49% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 29948865 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1524889115 # The number of ROB reads -system.cpu.rob.rob_writes 1798376442 # The number of ROB writes -system.cpu.timesIdled 10544 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 466491 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 29951867 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1525019812 # The number of ROB reads +system.cpu.rob.rob_writes 1798395927 # The number of ROB writes +system.cpu.timesIdled 10540 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 469345 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649299 # Number of Instructions Simulated system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.058298 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.058298 # CPI: Total CPI of All Threads -system.cpu.ipc 0.944914 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.944914 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 868460616 # number of integer regfile reads -system.cpu.int_regfile_writes 500698081 # number of integer regfile writes -system.cpu.fp_regfile_reads 30616065 # number of floating regfile reads -system.cpu.fp_regfile_writes 22959495 # number of floating regfile writes -system.cpu.cc_regfile_reads 3322380162 # number of cc regfile reads -system.cpu.cc_regfile_writes 369206587 # number of cc regfile writes -system.cpu.misc_regfile_reads 606831817 # number of misc regfile reads +system.cpu.cpi 1.058518 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.058518 # CPI: Total CPI of All Threads +system.cpu.ipc 0.944717 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.944717 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 868485327 # number of integer regfile reads +system.cpu.int_regfile_writes 500716513 # number of integer regfile writes +system.cpu.fp_regfile_reads 30616072 # number of floating regfile reads +system.cpu.fp_regfile_writes 22959512 # number of floating regfile writes +system.cpu.cc_regfile_reads 3322428373 # number of cc regfile reads +system.cpu.cc_regfile_writes 369236255 # number of cc regfile writes +system.cpu.misc_regfile_reads 606835918 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2756456 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.910987 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 371049565 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756968 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 134.586098 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 285993000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.910987 # Average occupied blocks per requestor +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2756526 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.910931 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 371056816 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2757038 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 134.585311 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 286323500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.910931 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999826 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999826 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 175 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 176 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 751745414 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 751745414 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 243126159 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 243126159 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127907378 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127907378 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 751754868 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 751754868 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 243133490 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 243133490 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127906319 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127906319 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 371033537 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 371033537 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 371036694 # number of overall hits -system.cpu.dcache.overall_hits::total 371036694 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2401303 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2401303 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1044099 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1044099 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 371039809 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 371039809 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 371042966 # number of overall hits +system.cpu.dcache.overall_hits::total 371042966 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2398664 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2398664 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1045158 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1045158 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3445402 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3445402 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3446049 # number of overall misses -system.cpu.dcache.overall_misses::total 3446049 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 80431299000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 80431299000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9946595850 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9946595850 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3443822 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3443822 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3444469 # number of overall misses +system.cpu.dcache.overall_misses::total 3444469 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 80554008500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 80554008500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9982772350 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9982772350 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 140000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 140000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 90377894850 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 90377894850 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 90377894850 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 90377894850 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 245527462 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 245527462 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 90536780850 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 90536780850 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 90536780850 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 90536780850 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 245532154 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 245532154 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3804 # number of SoftPFReq accesses(hits+misses) @@ -814,469 +817,470 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5741 system.cpu.dcache.LoadLockedReq_accesses::total 5741 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 374478939 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 374478939 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 374482743 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 374482743 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009780 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009780 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008097 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.008097 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 374483631 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 374483631 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 374487435 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 374487435 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009769 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009769 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008105 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.008105 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170084 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.170084 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000348 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000348 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009201 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009201 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009202 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009202 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33494.856334 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33494.856334 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9526.487287 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9526.487287 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.009196 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009196 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009198 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009198 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33582.864670 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33582.864670 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9551.448059 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9551.448059 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26231.451323 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26231.451323 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26226.526335 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26226.526335 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26289.622649 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26289.622649 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26284.684475 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26284.684475 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 336970 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 344610 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4742 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4869 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 71.060734 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2756456 # number of writebacks -system.cpu.dcache.writebacks::total 2756456 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365826 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 365826 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323069 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 323069 # number of WriteReq MSHR hits +system.cpu.dcache.avg_blocked_cycles::no_targets 70.776340 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2756526 # number of writebacks +system.cpu.dcache.writebacks::total 2756526 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 363119 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 363119 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323999 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 323999 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 688895 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 688895 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 688895 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 688895 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035477 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2035477 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721030 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 721030 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 687118 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 687118 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 687118 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 687118 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035545 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2035545 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721159 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 721159 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 642 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 642 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2756507 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2756507 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2757149 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2757149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75180323500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75180323500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5949856850 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5949856850 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5764000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5764000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 81130180350 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 81130180350 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 81135944350 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 81135944350 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2756704 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2756704 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2757346 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2757346 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75270268500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75270268500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5954605850 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5954605850 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5576500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5576500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 81224874350 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 81224874350 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 81230450850 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 81230450850 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.008290 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008290 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005591 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005591 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005592 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005592 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168770 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168770 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007361 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.007361 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007363 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.007363 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36934.990422 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36934.990422 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8251.885289 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8251.885289 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8978.193146 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8978.193146 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29432.241728 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29432.241728 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29427.479019 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29427.479019 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1980154 # number of replacements -system.cpu.icache.tags.tagsinuse 511.083769 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 245752724 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1980664 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 124.075928 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 275035500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.083769 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998210 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998210 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36977.943745 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36977.943745 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8256.994435 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8256.994435 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8686.137072 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8686.137072 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29464.488879 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29464.488879 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29459.651001 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29459.651001 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1980658 # number of replacements +system.cpu.icache.tags.tagsinuse 510.043873 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 245773558 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1981168 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 124.054880 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 275783500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.043873 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996179 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996179 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 112 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 334 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 497454087 # Number of tag accesses -system.cpu.icache.tags.data_accesses 497454087 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 245752746 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 245752746 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 245752746 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 245752746 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 245752746 # number of overall hits -system.cpu.icache.overall_hits::total 245752746 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1983875 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1983875 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1983875 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1983875 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1983875 # number of overall misses -system.cpu.icache.overall_misses::total 1983875 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16221042426 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16221042426 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16221042426 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16221042426 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16221042426 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16221042426 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 247736621 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 247736621 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 247736621 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 247736621 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 247736621 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 247736621 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008008 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008008 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008008 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008008 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008008 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008008 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8176.443791 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8176.443791 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8176.443791 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8176.443791 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8176.443791 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8176.443791 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 85075 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 747 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2929 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 497497160 # Number of tag accesses +system.cpu.icache.tags.data_accesses 497497160 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 245773612 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 245773612 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 245773612 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 245773612 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 245773612 # number of overall hits +system.cpu.icache.overall_hits::total 245773612 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1984230 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1984230 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1984230 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1984230 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1984230 # number of overall misses +system.cpu.icache.overall_misses::total 1984230 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16225163428 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16225163428 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16225163428 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16225163428 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16225163428 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16225163428 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 247757842 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 247757842 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 247757842 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 247757842 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 247757842 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 247757842 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008009 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008009 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008009 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008009 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008009 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008009 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8177.057815 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8177.057815 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8177.057815 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8177.057815 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8177.057815 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8177.057815 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 86855 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 219 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3239 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 29.045749 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 106.714286 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1980154 # number of writebacks -system.cpu.icache.writebacks::total 1980154 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3028 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3028 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3028 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3028 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3028 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3028 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1980847 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1980847 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1980847 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1980847 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1980847 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1980847 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15183658439 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15183658439 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15183658439 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15183658439 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15183658439 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15183658439 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007996 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007996 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007996 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.007996 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007996 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.007996 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7665.235346 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7665.235346 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7665.235346 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7665.235346 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7665.235346 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7665.235346 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 1350785 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 1355219 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 3879 # number of redundant prefetches already in prefetch queue +system.cpu.icache.avg_blocked_cycles::no_mshrs 26.815375 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 31.285714 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 1980658 # number of writebacks +system.cpu.icache.writebacks::total 1980658 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2752 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2752 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2752 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2752 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2752 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2752 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1981478 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1981478 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1981478 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1981478 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1981478 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1981478 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15191208442 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15191208442 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15191208442 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15191208442 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15191208442 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15191208442 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007998 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007998 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007998 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.007998 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007998 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.007998 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7666.604647 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7666.604647 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7666.604647 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7666.604647 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7666.604647 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7666.604647 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 1350180 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 1355046 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 4259 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4789973 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 297120 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16096.917401 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3841839 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 313315 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.261906 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 4789962 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 297363 # number of replacements +system.cpu.l2cache.tags.tagsinuse 16097.095848 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3953275 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 313560 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.607715 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15676.222250 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 420.695151 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.956801 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.025677 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.982478 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 430 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15765 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 61 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 263 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 100 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 402 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1551 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3686 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10031 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.026245 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962219 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 145605931 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 145605931 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 735798 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 735798 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 3358223 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 3358223 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 718689 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 718689 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1976463 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1976463 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1286254 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1286254 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1976463 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2004943 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3981406 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1976463 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2004943 # number of overall hits -system.cpu.l2cache.overall_hits::total 3981406 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 181 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 181 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 2160 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2160 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4204 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 4204 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 749865 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 749865 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 4204 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 752025 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 756229 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 4204 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 752025 # number of overall misses -system.cpu.l2cache.overall_misses::total 756229 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 187813000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 187813000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 349759500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 349759500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 63761970000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 63761970000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 349759500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 63949783000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 64299542500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 349759500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 63949783000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 64299542500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 735798 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 735798 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 3358223 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 3358223 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 181 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 181 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 720849 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 720849 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1980667 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1980667 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2036119 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 2036119 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1980667 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2756968 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 4737635 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1980667 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2756968 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 4737635 # number of overall (read+write) accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 15676.959856 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 420.135992 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.956846 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.025643 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.982489 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 460 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15737 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 63 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 274 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 116 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 407 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1553 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3714 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 9969 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.028076 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.960510 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 145611380 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 145611380 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 735645 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 735645 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 3358020 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 3358020 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 718668 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 718668 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1976918 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1976918 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1285460 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1285460 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1976918 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2004128 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 3981046 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1976918 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2004128 # number of overall hits +system.cpu.l2cache.overall_hits::total 3981046 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 308 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 308 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 2183 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2183 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4253 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 4253 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 750727 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 750727 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 4253 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 752910 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 757163 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 4253 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 752910 # number of overall misses +system.cpu.l2cache.overall_misses::total 757163 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 189493000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 189493000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 353014500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 353014500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 63858972500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 63858972500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 353014500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 64048465500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 64401480000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 353014500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 64048465500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 64401480000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 735645 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 735645 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 3358020 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 3358020 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 308 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 308 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 720851 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 720851 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1981171 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1981171 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2036187 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 2036187 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1981171 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2757038 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 4738209 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1981171 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2757038 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 4738209 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002996 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.002996 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.002123 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.002123 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.368282 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.368282 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.002123 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.272772 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.159622 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.002123 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.272772 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.159622 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86950.462963 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86950.462963 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83196.836346 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83196.836346 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85031.265628 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85031.265628 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83196.836346 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85036.778033 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 85026.549498 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83196.836346 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85036.778033 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 85026.549498 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003028 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.003028 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.002147 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.002147 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.368693 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.368693 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.002147 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.273087 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.159799 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.002147 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.273087 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.159799 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86803.939533 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86803.939533 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83003.644486 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83003.644486 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85062.842418 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85062.842418 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83003.644486 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85067.890585 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 85056.295672 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83003.644486 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85067.890585 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 85056.295672 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 3549 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 66317 # number of writebacks -system.cpu.l2cache.writebacks::total 66317 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 785 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 785 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 1052 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 1052 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 1837 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 1838 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 1837 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 1838 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202613 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 202613 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 181 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 181 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1375 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1375 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4203 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4203 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 748813 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 748813 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 4203 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 750188 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 754391 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 4203 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 750188 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202613 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 957004 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 20275662144 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 20275662144 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2881000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2881000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 136635500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 136635500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 324486000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 324486000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59198284500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59198284500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 324486000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59334920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 59659406000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 324486000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59334920000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 20275662144 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 79935068144 # number of overall MSHR miss cycles +system.cpu.l2cache.unused_prefetches 3562 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 66350 # number of writebacks +system.cpu.l2cache.writebacks::total 66350 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 796 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 796 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 1085 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 1085 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 1881 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 1883 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 1881 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 1883 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202894 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 202894 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 308 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 308 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1387 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1387 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4251 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4251 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 749642 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 749642 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4251 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 751029 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 755280 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4251 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 751029 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202894 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 958174 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 20344447507 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 20344447507 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4667000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4667000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 140070000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 140070000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 327411500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 327411500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59289686000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59289686000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 327411500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59429756000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 59757167500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 327411500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59429756000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 20344447507 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 80101615007 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001907 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001907 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.002122 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.002122 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367765 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367765 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.002122 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272106 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.159234 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.002122 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272106 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001924 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001924 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.002146 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.002146 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.368160 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.368160 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.002146 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272404 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.159402 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.002146 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272404 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.202000 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100070.884613 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 100070.884613 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15917.127072 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15917.127072 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 99371.272727 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 99371.272727 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 77203.426124 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 77203.426124 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79056.165558 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79056.165558 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77203.426124 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79093.400588 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79082.870819 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77203.426124 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79093.400588 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100070.884613 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83526.367856 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 9474606 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736642 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643287 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 98 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 97 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.202223 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100271.311655 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 100271.311655 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15152.597403 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15152.597403 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 100987.743331 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 100987.743331 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 77019.877676 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 77019.877676 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79090.667279 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79090.667279 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77019.877676 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79131.106788 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79119.223996 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77019.877676 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79131.106788 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100271.311655 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83598.193029 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 9476008 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 4737217 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 644846 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 94 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 93 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 4016964 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 802115 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4000812 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 230803 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 255056 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 181 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 181 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 720849 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 720849 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036119 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5941666 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270754 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 14212420 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253492416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352859136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 606351552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 552356 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4255808 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 5290172 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.121625 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.326853 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 4017663 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 801995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4001539 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 231013 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 255559 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 308 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 308 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 720851 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 720851 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1981478 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036187 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5943305 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8271218 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 14214523 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253556928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352868096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 606425024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 553229 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4266048 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 5291746 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.121883 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.327151 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 4646755 87.84% 87.84% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 643416 12.16% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 4646773 87.81% 87.81% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 644972 12.19% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5290172 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 9473913000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5291746 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 9475188000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2971268997 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2972215996 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4135554476 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4135722477 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 1254210 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 939897 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1255754 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 941197 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 955532 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66317 # Transaction distribution -system.membus.trans_dist::CleanEvict 230803 # Transaction distribution -system.membus.trans_dist::UpgradeReq 181 # Transaction distribution -system.membus.trans_dist::ReadExReq 1375 # Transaction distribution -system.membus.trans_dist::ReadExResp 1375 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 955534 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2211117 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2211117 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65486336 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 65486336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 956694 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66350 # Transaction distribution +system.membus.trans_dist::CleanEvict 231013 # Transaction distribution +system.membus.trans_dist::UpgradeReq 308 # Transaction distribution +system.membus.trans_dist::ReadExReq 1387 # Transaction distribution +system.membus.trans_dist::ReadExResp 1387 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 956696 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2213835 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2213835 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65563584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 65563584 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 957090 # Request fanout histogram +system.membus.snoop_fanout::samples 958391 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 957090 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 958391 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 957090 # Request fanout histogram -system.membus.reqLayer0.occupancy 1757256327 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 958391 # Request fanout histogram +system.membus.reqLayer0.occupancy 1760245062 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 5028523066 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5035040414 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index 35c099c69..4f45fd20e 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,80 +1,80 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.060132 # Number of seconds simulated -sim_ticks 60131512500 # Number of ticks simulated -final_tick 60131512500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.060161 # Number of seconds simulated +sim_ticks 60161166500 # Number of ticks simulated +final_tick 60161166500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 320494 # Simulator instruction rate (inst/s) -host_op_rate 409865 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 271758284 # Simulator tick rate (ticks/s) -host_mem_usage 281048 # Number of bytes of host memory used -host_seconds 221.27 # Real time elapsed on the host +host_inst_rate 318648 # Simulator instruction rate (inst/s) +host_op_rate 407504 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 270326146 # Simulator tick rate (ticks/s) +host_mem_usage 281460 # Number of bytes of host memory used +host_seconds 222.55 # Real time elapsed on the host sim_insts 70915150 # Number of instructions simulated sim_ops 90690106 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 286336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7938624 # Number of bytes read from this memory -system.physmem.bytes_read::total 8224960 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 286336 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 286336 # Number of instructions bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 286272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7938560 # Number of bytes read from this memory +system.physmem.bytes_read::total 8224832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 286272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 286272 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5539328 # Number of bytes written to this memory system.physmem.bytes_written::total 5539328 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4474 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124041 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128515 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 4473 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124040 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128513 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 86552 # Number of write requests responded to by this memory system.physmem.num_writes::total 86552 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 4761829 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 132021026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 136782856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4761829 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4761829 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 92120217 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 92120217 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 92120217 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4761829 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 132021026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 228903073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128515 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 4758418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 131954888 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 136713307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4758418 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4758418 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 92074810 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 92074810 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 92074810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4758418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 131954888 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 228788117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128513 # Number of read requests accepted system.physmem.writeReqs 86552 # Number of write requests accepted -system.physmem.readBursts 128515 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 128513 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 86552 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8224640 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 8224512 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue -system.physmem.bytesWritten 5537472 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8224960 # Total read bytes from the system interface side +system.physmem.bytesWritten 5537792 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8224832 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 5539328 # Total written bytes from the system interface side system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 8086 # Per bank write bursts -system.physmem.perBankRdBursts::1 8335 # Per bank write bursts +system.physmem.perBankRdBursts::1 8337 # Per bank write bursts system.physmem.perBankRdBursts::2 8257 # Per bank write bursts system.physmem.perBankRdBursts::3 8155 # Per bank write bursts -system.physmem.perBankRdBursts::4 8301 # Per bank write bursts -system.physmem.perBankRdBursts::5 8413 # Per bank write bursts -system.physmem.perBankRdBursts::6 8070 # Per bank write bursts +system.physmem.perBankRdBursts::4 8300 # Per bank write bursts +system.physmem.perBankRdBursts::5 8411 # Per bank write bursts +system.physmem.perBankRdBursts::6 8071 # Per bank write bursts system.physmem.perBankRdBursts::7 7917 # Per bank write bursts system.physmem.perBankRdBursts::8 8054 # Per bank write bursts -system.physmem.perBankRdBursts::9 7613 # Per bank write bursts +system.physmem.perBankRdBursts::9 7612 # Per bank write bursts system.physmem.perBankRdBursts::10 7771 # Per bank write bursts -system.physmem.perBankRdBursts::11 7825 # Per bank write bursts +system.physmem.perBankRdBursts::11 7824 # Per bank write bursts system.physmem.perBankRdBursts::12 7888 # Per bank write bursts -system.physmem.perBankRdBursts::13 7870 # Per bank write bursts -system.physmem.perBankRdBursts::14 7981 # Per bank write bursts -system.physmem.perBankRdBursts::15 7974 # Per bank write bursts -system.physmem.perBankWrBursts::0 5400 # Per bank write bursts +system.physmem.perBankRdBursts::13 7869 # Per bank write bursts +system.physmem.perBankRdBursts::14 7983 # Per bank write bursts +system.physmem.perBankRdBursts::15 7973 # Per bank write bursts +system.physmem.perBankWrBursts::0 5399 # Per bank write bursts system.physmem.perBankWrBursts::1 5549 # Per bank write bursts -system.physmem.perBankWrBursts::2 5475 # Per bank write bursts +system.physmem.perBankWrBursts::2 5478 # Per bank write bursts system.physmem.perBankWrBursts::3 5349 # Per bank write bursts system.physmem.perBankWrBursts::4 5387 # Per bank write bursts -system.physmem.perBankWrBursts::5 5586 # Per bank write bursts +system.physmem.perBankWrBursts::5 5588 # Per bank write bursts system.physmem.perBankWrBursts::6 5325 # Per bank write bursts system.physmem.perBankWrBursts::7 5260 # Per bank write bursts system.physmem.perBankWrBursts::8 5187 # Per bank write bursts -system.physmem.perBankWrBursts::9 5135 # Per bank write bursts +system.physmem.perBankWrBursts::9 5136 # Per bank write bursts system.physmem.perBankWrBursts::10 5306 # Per bank write bursts system.physmem.perBankWrBursts::11 5279 # Per bank write bursts system.physmem.perBankWrBursts::12 5541 # Per bank write bursts @@ -83,14 +83,14 @@ system.physmem.perBankWrBursts::14 5706 # Pe system.physmem.perBankWrBursts::15 5441 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 60131481000 # Total gap between requests +system.physmem.totGap 60161135000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128515 # Read request sizes (log2) +system.physmem.readPktSize::6 128513 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -98,11 +98,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 86552 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 116093 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12374 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 116119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12356 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -145,28 +145,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5436 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5580 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -194,115 +194,115 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 32872 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 418.606960 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 258.799568 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 361.901911 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8565 26.06% 26.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 6426 19.55% 45.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3391 10.32% 55.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2471 7.52% 63.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2230 6.78% 70.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1617 4.92% 75.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1341 4.08% 79.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1209 3.68% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5622 17.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 32872 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5350 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.018131 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 17.666671 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 347.276238 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5348 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 32871 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 418.627483 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 258.357746 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 362.584215 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8602 26.17% 26.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6385 19.42% 45.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3434 10.45% 56.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2432 7.40% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2215 6.74% 70.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1621 4.93% 75.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1317 4.01% 79.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1216 3.70% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5649 17.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 32871 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5351 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.014390 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 17.652764 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 347.251849 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5349 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5350 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5350 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.172523 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.162775 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.583592 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4904 91.66% 91.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 3 0.06% 91.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 417 7.79% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 22 0.41% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 3 0.06% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5350 # Writes before turning the bus around for reads -system.physmem.totQLat 3049168000 # Total ticks spent queuing -system.physmem.totMemAccLat 5458730500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 642550000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23727.09 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5351 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5351 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.170435 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.160762 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.581098 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4912 91.80% 91.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 3 0.06% 91.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 408 7.62% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 22 0.41% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 5 0.09% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5351 # Writes before turning the bus around for reads +system.physmem.totQLat 3055484500 # Total ticks spent queuing +system.physmem.totMemAccLat 5465009500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 642540000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23776.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42477.09 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 136.78 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 92.09 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 136.78 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 92.12 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 42526.61 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 136.71 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 92.05 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 136.71 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 92.07 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.79 # Data bus utilization in percentage system.physmem.busUtilRead 1.07 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.72 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.60 # Average write queue length when enqueuing -system.physmem.readRowHits 112228 # Number of row buffer hits during reads -system.physmem.writeRowHits 69923 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.33 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.79 # Row buffer hit rate for writes -system.physmem.avgGap 279594.18 # Average gap between requests +system.physmem.avgWrQLen 23.51 # Average write queue length when enqueuing +system.physmem.readRowHits 112270 # Number of row buffer hits during reads +system.physmem.writeRowHits 69886 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.36 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.74 # Row buffer hit rate for writes +system.physmem.avgGap 279734.66 # Average gap between requests system.physmem.pageHitRate 84.70 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 123522000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 65634525 # Energy for precharge commands per rank (pJ) +system.physmem_0.actEnergy 123657660 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 65710425 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 467912760 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 226187820 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2502199440.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2202561510 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 166933440 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5874746040 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 2984525760 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 8651084625 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 23265974460 # Total energy per rank (pJ) -system.physmem_0.averagePower 386.918165 # Core power per rank (mW) -system.physmem_0.totalIdleTime 54864943500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 285874500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1063428000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 34209724750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 7772192000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 3916970750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 12883322500 # Time in different power states -system.physmem_1.actEnergy 111255480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 59114715 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 449648640 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 225462240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2476999200.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2186669910 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 154102560 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 5325095040 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 3204580800 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 8848579860 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 23042291445 # Total energy per rank (pJ) -system.physmem_1.averagePower 383.198268 # Core power per rank (mW) -system.physmem_1.totalIdleTime 54933017000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 256278500 # Time in different power states -system.physmem_1.memoryStateTime::REF 1053008000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 34910026000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 8345277500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 3889148250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 11677774250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 14827796 # Number of BP lookups -system.cpu.branchPred.condPredicted 9922694 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 342031 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9662877 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6571901 # Number of BTB hits +system.physmem_0.writeEnergy 226208700 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2513877600.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2171898930 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 163742880 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 5875439160 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 3027961440 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 8657105625 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 23294071200 # Total energy per rank (pJ) +system.physmem_0.averagePower 387.194467 # Core power per rank (mW) +system.physmem_0.totalIdleTime 54970200750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 277627750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1068464000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 34200521750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 7885291750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 3844571250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 12884690000 # Time in different power states +system.physmem_1.actEnergy 111105540 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 59035020 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 449634360 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 225467460 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2466550320.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2149128000 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 155904480 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 5311061070 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 3203698560 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 8880552330 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 23012901840 # Total energy per rank (pJ) +system.physmem_1.averagePower 382.520865 # Core power per rank (mW) +system.physmem_1.totalIdleTime 55040293250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 259491500 # Time in different power states +system.physmem_1.memoryStateTime::REF 1048576000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 35050414500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 8342978750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 3812745000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 11646960750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 14829931 # Number of BP lookups +system.cpu.branchPred.condPredicted 9922625 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 344341 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9711925 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6581090 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 68.011846 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1720082 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 67.762982 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1720914 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 175657 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 158615 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 17042 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 24764 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 175731 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 158482 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 17249 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 24894 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -332,7 +332,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -362,7 +362,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -392,7 +392,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -423,16 +423,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 60131512500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 120263025 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 60161166500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 120322333 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915150 # Number of instructions committed system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1179235 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1183243 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.695872 # CPI: cycles per instruction -system.cpu.ipc 0.589667 # IPC: instructions per cycle +system.cpu.cpi 1.696708 # CPI: cycles per instruction +system.cpu.ipc 0.589376 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction @@ -472,338 +472,338 @@ system.cpu.op_class_0::FloatMemWrite 32 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 90690106 # Class of committed instruction -system.cpu.tickCycles 98355658 # Number of cycles that the object actually ticked -system.cpu.idleCycles 21907367 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 156451 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.127626 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42637298 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160547 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.575177 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 880684500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127626 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992951 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992951 # Average percentage of cache occupancy +system.cpu.tickCycles 98402849 # Number of cycles that the object actually ticked +system.cpu.idleCycles 21919484 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 156448 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.144261 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42640706 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160544 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.601368 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 880402500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.144261 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992955 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992955 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 1009 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3044 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3045 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86034719 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86034719 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 22880155 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22880155 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19642142 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19642142 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83163 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83163 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 86041472 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86041472 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 22883524 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22883524 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19642139 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642139 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83205 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83205 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42522297 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42522297 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42605460 # number of overall hits -system.cpu.dcache.overall_hits::total 42605460 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 47246 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 47246 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 207759 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207759 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 44783 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 44783 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 255005 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 255005 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 299788 # number of overall misses -system.cpu.dcache.overall_misses::total 299788 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1839905000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1839905000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18545313000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18545313000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20385218000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20385218000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20385218000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20385218000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22927401 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22927401 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42525663 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42525663 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42608868 # number of overall hits +system.cpu.dcache.overall_hits::total 42608868 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 47232 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 47232 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207762 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207762 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 44764 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 44764 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 254994 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 254994 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 299758 # number of overall misses +system.cpu.dcache.overall_misses::total 299758 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1840606500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1840606500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18547852000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18547852000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20388458500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20388458500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20388458500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20388458500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22930756 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22930756 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 127946 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 127946 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 127969 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 127969 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42777302 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42777302 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42905248 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42905248 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002061 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002061 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 42780657 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42780657 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42908626 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42908626 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002060 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002060 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010467 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.010467 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.350015 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.350015 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.005961 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005961 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006987 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006987 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38943.085129 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38943.085129 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89263.584249 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 89263.584249 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 79940.463912 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 79940.463912 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67998.779137 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67998.779137 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 185 # number of cycles access was blocked +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.349803 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.349803 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005960 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005960 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006986 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006986 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38969.480437 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38969.480437 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89274.516033 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 89274.516033 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 79956.620548 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 79956.620548 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 68016.394892 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 68016.394892 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 185 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 128145 # number of writebacks -system.cpu.dcache.writebacks::total 128145 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 17717 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 17717 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100722 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 100722 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 118439 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 118439 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 118439 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 118439 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29529 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 29529 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107037 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107037 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23981 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 23981 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 136566 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 136566 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 160547 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160547 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 773861500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 773861500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9479489000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9479489000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1896776000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1896776000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10253350500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10253350500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12150126500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12150126500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 128143 # number of writebacks +system.cpu.dcache.writebacks::total 128143 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 17700 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 17700 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100723 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 100723 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 118423 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 118423 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 118423 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 118423 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29532 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 29532 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107039 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107039 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23973 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 23973 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 136571 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 136571 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 160544 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160544 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 777371000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 777371000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9483957500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9483957500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1891396500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1891396500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10261328500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10261328500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12152725000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12152725000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187431 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187431 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187334 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187334 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26206.830573 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26206.830573 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88562.730645 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88562.730645 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79094.950169 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79094.950169 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75079.818549 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75079.818549 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75679.561125 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75679.561125 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 43545 # number of replacements -system.cpu.icache.tags.tagsinuse 1851.999823 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25048343 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 45587 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 549.462413 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26323.005553 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26323.005553 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88602.822336 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88602.822336 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78896.946565 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78896.946565 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75135.486304 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75135.486304 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75697.160903 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75697.160903 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 43580 # number of replacements +system.cpu.icache.tags.tagsinuse 1852.022642 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25068801 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 45622 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 549.489303 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1851.999823 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.904297 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.904297 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1852.022642 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.904308 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.904308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 898 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1021 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 897 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1022 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50233449 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50233449 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 25048343 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25048343 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25048343 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25048343 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25048343 # number of overall hits -system.cpu.icache.overall_hits::total 25048343 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 45588 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 45588 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 45588 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 45588 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 45588 # number of overall misses -system.cpu.icache.overall_misses::total 45588 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1042263500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1042263500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1042263500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1042263500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1042263500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1042263500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25093931 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25093931 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25093931 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25093931 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25093931 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25093931 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 50274470 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50274470 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 25068801 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25068801 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25068801 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25068801 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25068801 # number of overall hits +system.cpu.icache.overall_hits::total 25068801 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 45623 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 45623 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 45623 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 45623 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 45623 # number of overall misses +system.cpu.icache.overall_misses::total 45623 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1044947000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1044947000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1044947000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1044947000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1044947000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1044947000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25114424 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25114424 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25114424 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25114424 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25114424 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25114424 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001817 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001817 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001817 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001817 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001817 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001817 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22862.672194 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22862.672194 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22862.672194 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22862.672194 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22862.672194 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22862.672194 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22903.951954 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22903.951954 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22903.951954 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22903.951954 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22903.951954 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22903.951954 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 43545 # number of writebacks -system.cpu.icache.writebacks::total 43545 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45588 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 45588 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 45588 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 45588 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 45588 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 45588 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 996676500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 996676500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 996676500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 996676500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 996676500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 996676500 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 43580 # number of writebacks +system.cpu.icache.writebacks::total 43580 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45623 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 45623 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 45623 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 45623 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 45623 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 45623 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 999325000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 999325000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 999325000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 999325000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 999325000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 999325000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001817 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001817 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001817 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21862.694130 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21862.694130 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21862.694130 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21862.694130 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21862.694130 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21862.694130 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 97176 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31292.341702 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 268174 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129944 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.063766 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 10980599000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 476.632754 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1378.083150 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29437.625798 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.014546 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.042056 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.898365 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.954966 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21903.973873 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21903.973873 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21903.973873 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21903.973873 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21903.973873 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21903.973873 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 97173 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31293.322597 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 268235 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 129941 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.064283 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 10984579000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 476.897365 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1377.117238 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29439.307994 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.014554 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.042026 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.898416 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.954996 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1141 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12834 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17840 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 782 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1149 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12846 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17826 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 783 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3316240 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3316240 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 128145 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 128145 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 39944 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 39944 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4720 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4720 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41101 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 41101 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31726 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 31726 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 41101 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 36446 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 77547 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 41101 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 36446 # number of overall hits -system.cpu.l2cache.overall_hits::total 77547 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 102317 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102317 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4487 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 4487 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21784 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 21784 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 4487 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 124101 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 128588 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 4487 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 124101 # number of overall misses -system.cpu.l2cache.overall_misses::total 128588 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9269327500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9269327500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 492863000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 492863000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2253034500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2253034500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 492863000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11522362000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 12015225000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 492863000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11522362000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 12015225000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 128145 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 128145 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 39944 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 39944 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 107037 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 107037 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 45588 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 45588 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53510 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 53510 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 45588 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 160547 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 206135 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 45588 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 160547 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 206135 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955903 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955903 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098425 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098425 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.407101 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.407101 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098425 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.772989 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.623805 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098425 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.772989 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.623805 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90594.207219 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90594.207219 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 109842.433697 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 109842.433697 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103426.115498 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 103426.115498 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 109842.433697 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92846.649100 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 93439.706660 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 109842.433697 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92846.649100 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 93439.706660 # average overall miss latency +system.cpu.l2cache.tags.tag_accesses 3316701 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3316701 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 128143 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 128143 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 39976 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 39976 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4721 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4721 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41137 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 41137 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31723 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 31723 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 41137 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 36444 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 77581 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 41137 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 36444 # number of overall hits +system.cpu.l2cache.overall_hits::total 77581 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 102318 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102318 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4486 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 4486 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21782 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 21782 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 4486 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 124100 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 128586 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 4486 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 124100 # number of overall misses +system.cpu.l2cache.overall_misses::total 128586 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9273780500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9273780500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 495081500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 495081500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2251192500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2251192500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 495081500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11524973000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12020054500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 495081500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11524973000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12020054500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 128143 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 128143 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 39976 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 39976 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 107039 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 107039 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 45623 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 45623 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53505 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 53505 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 45623 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 160544 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 206167 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 45623 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 160544 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 206167 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955895 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955895 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098328 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098328 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.407102 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.407102 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098328 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.772997 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.623698 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098328 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.772997 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.623698 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90636.842980 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90636.842980 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 110361.457869 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 110361.457869 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103351.046736 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 103351.046736 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 110361.457869 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92868.436745 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 93478.718523 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 110361.457869 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92868.436745 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 93478.718523 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -824,128 +824,128 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 60 system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102317 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102317 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4475 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4475 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21724 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21724 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 4475 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 124041 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 128516 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 4475 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 124041 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 128516 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8246157500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8246157500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 446695500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 446695500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2029647000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2029647000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 446695500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10275804500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10722500000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 446695500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10275804500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10722500000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102318 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102318 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4474 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4474 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21722 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21722 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4474 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124040 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128514 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4474 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124040 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128514 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8250600500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8250600500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 448924000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 448924000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2029137000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2029137000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 448924000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10279737500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10728661500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 448924000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10279737500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10728661500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955903 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955903 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098162 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.405980 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.405980 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.623456 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.623456 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80594.207219 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80594.207219 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99820.223464 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99820.223464 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93428.788437 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93428.788437 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99820.223464 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82841.999823 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83433.191198 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99820.223464 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82841.999823 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83433.191198 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 406131 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 200034 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7844 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955895 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955895 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.098065 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098065 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.405981 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.405981 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.098065 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772623 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.623349 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098065 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772623 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.623349 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80636.842980 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80636.842980 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 100340.634779 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 100340.634779 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93413.912163 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93413.912163 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 100340.634779 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82874.375202 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83482.433820 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 100340.634779 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82874.375202 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83482.433820 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 406195 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 200065 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7850 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 3482 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3452 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 99097 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 214697 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 43545 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 38930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107037 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107037 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 45588 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 53510 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134720 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477545 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 612265 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5704448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18476288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 24180736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 97176 # Total snoops (count) +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 99127 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 214695 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 43580 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 38926 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107039 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107039 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 45623 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 53505 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134825 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477536 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 612361 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5708928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18475968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 24184896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 97173 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 5539328 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 303311 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.037565 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.190662 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 303340 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.037578 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.190694 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 291947 96.25% 96.25% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 11334 3.74% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 291971 96.25% 96.25% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11339 3.74% 99.99% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 303311 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 374755500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 303340 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 374820500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 68395969 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 68448469 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 240852935 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 240848435 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 222304 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 93865 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 222299 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 93862 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 26198 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 26195 # Transaction distribution system.membus.trans_dist::WritebackDirty 86552 # Transaction distribution -system.membus.trans_dist::CleanEvict 7237 # Transaction distribution -system.membus.trans_dist::ReadExReq 102317 # Transaction distribution -system.membus.trans_dist::ReadExResp 102317 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 26198 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 350819 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 350819 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13764288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13764288 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::CleanEvict 7234 # Transaction distribution +system.membus.trans_dist::ReadExReq 102318 # Transaction distribution +system.membus.trans_dist::ReadExResp 102318 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 26195 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 350812 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 350812 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13764160 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13764160 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 128515 # Request fanout histogram +system.membus.snoop_fanout::samples 128513 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 128515 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 128513 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 128515 # Request fanout histogram -system.membus.reqLayer0.occupancy 588249500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 128513 # Request fanout histogram +system.membus.reqLayer0.occupancy 588234000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 677382500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 677366750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index ad340b529..79d31fb69 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.038007 # Number of seconds simulated -sim_ticks 38007342000 # Number of ticks simulated -final_tick 38007342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.037944 # Number of seconds simulated +sim_ticks 37944194500 # Number of ticks simulated +final_tick 37944194500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 224949 # Simulator instruction rate (inst/s) -host_op_rate 287684 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 120575368 # Simulator tick rate (ticks/s) -host_mem_usage 283980 # Number of bytes of host memory used -host_seconds 315.22 # Real time elapsed on the host +host_inst_rate 220724 # Simulator instruction rate (inst/s) +host_op_rate 282280 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 118113932 # Simulator tick rate (ticks/s) +host_mem_usage 283128 # Number of bytes of host memory used +host_seconds 321.25 # Real time elapsed on the host sim_insts 70907652 # Number of instructions simulated sim_ops 90682607 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 2373952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5705216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6169536 # Number of bytes read from this memory -system.physmem.bytes_read::total 14248704 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2373952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2373952 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6224192 # Number of bytes written to this memory -system.physmem.bytes_written::total 6224192 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 37093 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 89144 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96399 # Number of read requests responded to by this memory -system.physmem.num_reads::total 222636 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97253 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97253 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 62460353 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 150108261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 162324848 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 374893461 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 62460353 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 62460353 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 163762886 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 163762886 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 163762886 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 62460353 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 150108261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 162324848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 538656347 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222637 # Number of read requests accepted -system.physmem.writeReqs 97253 # Number of write requests accepted -system.physmem.readBursts 222637 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97253 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 14240000 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue -system.physmem.bytesWritten 6222848 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 14248768 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6224192 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 2366464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5687552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6178176 # Number of bytes read from this memory +system.physmem.bytes_read::total 14232192 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2366464 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2366464 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6224000 # Number of bytes written to this memory +system.physmem.bytes_written::total 6224000 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 36976 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 88868 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96534 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222378 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97250 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97250 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 62366958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 149892548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 162822695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 375082201 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 62366958 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 62366958 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 164030363 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 164030363 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 164030363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 62366958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 149892548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 162822695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 539112564 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222379 # Number of read requests accepted +system.physmem.writeReqs 97250 # Number of write requests accepted +system.physmem.readBursts 222379 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97250 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 14222400 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9856 # Total number of bytes read from write queue +system.physmem.bytesWritten 6222336 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 14232256 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6224000 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 154 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9656 # Per bank write bursts -system.physmem.perBankRdBursts::1 9952 # Per bank write bursts -system.physmem.perBankRdBursts::2 12608 # Per bank write bursts -system.physmem.perBankRdBursts::3 25349 # Per bank write bursts -system.physmem.perBankRdBursts::4 17405 # Per bank write bursts -system.physmem.perBankRdBursts::5 22083 # Per bank write bursts -system.physmem.perBankRdBursts::6 11752 # Per bank write bursts -system.physmem.perBankRdBursts::7 14068 # Per bank write bursts -system.physmem.perBankRdBursts::8 11731 # Per bank write bursts -system.physmem.perBankRdBursts::9 15466 # Per bank write bursts -system.physmem.perBankRdBursts::10 11740 # Per bank write bursts -system.physmem.perBankRdBursts::11 11331 # Per bank write bursts -system.physmem.perBankRdBursts::12 9464 # Per bank write bursts -system.physmem.perBankRdBursts::13 9568 # Per bank write bursts -system.physmem.perBankRdBursts::14 9844 # Per bank write bursts -system.physmem.perBankRdBursts::15 20483 # Per bank write bursts -system.physmem.perBankWrBursts::0 5965 # Per bank write bursts -system.physmem.perBankWrBursts::1 6210 # Per bank write bursts -system.physmem.perBankWrBursts::2 6157 # Per bank write bursts -system.physmem.perBankWrBursts::3 6128 # Per bank write bursts -system.physmem.perBankWrBursts::4 6115 # Per bank write bursts -system.physmem.perBankWrBursts::5 6243 # Per bank write bursts -system.physmem.perBankWrBursts::6 6020 # Per bank write bursts -system.physmem.perBankWrBursts::7 5952 # Per bank write bursts -system.physmem.perBankWrBursts::8 5952 # Per bank write bursts -system.physmem.perBankWrBursts::9 6130 # Per bank write bursts -system.physmem.perBankWrBursts::10 6213 # Per bank write bursts -system.physmem.perBankWrBursts::11 5918 # Per bank write bursts -system.physmem.perBankWrBursts::12 6006 # Per bank write bursts -system.physmem.perBankWrBursts::13 6051 # Per bank write bursts -system.physmem.perBankWrBursts::14 6145 # Per bank write bursts -system.physmem.perBankWrBursts::15 6027 # Per bank write bursts +system.physmem.perBankRdBursts::0 9631 # Per bank write bursts +system.physmem.perBankRdBursts::1 9947 # Per bank write bursts +system.physmem.perBankRdBursts::2 12518 # Per bank write bursts +system.physmem.perBankRdBursts::3 24674 # Per bank write bursts +system.physmem.perBankRdBursts::4 17362 # Per bank write bursts +system.physmem.perBankRdBursts::5 22065 # Per bank write bursts +system.physmem.perBankRdBursts::6 11751 # Per bank write bursts +system.physmem.perBankRdBursts::7 14087 # Per bank write bursts +system.physmem.perBankRdBursts::8 11655 # Per bank write bursts +system.physmem.perBankRdBursts::9 16110 # Per bank write bursts +system.physmem.perBankRdBursts::10 11699 # Per bank write bursts +system.physmem.perBankRdBursts::11 11328 # Per bank write bursts +system.physmem.perBankRdBursts::12 9447 # Per bank write bursts +system.physmem.perBankRdBursts::13 9546 # Per bank write bursts +system.physmem.perBankRdBursts::14 9858 # Per bank write bursts +system.physmem.perBankRdBursts::15 20547 # Per bank write bursts +system.physmem.perBankWrBursts::0 5941 # Per bank write bursts +system.physmem.perBankWrBursts::1 6221 # Per bank write bursts +system.physmem.perBankWrBursts::2 6116 # Per bank write bursts +system.physmem.perBankWrBursts::3 6136 # Per bank write bursts +system.physmem.perBankWrBursts::4 6032 # Per bank write bursts +system.physmem.perBankWrBursts::5 6294 # Per bank write bursts +system.physmem.perBankWrBursts::6 6000 # Per bank write bursts +system.physmem.perBankWrBursts::7 5967 # Per bank write bursts +system.physmem.perBankWrBursts::8 5964 # Per bank write bursts +system.physmem.perBankWrBursts::9 6073 # Per bank write bursts +system.physmem.perBankWrBursts::10 6219 # Per bank write bursts +system.physmem.perBankWrBursts::11 5919 # Per bank write bursts +system.physmem.perBankWrBursts::12 6077 # Per bank write bursts +system.physmem.perBankWrBursts::13 6073 # Per bank write bursts +system.physmem.perBankWrBursts::14 6160 # Per bank write bursts +system.physmem.perBankWrBursts::15 6032 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 38007330500 # Total gap between requests +system.physmem.totGap 37944183500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 222637 # Read request sizes (log2) +system.physmem.readPktSize::6 222379 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97253 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 112108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 59931 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10934 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4622 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4261 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 73 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 42 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97250 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 111691 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 60016 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15678 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10788 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5274 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4596 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4274 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 47 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see @@ -149,36 +149,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6446 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8436 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -198,119 +198,119 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 132899 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 153.968593 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 102.497917 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 209.528989 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 82983 62.44% 62.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 32243 24.26% 86.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6367 4.79% 91.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2726 2.05% 93.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1184 0.89% 94.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1005 0.76% 95.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 875 0.66% 95.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 807 0.61% 96.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4709 3.54% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 132899 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5883 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 37.820840 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 210.672420 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5878 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 132661 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 154.093818 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.620444 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 209.524421 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 82661 62.31% 62.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 32331 24.37% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6343 4.78% 91.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2828 2.13% 93.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1153 0.87% 94.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1000 0.75% 95.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 785 0.59% 95.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 836 0.63% 96.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4724 3.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 132661 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5873 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 37.833986 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 211.191475 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5868 99.91% 99.91% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::512-1023 4 0.07% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-15871 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5883 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5882 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.528392 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.490234 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.186972 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4697 79.85% 79.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 46 0.78% 80.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 744 12.65% 93.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 191 3.25% 96.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 91 1.55% 98.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 73 1.24% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 20 0.34% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 15 0.26% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5882 # Writes before turning the bus around for reads -system.physmem.totQLat 8329547257 # Total ticks spent queuing -system.physmem.totMemAccLat 12501422257 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1112500000 # Total ticks spent in databus transfers -system.physmem.avgQLat 37436.00 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 4999.98 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 56185.91 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 374.66 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 163.73 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 374.90 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 163.76 # Average system write bandwidth in MiByte/s +system.physmem.rdPerTurnAround::total 5873 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5873 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.554401 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.514141 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.221324 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4642 79.04% 79.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 60 1.02% 80.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 721 12.28% 92.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 237 4.04% 96.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 117 1.99% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 50 0.85% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 21 0.36% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 10 0.17% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 9 0.15% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 3 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 3 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5873 # Writes before turning the bus around for reads +system.physmem.totQLat 8400725955 # Total ticks spent queuing +system.physmem.totMemAccLat 12567444705 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1111125000 # Total ticks spent in databus transfers +system.physmem.avgQLat 37802.79 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 56552.79 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 374.82 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 163.99 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 375.08 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 164.03 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 4.21 # Data bus utilization in percentage system.physmem.busUtilRead 2.93 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.28 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.37 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.63 # Average write queue length when enqueuing -system.physmem.readRowHits 157173 # Number of row buffer hits during reads -system.physmem.writeRowHits 29653 # Number of row buffer hits during writes -system.physmem.readRowHitRate 70.64 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 30.49 # Row buffer hit rate for writes -system.physmem.avgGap 118813.75 # Average gap between requests -system.physmem.pageHitRate 58.43 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 507596880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 269771370 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 877313220 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 254683800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3009892080.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2962459860 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 75632160 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 13054365150 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 948417120 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 77983215 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 22038660255 # Total energy per rank (pJ) -system.physmem_0.averagePower 579.852702 # Core power per rank (mW) -system.physmem_0.totalIdleTime 31313307761 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 43781047 # Time in different power states -system.physmem_0.memoryStateTime::REF 1273526000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 214718250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 2469720434 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5376727192 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 28628869077 # Time in different power states -system.physmem_1.actEnergy 441337680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 234557565 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 711336780 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 252841140 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2899256880.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2760551040 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 73978560 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 11934955830 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 1428119040 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 493845795 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 21231004530 # Total energy per rank (pJ) -system.physmem_1.averagePower 558.602674 # Core power per rank (mW) -system.physmem_1.totalIdleTime 31760586804 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 51273339 # Time in different power states -system.physmem_1.memoryStateTime::REF 1226918000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1868150750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 3718457459 # Time in different power states -system.physmem_1.memoryStateTime::ACT 4968563857 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 26173978595 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 17074531 # Number of BP lookups -system.cpu.branchPred.condPredicted 11460402 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 598628 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9274722 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7374340 # Number of BTB hits +system.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing +system.physmem.readRowHits 156951 # Number of row buffer hits during reads +system.physmem.writeRowHits 29827 # Number of row buffer hits during writes +system.physmem.readRowHitRate 70.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 30.67 # Row buffer hit rate for writes +system.physmem.avgGap 118713.21 # Average gap between requests +system.physmem.pageHitRate 58.46 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 506618700 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 269259045 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 871329900 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 254250540 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3004974960.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2939010630 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75129120 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 12925802790 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 1053663840 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 77310705 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 21977801430 # Total energy per rank (pJ) +system.physmem_0.averagePower 579.213801 # Core power per rank (mW) +system.physmem_0.totalIdleTime 31303061618 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 43527335 # Time in different power states +system.physmem_0.memoryStateTime::REF 1271434000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 212368250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 2743799817 # Time in different power states +system.physmem_0.memoryStateTime::ACT 5326073297 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 28346991801 # Time in different power states +system.physmem_1.actEnergy 440652240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 234189450 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 715349460 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 253258740 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2887578720.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2772991290 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 73095360 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 11918051910 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 1378656480 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 511952955 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 21185918985 # Total energy per rank (pJ) +system.physmem_1.averagePower 558.344142 # Core power per rank (mW) +system.physmem_1.totalIdleTime 31672221792 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 50102341 # Time in different power states +system.physmem_1.memoryStateTime::REF 1221978000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1946071250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 3589983863 # Time in different power states +system.physmem_1.memoryStateTime::ACT 4999892367 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 26136166679 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 17059712 # Number of BP lookups +system.cpu.branchPred.condPredicted 11436495 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 610883 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9177884 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7343978 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 79.510092 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1855435 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101567 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 233050 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 195925 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 37125 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 22231 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 80.018205 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1859096 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101568 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 235599 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 198019 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 37580 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 22235 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -340,7 +340,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -370,7 +370,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -400,7 +400,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -431,241 +431,241 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 38007342000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 76014685 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 37944194500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 75888390 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5565404 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87125388 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17074531 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9425700 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 66120510 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1223729 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 11256 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 48 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 32224 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22440736 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 69274 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 72341306 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.522198 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.331033 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 5573583 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87028801 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17059712 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9401093 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 65975948 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1248205 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 11552 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 20 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 32118 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22429818 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 69336 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 72217323 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.523317 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.330813 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 27150688 37.53% 37.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8169627 11.29% 48.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9114831 12.60% 61.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27906160 38.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 27066857 37.48% 37.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8167411 11.31% 48.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9106696 12.61% 61.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27876359 38.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 72341306 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.224621 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.146165 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8942287 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 26299816 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 30976482 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5677371 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 445350 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3133946 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 168438 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 100318297 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2804928 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 445350 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13582767 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11480611 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 882043 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 31792045 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14158490 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 98346425 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 855389 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 4229008 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 68182 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4663621 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5443965 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103273055 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 453619684 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 114297516 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 686 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 72217323 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.224800 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.146800 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8951903 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 26171728 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 30965562 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5674558 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 453572 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6946604 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172649 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 100221832 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2852875 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 453572 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13609160 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11386876 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 864961 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 31760902 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14141852 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 98228803 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 864073 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 4236637 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 68346 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4658326 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5438830 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103135317 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 453117590 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 114171014 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 768 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629369 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9643686 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18991 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 19021 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12815345 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24159121 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21761593 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1442839 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2330212 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97411129 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34857 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94489103 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 595557 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6763379 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 17995254 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1071 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 72341306 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.306157 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.170975 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9505948 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 19046 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 19073 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12792135 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24137829 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21734716 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1433415 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2312086 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97293576 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34871 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94397579 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 595173 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6645840 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 17792691 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1085 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 72217323 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.307132 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.170641 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24199109 33.45% 33.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17470195 24.15% 57.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17034708 23.55% 81.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11601119 16.04% 97.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2034740 2.81% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1435 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24111122 33.39% 33.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17469676 24.19% 57.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17013658 23.56% 81.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11592271 16.05% 97.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2029206 2.81% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1390 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 72341306 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 72217323 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6739464 22.68% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 40 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11065982 37.24% 59.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 11909373 40.08% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 33 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6732689 22.67% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 34 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11048676 37.21% 59.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 11914326 40.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 49 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 21 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49308872 52.18% 52.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 86547 0.09% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 13 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23960981 25.36% 77.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21132544 22.37% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 62 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49269666 52.19% 52.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 86409 0.09% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 33 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 12 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 19 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23933468 25.35% 77.64% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21107870 22.36% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 70 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 32 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94489103 # Type of FU issued -system.cpu.iq.rate 1.243037 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29714913 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.314480 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 291629642 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 104220574 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93205627 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 340 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 544 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 99 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124203819 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 197 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1369166 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 94397579 # Type of FU issued +system.cpu.iq.rate 1.243900 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29695795 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.314582 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 291303077 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 103985333 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93134762 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 372 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 690 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 96 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 124093153 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 221 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1368431 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1292859 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2033 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11913 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1205855 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1271567 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1549 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11881 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1178978 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 148706 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 187344 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 147641 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 185447 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 445350 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 625818 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1199933 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97461708 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 453572 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 612952 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1120138 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97344492 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24159121 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21761593 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18937 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1609 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1195657 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11913 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 250763 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 222991 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 473754 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93695211 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23697676 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 793892 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24137829 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21734716 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18951 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1593 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1115880 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11881 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 249751 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 231660 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 481411 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93615083 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23674361 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 782496 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 15722 # number of nop insts executed -system.cpu.iew.exec_refs 44622526 # number of memory reference insts executed -system.cpu.iew.exec_branches 14207940 # Number of branches executed -system.cpu.iew.exec_stores 20924850 # Number of stores executed -system.cpu.iew.exec_rate 1.232594 # Inst execution rate -system.cpu.iew.wb_sent 93313259 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93205726 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44957522 # num instructions producing a value -system.cpu.iew.wb_consumers 76634731 # num instructions consuming a value -system.cpu.iew.wb_rate 1.226154 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.586647 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 5905401 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 16045 # number of nop insts executed +system.cpu.iew.exec_refs 44580255 # number of memory reference insts executed +system.cpu.iew.exec_branches 14200394 # Number of branches executed +system.cpu.iew.exec_stores 20905894 # Number of stores executed +system.cpu.iew.exec_rate 1.233589 # Inst execution rate +system.cpu.iew.wb_sent 93237318 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93134858 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44916796 # num instructions producing a value +system.cpu.iew.wb_consumers 76568590 # num instructions consuming a value +system.cpu.iew.wb_rate 1.227261 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.586622 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 5786029 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 432114 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 71383083 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.270443 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.106463 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 440353 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 71261477 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.272611 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.107279 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 37916370 53.12% 53.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16693361 23.39% 76.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4299601 6.02% 82.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4172974 5.85% 88.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1943479 2.72% 91.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1233650 1.73% 92.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 737671 1.03% 93.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 579334 0.81% 94.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3806643 5.33% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 37792643 53.03% 53.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16691471 23.42% 76.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4304606 6.04% 82.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4169247 5.85% 88.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1943443 2.73% 91.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1235947 1.73% 92.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 743394 1.04% 93.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 579944 0.81% 94.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3800782 5.33% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 71383083 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 71261477 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913204 # Number of instructions committed system.cpu.commit.committedOps 90688159 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -715,552 +715,552 @@ system.cpu.commit.op_class_0::FloatMemWrite 32 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688159 # Class of committed instruction -system.cpu.commit.bw_lim_events 3806643 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 164144701 # The number of ROB reads -system.cpu.rob.rob_writes 194146843 # The number of ROB writes -system.cpu.timesIdled 54077 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3673379 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3800782 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 163909584 # The number of ROB reads +system.cpu.rob.rob_writes 193905843 # The number of ROB writes +system.cpu.timesIdled 54309 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3671067 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907652 # Number of Instructions Simulated system.cpu.committedOps 90682607 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.072024 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.072024 # CPI: Total CPI of All Threads -system.cpu.ipc 0.932815 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.932815 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 101986551 # number of integer regfile reads -system.cpu.int_regfile_writes 56614441 # number of integer regfile writes -system.cpu.fp_regfile_reads 62 # number of floating regfile reads -system.cpu.fp_regfile_writes 51 # number of floating regfile writes -system.cpu.cc_regfile_reads 345121100 # number of cc regfile reads -system.cpu.cc_regfile_writes 38758964 # number of cc regfile writes -system.cpu.misc_regfile_reads 44102244 # number of misc regfile reads +system.cpu.cpi 1.070243 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.070243 # CPI: Total CPI of All Threads +system.cpu.ipc 0.934368 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.934368 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 101911048 # number of integer regfile reads +system.cpu.int_regfile_writes 56566498 # number of integer regfile writes +system.cpu.fp_regfile_reads 60 # number of floating regfile reads +system.cpu.fp_regfile_writes 50 # number of floating regfile writes +system.cpu.cc_regfile_reads 344842465 # number of cc regfile reads +system.cpu.cc_regfile_writes 38739142 # number of cc regfile writes +system.cpu.misc_regfile_reads 44068796 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 484796 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.868688 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40338903 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485308 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.120210 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 154723500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.868688 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997790 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997790 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 484861 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.868864 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40324171 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485373 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.078727 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 154340500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.868864 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997791 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997791 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84466908 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84466908 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 21416602 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21416602 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18830761 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18830761 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60264 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60264 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15306 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15306 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84436477 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84436477 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 21401665 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21401665 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18831129 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18831129 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60098 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60098 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15305 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15305 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40247363 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40247363 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40307627 # number of overall hits -system.cpu.dcache.overall_hits::total 40307627 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 563583 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 563583 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1019140 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1019140 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 68608 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 68608 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 617 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 617 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1582723 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1582723 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1651331 # number of overall misses -system.cpu.dcache.overall_misses::total 1651331 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14467064000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14467064000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14294982430 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14294982430 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6393500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 6393500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28762046430 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28762046430 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28762046430 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28762046430 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21980185 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21980185 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40232794 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40232794 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40292892 # number of overall hits +system.cpu.dcache.overall_hits::total 40292892 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 563103 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 563103 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1018772 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1018772 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68943 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68943 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 618 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 618 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1581875 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1581875 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1650818 # number of overall misses +system.cpu.dcache.overall_misses::total 1650818 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14421291500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14421291500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14222478926 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14222478926 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5900000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5900000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28643770426 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28643770426 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28643770426 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28643770426 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21964768 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21964768 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128872 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128872 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 129041 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 129041 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15923 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15923 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41830086 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41830086 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41958958 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41958958 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025641 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025641 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051342 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051342 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532373 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.532373 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038749 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038749 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037837 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037837 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039356 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039356 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25669.801964 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25669.801964 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14026.514934 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14026.514934 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10362.236629 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10362.236629 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18172.508032 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18172.508032 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17417.493180 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17417.493180 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2976739 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 131356 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.800000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22.661614 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 484796 # number of writebacks -system.cpu.dcache.writebacks::total 484796 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 264511 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 264511 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870576 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 870576 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 617 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 617 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1135087 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1135087 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1135087 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1135087 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299072 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299072 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148564 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148564 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37686 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37686 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 447636 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 447636 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 485322 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 485322 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7113004000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7113004000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2350412971 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2350412971 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2001432500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2001432500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9463416971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9463416971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11464849471 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11464849471 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013606 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013606 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007484 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007484 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292430 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292430 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010701 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.010701 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011567 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.011567 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23783.583886 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23783.583886 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15820.878349 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15820.878349 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53108.117073 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53108.117073 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21140.875557 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21140.875557 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23623.181045 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23623.181045 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 325456 # number of replacements -system.cpu.icache.tags.tagsinuse 510.336563 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22103277 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 325967 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.808327 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 1174665500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.336563 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996751 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996751 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu.dcache.demand_accesses::cpu.data 41814669 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41814669 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41943710 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41943710 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025637 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025637 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051324 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051324 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.534272 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.534272 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038812 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038812 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037831 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037831 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039358 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039358 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25610.397210 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25610.397210 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13960.414034 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 13960.414034 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9546.925566 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9546.925566 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18107.480317 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18107.480317 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17351.258846 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17351.258846 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 104 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2957939 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 131286 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.933333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22.530498 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 484861 # number of writebacks +system.cpu.dcache.writebacks::total 484861 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 263994 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 263994 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870189 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 870189 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 618 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 618 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1134183 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1134183 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1134183 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1134183 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299109 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 299109 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148583 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 148583 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37695 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 37695 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 447692 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 447692 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 485387 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 485387 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7100123000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7100123000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2335671469 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2335671469 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2001428000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2001428000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9435794469 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9435794469 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11437222469 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11437222469 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013618 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013618 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007485 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007485 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292116 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292116 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010707 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.010707 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011572 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.011572 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23737.577271 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23737.577271 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15719.641339 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15719.641339 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53095.317681 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53095.317681 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21076.531341 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21076.531341 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23563.100102 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23563.100102 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 325105 # number of replacements +system.cpu.icache.tags.tagsinuse 510.398248 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22092527 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 325617 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.848199 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 1172472500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.398248 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996872 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996872 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 332 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 333 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 8 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45207041 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45207041 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 22103280 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22103280 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22103280 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22103280 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22103280 # number of overall hits -system.cpu.icache.overall_hits::total 22103280 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 337250 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 337250 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 337250 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 337250 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 337250 # number of overall misses -system.cpu.icache.overall_misses::total 337250 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 5803062852 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 5803062852 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 5803062852 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 5803062852 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 5803062852 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 5803062852 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22440530 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22440530 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22440530 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22440530 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22440530 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22440530 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015029 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.015029 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.015029 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.015029 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.015029 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.015029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17207.006233 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17207.006233 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17207.006233 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17207.006233 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17207.006233 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17207.006233 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 559762 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 25894 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.617440 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 325456 # number of writebacks -system.cpu.icache.writebacks::total 325456 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 11268 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 11268 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 11268 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 11268 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 11268 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 11268 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 325982 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 325982 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 325982 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 325982 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 325982 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 325982 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5371171413 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 5371171413 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5371171413 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 5371171413 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5371171413 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 5371171413 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014526 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014526 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014526 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014526 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16476.895697 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16476.895697 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16476.895697 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16476.895697 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16476.895697 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16476.895697 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 822258 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 825535 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 2876 # number of redundant prefetches already in prefetch queue +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 45184842 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45184842 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 22092527 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22092527 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22092527 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22092527 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22092527 # number of overall hits +system.cpu.icache.overall_hits::total 22092527 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 337079 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 337079 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 337079 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 337079 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 337079 # number of overall misses +system.cpu.icache.overall_misses::total 337079 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 5811924859 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 5811924859 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 5811924859 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 5811924859 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 5811924859 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 5811924859 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22429606 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22429606 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22429606 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22429606 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22429606 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22429606 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015028 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015028 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015028 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015028 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015028 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015028 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17242.025932 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17242.025932 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17242.025932 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17242.025932 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17242.025932 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17242.025932 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 559324 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 118 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 25723 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.744120 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 39.333333 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 325105 # number of writebacks +system.cpu.icache.writebacks::total 325105 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 11448 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 11448 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 11448 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 11448 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 11448 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 11448 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 325631 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 325631 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 325631 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 325631 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 325631 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 325631 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5369635927 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 5369635927 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5369635927 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 5369635927 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5369635927 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 5369635927 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014518 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014518 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014518 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014518 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014518 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014518 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16489.940844 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16489.940844 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16489.940844 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16489.940844 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16489.940844 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16489.940844 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 822760 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 825879 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 2736 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 78497 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 125579 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15699.484972 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 681508 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 141902 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.802667 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 78985 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 125384 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15697.006900 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 681705 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 141714 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.810428 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15625.141607 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 74.343365 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.953683 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004538 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.958221 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 24 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 16299 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 15640.024987 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 56.981913 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.954591 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.003478 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.958069 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 23 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 16307 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 12 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 10 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::4 3 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2587 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12184 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 533 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 859 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001465 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994812 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 25493850 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 25493850 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 260429 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 260429 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 469974 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 469974 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 137044 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 137044 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 288848 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 288848 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 255916 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 255916 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 288848 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 392960 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 681808 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 288848 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 392960 # number of overall hits -system.cpu.l2cache.overall_hits::total 681808 # number of overall hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2537 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12202 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 564 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 868 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001404 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995300 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 25485617 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 25485617 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 259863 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 259863 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 470316 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 470316 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 137267 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 137267 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 288609 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 288609 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 256036 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 256036 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 288609 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 393303 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 681912 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 288609 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 393303 # number of overall hits +system.cpu.l2cache.overall_hits::total 681912 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 14 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 14 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 11552 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 11552 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 37119 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 37119 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 80796 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 80796 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 37119 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 92348 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 129467 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 37119 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 92348 # number of overall misses -system.cpu.l2cache.overall_misses::total 129467 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1233354500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1233354500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 3144915500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 3144915500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6919452000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6919452000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 3144915500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8152806500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11297722000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 3144915500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8152806500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11297722000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 260429 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 260429 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 469974 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 469974 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 11350 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 11350 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 37008 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 37008 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 80720 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 80720 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 37008 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 92070 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 129078 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 37008 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 92070 # number of overall misses +system.cpu.l2cache.overall_misses::total 129078 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1217096500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1217096500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 3145310000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 3145310000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6905491500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6905491500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 3145310000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8122588000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11267898000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 3145310000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8122588000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11267898000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 259863 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 259863 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 470316 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 470316 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 14 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 148596 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 148596 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 325967 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 325967 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 336712 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 336712 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 325967 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 485308 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 811275 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 325967 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 485308 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 811275 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 148617 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 148617 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 325617 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 325617 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 336756 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 336756 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 325617 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 485373 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 810990 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 325617 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 485373 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 810990 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.077741 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.077741 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.113873 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.113873 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.239956 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.239956 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113873 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.190287 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.159585 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113873 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.190287 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.159585 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106765.451870 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106765.451870 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84725.221585 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84725.221585 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85641.021833 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85641.021833 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84725.221585 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88283.519946 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 87263.333514 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84725.221585 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88283.519946 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 87263.333514 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.076371 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.076371 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.113655 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.113655 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.239699 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.239699 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113655 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.189689 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.159161 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113655 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.189689 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.159161 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 107233.171806 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 107233.171806 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84990.002162 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84990.002162 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85548.705401 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85548.705401 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84990.002162 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88221.874661 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 87295.263329 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84990.002162 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88221.874661 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 87295.263329 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 426 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 97253 # number of writebacks -system.cpu.l2cache.writebacks::total 97253 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3091 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 3091 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 25 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 25 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 113 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 113 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 25 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 3204 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 3229 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 25 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 3204 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 3229 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 114995 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 114995 # number of HardPFReq MSHR misses +system.cpu.l2cache.unused_prefetches 367 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 97250 # number of writebacks +system.cpu.l2cache.writebacks::total 97250 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3084 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 3084 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 31 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 31 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 118 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 118 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 31 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 3202 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 3233 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 31 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 3202 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 3233 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 115040 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 115040 # number of HardPFReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 14 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8461 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 8461 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 37094 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 37094 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 80683 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 80683 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 37094 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 89144 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 126238 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 37094 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 89144 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 114995 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 241233 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10227090401 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10227090401 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 218000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 218000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 733523000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 733523000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2920395500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2920395500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6427576500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6427576500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2920395500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7161099500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10081495000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2920395500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7161099500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10227090401 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20308585401 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8266 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 8266 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 36977 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 36977 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 80602 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 80602 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 36977 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 88868 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 125845 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 36977 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 88868 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 115040 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 240885 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10309951422 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10309951422 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 216500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 216500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 719316500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 719316500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2921107000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2921107000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6413507000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6413507000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2921107000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7132823500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10053930500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2921107000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7132823500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10309951422 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20363881922 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056940 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056940 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.113797 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.113797 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.239620 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239620 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113797 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.183685 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.155604 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113797 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.183685 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.055619 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.055619 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.113560 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.113560 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.239348 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239348 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113560 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.183092 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.155175 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113560 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.183092 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.297350 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 88935.087621 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 88935.087621 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15571.428571 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15571.428571 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86694.598747 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86694.598747 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78729.592387 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78729.592387 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79664.569984 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79664.569984 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78729.592387 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80331.817060 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79861.016493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78729.592387 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80331.817060 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 88935.087621 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84186.597194 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1621556 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 810285 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80433 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 18616 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18570 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 46 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 662693 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 357682 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 549823 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 28326 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 146207 # Transaction distribution +system.cpu.l2cache.overall_mshr_miss_rate::total 0.297026 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89620.579120 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 89620.579120 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15464.285714 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15464.285714 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87021.110573 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87021.110573 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78997.944668 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78997.944668 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79570.072703 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79570.072703 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78997.944668 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80263.126210 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79891.378283 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78997.944668 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80263.126210 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89620.579120 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84537.774963 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1620984 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 810002 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80349 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 18528 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18483 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 45 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 662386 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 357113 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 550103 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 28134 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 146171 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148596 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148596 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 325982 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 336712 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 977404 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455440 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2432844 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41691008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62086656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 103777664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 271801 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6225152 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1083090 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.091523 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.288499 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 148617 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148617 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 325631 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 336756 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 976352 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455635 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2431987 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41646144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62094976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 103741120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 271569 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6224896 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1082573 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.091409 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.288334 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 984008 90.85% 90.85% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 99036 9.14% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 46 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 983661 90.86% 90.86% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 98867 9.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 45 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1083090 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1621030000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1082573 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1620458000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 489099244 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 488577734 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 728047842 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 728149334 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 348230 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 205331 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 347777 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 205067 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 214175 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97253 # Transaction distribution -system.membus.trans_dist::CleanEvict 28326 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 214112 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97250 # Transaction distribution +system.membus.trans_dist::CleanEvict 28134 # Transaction distribution system.membus.trans_dist::UpgradeReq 14 # Transaction distribution -system.membus.trans_dist::ReadExReq 8461 # Transaction distribution -system.membus.trans_dist::ReadExResp 8461 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 214176 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570866 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 570866 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20472896 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20472896 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 8266 # Transaction distribution +system.membus.trans_dist::ReadExResp 8266 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 214113 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570155 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 570155 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20456192 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20456192 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 222651 # Request fanout histogram +system.membus.snoop_fanout::samples 222393 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 222651 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 222393 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 222651 # Request fanout histogram -system.membus.reqLayer0.occupancy 835869990 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 222393 # Request fanout histogram +system.membus.reqLayer0.occupancy 835299244 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1175713686 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1174434906 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index c13f099b6..fe9262960 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.150228 # Number of seconds simulated -sim_ticks 1150227786500 # Number of ticks simulated -final_tick 1150227786500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.150356 # Number of seconds simulated +sim_ticks 1150356296500 # Number of ticks simulated +final_tick 1150356296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 394229 # Simulator instruction rate (inst/s) -host_op_rate 424722 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 293579950 # Simulator tick rate (ticks/s) -host_mem_usage 273524 # Number of bytes of host memory used -host_seconds 3917.94 # Real time elapsed on the host +host_inst_rate 374766 # Simulator instruction rate (inst/s) +host_op_rate 403753 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 279117141 # Simulator tick rate (ticks/s) +host_mem_usage 273688 # Number of bytes of host memory used +host_seconds 4121.41 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 50240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 132094848 # Number of bytes read from this memory -system.physmem.bytes_read::total 132145088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 132097728 # Number of bytes read from this memory +system.physmem.bytes_read::total 132147968 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 50240 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 50240 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67849984 # Number of bytes written to this memory -system.physmem.bytes_written::total 67849984 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 67851072 # Number of bytes written to this memory +system.physmem.bytes_written::total 67851072 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 785 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2063982 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2064767 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1060156 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1060156 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 43678 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 114842338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 114886016 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 43678 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 43678 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 58988302 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 58988302 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 58988302 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 43678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 114842338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 173874318 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2064767 # Number of read requests accepted -system.physmem.writeReqs 1060156 # Number of write requests accepted -system.physmem.readBursts 2064767 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1060156 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 132061888 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 83200 # Total number of bytes read from write queue -system.physmem.bytesWritten 67848256 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 132145088 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 67849984 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1300 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu.data 2064027 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2064812 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1060173 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1060173 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 43673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 114832012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 114875685 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 43673 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 43673 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 58982658 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 58982658 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 58982658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 43673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 114832012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 173858343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2064812 # Number of read requests accepted +system.physmem.writeReqs 1060173 # Number of write requests accepted +system.physmem.readBursts 2064812 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1060173 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 132064448 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 83520 # Total number of bytes read from write queue +system.physmem.bytesWritten 67849344 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132147968 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 67851072 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1305 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 128524 # Per bank write bursts -system.physmem.perBankRdBursts::1 125801 # Per bank write bursts -system.physmem.perBankRdBursts::2 122666 # Per bank write bursts -system.physmem.perBankRdBursts::3 124575 # Per bank write bursts -system.physmem.perBankRdBursts::4 123572 # Per bank write bursts -system.physmem.perBankRdBursts::5 123680 # Per bank write bursts -system.physmem.perBankRdBursts::6 124357 # Per bank write bursts +system.physmem.perBankRdBursts::0 128530 # Per bank write bursts +system.physmem.perBankRdBursts::1 125798 # Per bank write bursts +system.physmem.perBankRdBursts::2 122667 # Per bank write bursts +system.physmem.perBankRdBursts::3 124564 # Per bank write bursts +system.physmem.perBankRdBursts::4 123583 # Per bank write bursts +system.physmem.perBankRdBursts::5 123689 # Per bank write bursts +system.physmem.perBankRdBursts::6 124368 # Per bank write bursts system.physmem.perBankRdBursts::7 124965 # Per bank write bursts -system.physmem.perBankRdBursts::8 132488 # Per bank write bursts -system.physmem.perBankRdBursts::9 134781 # Per bank write bursts -system.physmem.perBankRdBursts::10 133246 # Per bank write bursts +system.physmem.perBankRdBursts::8 132503 # Per bank write bursts +system.physmem.perBankRdBursts::9 134776 # Per bank write bursts +system.physmem.perBankRdBursts::10 133237 # Per bank write bursts system.physmem.perBankRdBursts::11 134508 # Per bank write bursts -system.physmem.perBankRdBursts::12 134523 # Per bank write bursts -system.physmem.perBankRdBursts::13 134597 # Per bank write bursts -system.physmem.perBankRdBursts::14 130537 # Per bank write bursts -system.physmem.perBankRdBursts::15 130647 # Per bank write bursts -system.physmem.perBankWrBursts::0 66781 # Per bank write bursts -system.physmem.perBankWrBursts::1 64940 # Per bank write bursts -system.physmem.perBankWrBursts::2 63173 # Per bank write bursts -system.physmem.perBankWrBursts::3 63584 # Per bank write bursts -system.physmem.perBankWrBursts::4 63558 # Per bank write bursts -system.physmem.perBankWrBursts::5 63644 # Per bank write bursts -system.physmem.perBankWrBursts::6 65047 # Per bank write bursts -system.physmem.perBankWrBursts::7 66059 # Per bank write bursts -system.physmem.perBankWrBursts::8 67975 # Per bank write bursts -system.physmem.perBankWrBursts::9 68435 # Per bank write bursts -system.physmem.perBankWrBursts::10 68155 # Per bank write bursts -system.physmem.perBankWrBursts::11 68585 # Per bank write bursts -system.physmem.perBankWrBursts::12 68036 # Per bank write bursts -system.physmem.perBankWrBursts::13 68532 # Per bank write bursts -system.physmem.perBankWrBursts::14 67159 # Per bank write bursts +system.physmem.perBankRdBursts::12 134521 # Per bank write bursts +system.physmem.perBankRdBursts::13 134606 # Per bank write bursts +system.physmem.perBankRdBursts::14 130538 # Per bank write bursts +system.physmem.perBankRdBursts::15 130654 # Per bank write bursts +system.physmem.perBankWrBursts::0 66782 # Per bank write bursts +system.physmem.perBankWrBursts::1 64941 # Per bank write bursts +system.physmem.perBankWrBursts::2 63176 # Per bank write bursts +system.physmem.perBankWrBursts::3 63581 # Per bank write bursts +system.physmem.perBankWrBursts::4 63564 # Per bank write bursts +system.physmem.perBankWrBursts::5 63647 # Per bank write bursts +system.physmem.perBankWrBursts::6 65050 # Per bank write bursts +system.physmem.perBankWrBursts::7 66062 # Per bank write bursts +system.physmem.perBankWrBursts::8 67977 # Per bank write bursts +system.physmem.perBankWrBursts::9 68434 # Per bank write bursts +system.physmem.perBankWrBursts::10 68153 # Per bank write bursts +system.physmem.perBankWrBursts::11 68587 # Per bank write bursts +system.physmem.perBankWrBursts::12 68034 # Per bank write bursts +system.physmem.perBankWrBursts::13 68534 # Per bank write bursts +system.physmem.perBankWrBursts::14 67158 # Per bank write bursts system.physmem.perBankWrBursts::15 66466 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1150227685500 # Total gap between requests +system.physmem.totGap 1150356195500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2064767 # Read request sizes (log2) +system.physmem.readPktSize::6 2064812 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1060156 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1919511 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 143942 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1060173 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1919552 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 143941 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -145,26 +145,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 32142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 62501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 62728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 62816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 62688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 62636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 30915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 32043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 62496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 62733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 62829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 62687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 62667 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 62593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 62501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 62570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 62618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 63061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 62416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 62338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 62549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 62604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 62637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 63099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 62454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 62359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -194,122 +194,122 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1927678 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.704158 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.827351 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.878363 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1497959 77.71% 77.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 310183 16.09% 93.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52221 2.71% 96.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20819 1.08% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 1927714 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.704114 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.833686 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.867792 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1497696 77.69% 77.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 310699 16.12% 93.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52184 2.71% 96.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20631 1.07% 97.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 13074 0.68% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7800 0.40% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5214 0.27% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5117 0.27% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 15291 0.79% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1927678 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 62183 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.137240 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 23.854238 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 150.737609 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 62144 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::640-767 7807 0.40% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5185 0.27% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5186 0.27% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15252 0.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1927714 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 62200 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.128826 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 23.842942 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 148.982645 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 62161 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 18 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 4 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 4 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 5 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::18432-19455 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 62183 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 62183 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.048534 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.017369 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.031425 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 29894 48.07% 48.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1086 1.75% 49.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 29528 47.49% 97.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1644 2.64% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 28 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 62183 # Writes before turning the bus around for reads -system.physmem.totQLat 59946131250 # Total ticks spent queuing -system.physmem.totMemAccLat 98636137500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10317335000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29051.17 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 62200 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 62200 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.044148 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.013066 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.029999 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 29988 48.21% 48.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1141 1.83% 50.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 29436 47.32% 97.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1609 2.59% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 24 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 62200 # Writes before turning the bus around for reads +system.physmem.totQLat 60011294750 # Total ticks spent queuing +system.physmem.totMemAccLat 98702051000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10317535000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29082.19 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47801.17 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 114.81 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 58.99 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 114.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 58.99 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47832.19 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 114.80 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 58.98 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 114.88 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 58.98 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.36 # Data bus utilization in percentage system.physmem.busUtilRead 0.90 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.46 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing -system.physmem.readRowHits 775435 # Number of row buffer hits during reads -system.physmem.writeRowHits 420473 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.58 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.66 # Row buffer hit rate for writes -system.physmem.avgGap 368081.93 # Average gap between requests +system.physmem.avgWrQLen 24.14 # Average write queue length when enqueuing +system.physmem.readRowHits 775182 # Number of row buffer hits during reads +system.physmem.writeRowHits 420747 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.69 # Row buffer hit rate for writes +system.physmem.avgGap 368115.75 # Average gap between requests system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6703938780 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3563201400 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7126719600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 2697622920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 71587735440.000015 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47610368340 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2598027360 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 242891748180 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 71936235360 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 82347779655 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 539087705175 # Total energy per rank (pJ) -system.physmem_0.averagePower 468.679083 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1039000185750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 3501543500 # Time in different power states -system.physmem_0.memoryStateTime::REF 30348316000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 319007908000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 187335147250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 77377438000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 532657433750 # Time in different power states -system.physmem_1.actEnergy 7059753540 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3752336610 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7606434780 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 6705024060 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3563778240 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7126890960 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 2697711660 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 71598184320.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47589199680 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2602904160 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 242927855970 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 71960703840 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 82354339920 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 539151608970 # Total energy per rank (pJ) +system.physmem_0.averagePower 468.682274 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1039160467250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3513710000 # Time in different power states +system.physmem_0.memoryStateTime::REF 30352766000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 319025802500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 187397997250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 77329050000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 532736970750 # Time in different power states +system.physmem_1.actEnergy 7058925300 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3751896390 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7606549020 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 2836250460 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 71062832880.000015 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 47583848520 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2430369600 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 248599905450 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 68453747040 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 80907358950 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 540315522360 # Total energy per rank (pJ) -system.physmem_1.averagePower 469.746535 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1039499383250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3059154750 # Time in different power states -system.physmem_1.memoryStateTime::REF 30118266000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 316057409750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 178263690250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 77550921750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 545178344000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 240019900 # Number of BP lookups -system.cpu.branchPred.condPredicted 186610401 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14528957 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 131646658 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122324616 # Number of BTB hits +system.physmem_1.refreshEnergy 71153184960.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 47703954360 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2452947360 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 248582355720 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 68636874240 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 80784488595 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 540590019675 # Total energy per rank (pJ) +system.physmem_1.averagePower 469.932679 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1039304472000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3115835000 # Time in different power states +system.physmem_1.memoryStateTime::REF 30156708000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 315425606000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 178743425250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 77779220750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 545135501500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 240030332 # Number of BP lookups +system.cpu.branchPred.condPredicted 186613747 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14536765 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 132238924 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122337864 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.918892 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15657431 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 92.512749 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15662658 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 535 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 538 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 232 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 303 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 306 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 162 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -339,7 +339,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -369,7 +369,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -399,7 +399,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -430,16 +430,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2300455573 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2300712593 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563088 # Number of instructions committed system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed -system.cpu.discardedOps 41363694 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 41389188 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.489389 # CPI: cycles per instruction -system.cpu.ipc 0.671416 # IPC: instructions per cycle +system.cpu.cpi 1.489556 # CPI: cycles per instruction +system.cpu.ipc 0.671341 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction @@ -479,16 +479,16 @@ system.cpu.op_class_0::FloatMemWrite 24 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 1664032481 # Class of committed instruction -system.cpu.tickCycles 1845015660 # Number of cycles that the object actually ticked -system.cpu.idleCycles 455439913 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9220107 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.805308 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624493167 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9224203 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.701585 # Average number of references to valid blocks. +system.cpu.tickCycles 1845105384 # Number of cycles that the object actually ticked +system.cpu.idleCycles 455607209 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 9220185 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.806447 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624504262 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9224281 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.702216 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 9872962500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.805308 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.806447 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997511 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997511 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -497,43 +497,43 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 1190 system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1277391153 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1277391153 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 454163886 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 454163886 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170329158 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170329158 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1277413521 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1277413521 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 454174952 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 454174952 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170329187 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170329187 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624493044 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624493044 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624493045 # number of overall hits -system.cpu.dcache.overall_hits::total 624493045 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7333417 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7333417 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2256889 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2256889 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 624504139 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624504139 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624504140 # number of overall hits +system.cpu.dcache.overall_hits::total 624504140 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7333496 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7333496 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2256860 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2256860 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9590306 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9590306 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9590308 # number of overall misses -system.cpu.dcache.overall_misses::total 9590308 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 208196327000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 208196327000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 119903341000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 119903341000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 328099668000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 328099668000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 328099668000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 328099668000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461497303 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461497303 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9590356 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9590356 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9590358 # number of overall misses +system.cpu.dcache.overall_misses::total 9590358 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 208281810000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 208281810000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 119887020500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 119887020500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 328168830500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 328168830500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 328168830500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 328168830500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461508448 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461508448 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) @@ -542,64 +542,64 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 634083350 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 634083350 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 634083353 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 634083353 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 634094495 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 634094495 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 634094498 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 634094498 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015890 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015890 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013077 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.013077 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015125 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015125 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015125 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015125 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28390.084322 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28390.084322 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53127.708540 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53127.708540 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34211.595334 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34211.595334 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34211.588199 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34211.588199 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.015124 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015124 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015124 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015124 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28401.435005 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28401.435005 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53121.159709 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53121.159709 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34218.628641 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34218.628641 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34218.621505 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34218.621505 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3670055 # number of writebacks -system.cpu.dcache.writebacks::total 3670055 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3670078 # number of writebacks +system.cpu.dcache.writebacks::total 3670078 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 366055 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 366055 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 366104 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 366104 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 366104 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 366104 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333368 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7333368 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890834 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1890834 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 366027 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 366027 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 366076 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 366076 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 366076 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 366076 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333447 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7333447 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890833 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890833 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9224202 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9224202 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9224203 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9224203 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200858538000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 200858538000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92467008500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 92467008500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9224280 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9224280 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9224281 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9224281 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200943921500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 200943921500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92449770000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92449770000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 81000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 81000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293325546500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 293325546500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293325627500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 293325627500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293393691500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 293393691500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293393772500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 293393772500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses @@ -610,70 +610,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014547 system.cpu.dcache.demand_mshr_miss_rate::total 0.014547 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27389.671158 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27389.671158 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48902.763807 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48902.763807 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27401.019125 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27401.019125 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48893.672789 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48893.672789 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 81000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 81000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31799.558000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31799.558000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31799.563334 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31799.563334 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31806.676673 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31806.676673 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31806.682006 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31806.682006 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 33 # number of replacements -system.cpu.icache.tags.tagsinuse 660.477823 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 466274758 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 660.481453 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 466324528 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 822 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 567244.231144 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 567304.778589 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 660.477823 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.322499 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.322499 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 660.481453 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.322501 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.322501 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 751 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.385254 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 932551982 # Number of tag accesses -system.cpu.icache.tags.data_accesses 932551982 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 466274758 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 466274758 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 466274758 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 466274758 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 466274758 # number of overall hits -system.cpu.icache.overall_hits::total 466274758 # number of overall hits +system.cpu.icache.tags.tag_accesses 932651522 # Number of tag accesses +system.cpu.icache.tags.data_accesses 932651522 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 466324528 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 466324528 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 466324528 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 466324528 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 466324528 # number of overall hits +system.cpu.icache.overall_hits::total 466324528 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 822 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 822 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 822 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 822 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 822 # number of overall misses system.cpu.icache.overall_misses::total 822 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 74803000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 74803000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 74803000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 74803000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 74803000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 74803000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 466275580 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 466275580 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 466275580 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 466275580 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 466275580 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 466275580 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 75338000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 75338000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 75338000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 75338000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 75338000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 75338000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 466325350 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 466325350 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 466325350 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 466325350 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 466325350 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 466325350 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 91001.216545 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 91001.216545 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 91001.216545 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 91001.216545 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 91001.216545 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 91001.216545 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 91652.068127 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 91652.068127 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 91652.068127 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 91652.068127 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 91652.068127 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 91652.068127 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -688,38 +688,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 822 system.cpu.icache.demand_mshr_misses::total 822 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 822 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 822 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 73981000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 73981000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 73981000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 73981000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 73981000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 73981000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 74516000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 74516000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 74516000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 74516000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 74516000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 74516000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 90001.216545 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 90001.216545 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 90001.216545 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 90001.216545 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 90001.216545 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 90001.216545 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 2032334 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31895.837315 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 16378248 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2065102 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.930963 # Average number of references to valid blocks. +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 90652.068127 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 90652.068127 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 90652.068127 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 90652.068127 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 90652.068127 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 90652.068127 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 2032379 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31895.934748 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 16378358 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2065147 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.930844 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 54709395000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 10.372175 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.535649 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31859.929491 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 10.372068 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.532774 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31860.029906 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000317 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000779 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.972288 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.973384 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.972291 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.973387 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 831 # Occupied blocks per task id @@ -727,227 +727,227 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2946 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7191 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21752 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 149613670 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 149613670 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3670055 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3670055 # number of WritebackDirty hits +system.cpu.l2cache.tags.tag_accesses 149614963 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 149614963 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 3670078 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 3670078 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1078511 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1078511 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1078495 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1078495 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 37 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 37 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6081704 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6081704 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6081752 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 6081752 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 37 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7160215 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7160252 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7160247 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7160284 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 37 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7160215 # number of overall hits -system.cpu.l2cache.overall_hits::total 7160252 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 812323 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 812323 # number of ReadExReq misses +system.cpu.l2cache.overall_hits::cpu.data 7160247 # number of overall hits +system.cpu.l2cache.overall_hits::total 7160284 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 812338 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 812338 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 785 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 785 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1251665 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 1251665 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1251696 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 1251696 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 785 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2063988 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2064773 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2064034 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2064819 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 785 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2063988 # number of overall misses -system.cpu.l2cache.overall_misses::total 2064773 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 78282928500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 78282928500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 72328000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 72328000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 125997338000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 125997338000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 72328000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 204280266500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 204352594500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 72328000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 204280266500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 204352594500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 3670055 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 3670055 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 2064034 # number of overall misses +system.cpu.l2cache.overall_misses::total 2064819 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 78265681500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 78265681500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 72863000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 72863000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 126082122000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 126082122000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 72863000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 204347803500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 204420666500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 72863000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 204347803500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 204420666500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 3670078 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 3670078 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890834 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1890834 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890833 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1890833 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 822 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 822 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7333369 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7333369 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7333448 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 7333448 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 822 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9224203 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9225025 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9224281 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9225103 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 822 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9224203 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9225025 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.429611 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.429611 # miss rate for ReadExReq accesses +system.cpu.l2cache.overall_accesses::cpu.data 9224281 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9225103 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.429619 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.429619 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.954988 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.954988 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.170681 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.170681 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.170683 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.170683 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.954988 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.223758 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.223823 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.223761 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.223826 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.954988 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.223758 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.223823 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96369.213355 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96369.213355 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92137.579618 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92137.579618 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100663.786237 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100663.786237 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92137.579618 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98973.572763 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 98970.973807 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92137.579618 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98973.572763 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 98970.973807 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.223761 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.223826 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96346.202566 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96346.202566 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92819.108280 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92819.108280 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100729.028454 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100729.028454 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92819.108280 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99004.087869 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 99001.736472 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92819.108280 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99004.087869 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 99001.736472 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1060156 # number of writebacks -system.cpu.l2cache.writebacks::total 1060156 # number of writebacks -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits +system.cpu.l2cache.writebacks::writebacks 1060173 # number of writebacks +system.cpu.l2cache.writebacks::total 1060173 # number of writebacks +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 7 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 7 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 215 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 215 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 812323 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 812323 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 812338 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 812338 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 785 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 785 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1251659 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1251659 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1251689 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1251689 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 785 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2063982 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2064767 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2064027 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2064812 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 785 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2063982 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2064767 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70159698500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70159698500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 64478000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 64478000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113480200500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113480200500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64478000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183639899000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 183704377000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64478000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183639899000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 183704377000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 2064027 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2064812 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70142301500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70142301500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65013000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65013000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113564745500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113564745500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65013000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183707047000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 183772060000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65013000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183707047000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 183772060000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429611 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.429611 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429619 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.429619 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.954988 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.170680 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.170680 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.170682 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.170682 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223757 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.223822 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223760 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.223825 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223757 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.223822 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86369.213355 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86369.213355 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82137.579618 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82137.579618 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90663.831363 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90663.831363 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82137.579618 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88973.595215 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88970.996243 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82137.579618 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88973.595215 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88970.996243 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18445165 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220152 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223760 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.223825 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86346.202566 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86346.202566 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82819.108280 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82819.108280 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90729.203101 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90729.203101 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82819.108280 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 89004.187930 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 89001.836487 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82819.108280 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 89004.187930 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89001.836487 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18445321 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220230 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1444 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1438 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7334191 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4730211 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 7334270 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4730251 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6522230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890834 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6522313 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890833 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890833 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 822 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333369 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333448 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1677 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668513 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27670190 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668747 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27670424 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825232512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 825287232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2032334 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 67849984 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11257359 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825238976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 825293696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2032379 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 67851072 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11257482 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000271 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.016506 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11254309 99.97% 99.97% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11254432 99.97% 99.97% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 3044 0.03% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11257359 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12892670500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11257482 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12892771500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1233000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13836307494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13836424993 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 4095872 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2031262 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 4095962 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2031307 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1252444 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1060156 # Transaction distribution -system.membus.trans_dist::CleanEvict 970949 # Transaction distribution -system.membus.trans_dist::ReadExReq 812323 # Transaction distribution -system.membus.trans_dist::ReadExResp 812323 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1252444 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6160639 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6160639 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 199995072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 199995072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1252474 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1060173 # Transaction distribution +system.membus.trans_dist::CleanEvict 970977 # Transaction distribution +system.membus.trans_dist::ReadExReq 812338 # Transaction distribution +system.membus.trans_dist::ReadExResp 812338 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1252474 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6160774 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6160774 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 199999040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 199999040 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2064767 # Request fanout histogram +system.membus.snoop_fanout::samples 2064812 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2064767 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2064812 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2064767 # Request fanout histogram -system.membus.reqLayer0.occupancy 8804919500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2064812 # Request fanout histogram +system.membus.reqLayer0.occupancy 8805297000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 11285149250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11285202500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 413bb751f..2fc5a813e 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.787540 # Number of seconds simulated -sim_ticks 787540181500 # Number of ticks simulated -final_tick 787540181500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.787836 # Number of seconds simulated +sim_ticks 787835965500 # Number of ticks simulated +final_tick 787835965500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 265954 # Simulator instruction rate (inst/s) -host_op_rate 286525 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 135604104 # Simulator tick rate (ticks/s) -host_mem_usage 328428 # Number of bytes of host memory used -host_seconds 5807.64 # Real time elapsed on the host +host_inst_rate 263266 # Simulator instruction rate (inst/s) +host_op_rate 283629 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 134283963 # Simulator tick rate (ticks/s) +host_mem_usage 329624 # Number of bytes of host memory used +host_seconds 5866.94 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 65088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 236130432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63765312 # Number of bytes read from this memory -system.physmem.bytes_read::total 299960832 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65088 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104600704 # Number of bytes written to this memory -system.physmem.bytes_written::total 104600704 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1017 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3689538 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 996333 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4686888 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1634386 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1634386 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 82647 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 299832869 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 80967693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 380883210 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 82647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 82647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 132819514 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 132819514 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 132819514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 82647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 299832869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 80967693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 513702723 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4686888 # Number of read requests accepted -system.physmem.writeReqs 1634386 # Number of write requests accepted -system.physmem.readBursts 4686888 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1634386 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 299458048 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 502784 # Total number of bytes read from write queue -system.physmem.bytesWritten 104597376 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 299960832 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104600704 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7856 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 26 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 65344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 236015808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63804544 # Number of bytes read from this memory +system.physmem.bytes_read::total 299885696 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104593152 # Number of bytes written to this memory +system.physmem.bytes_written::total 104593152 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1021 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3687747 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 996946 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4685714 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1634268 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1634268 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 82941 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 299574808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 80987092 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 380644841 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 82941 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 82941 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 132760062 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 132760062 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 132760062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 82941 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 299574808 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 80987092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 513404904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4685714 # Number of read requests accepted +system.physmem.writeReqs 1634268 # Number of write requests accepted +system.physmem.readBursts 4685714 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1634268 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 299374336 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 511360 # Total number of bytes read from write queue +system.physmem.bytesWritten 104589440 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 299885696 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104593152 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7990 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 28 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 302302 # Per bank write bursts -system.physmem.perBankRdBursts::1 301952 # Per bank write bursts -system.physmem.perBankRdBursts::2 285792 # Per bank write bursts -system.physmem.perBankRdBursts::3 288384 # Per bank write bursts -system.physmem.perBankRdBursts::4 288196 # Per bank write bursts -system.physmem.perBankRdBursts::5 285903 # Per bank write bursts -system.physmem.perBankRdBursts::6 281854 # Per bank write bursts -system.physmem.perBankRdBursts::7 277846 # Per bank write bursts -system.physmem.perBankRdBursts::8 294690 # Per bank write bursts -system.physmem.perBankRdBursts::9 300083 # Per bank write bursts -system.physmem.perBankRdBursts::10 291836 # Per bank write bursts -system.physmem.perBankRdBursts::11 298648 # Per bank write bursts -system.physmem.perBankRdBursts::12 299589 # Per bank write bursts -system.physmem.perBankRdBursts::13 298339 # Per bank write bursts -system.physmem.perBankRdBursts::14 293778 # Per bank write bursts -system.physmem.perBankRdBursts::15 289840 # Per bank write bursts -system.physmem.perBankWrBursts::0 103932 # Per bank write bursts -system.physmem.perBankWrBursts::1 101641 # Per bank write bursts -system.physmem.perBankWrBursts::2 99135 # Per bank write bursts -system.physmem.perBankWrBursts::3 99721 # Per bank write bursts -system.physmem.perBankWrBursts::4 98850 # Per bank write bursts -system.physmem.perBankWrBursts::5 98703 # Per bank write bursts -system.physmem.perBankWrBursts::6 102612 # Per bank write bursts -system.physmem.perBankWrBursts::7 104045 # Per bank write bursts -system.physmem.perBankWrBursts::8 105476 # Per bank write bursts -system.physmem.perBankWrBursts::9 104249 # Per bank write bursts -system.physmem.perBankWrBursts::10 101862 # Per bank write bursts -system.physmem.perBankWrBursts::11 102612 # Per bank write bursts -system.physmem.perBankWrBursts::12 102593 # Per bank write bursts -system.physmem.perBankWrBursts::13 102283 # Per bank write bursts -system.physmem.perBankWrBursts::14 104155 # Per bank write bursts -system.physmem.perBankWrBursts::15 102465 # Per bank write bursts +system.physmem.perBankRdBursts::0 301500 # Per bank write bursts +system.physmem.perBankRdBursts::1 301960 # Per bank write bursts +system.physmem.perBankRdBursts::2 285447 # Per bank write bursts +system.physmem.perBankRdBursts::3 288137 # Per bank write bursts +system.physmem.perBankRdBursts::4 288946 # Per bank write bursts +system.physmem.perBankRdBursts::5 285921 # Per bank write bursts +system.physmem.perBankRdBursts::6 281288 # Per bank write bursts +system.physmem.perBankRdBursts::7 278400 # Per bank write bursts +system.physmem.perBankRdBursts::8 294011 # Per bank write bursts +system.physmem.perBankRdBursts::9 300115 # Per bank write bursts +system.physmem.perBankRdBursts::10 292046 # Per bank write bursts +system.physmem.perBankRdBursts::11 297684 # Per bank write bursts +system.physmem.perBankRdBursts::12 299531 # Per bank write bursts +system.physmem.perBankRdBursts::13 298464 # Per bank write bursts +system.physmem.perBankRdBursts::14 294115 # Per bank write bursts +system.physmem.perBankRdBursts::15 290159 # Per bank write bursts +system.physmem.perBankWrBursts::0 103775 # Per bank write bursts +system.physmem.perBankWrBursts::1 101738 # Per bank write bursts +system.physmem.perBankWrBursts::2 99347 # Per bank write bursts +system.physmem.perBankWrBursts::3 99748 # Per bank write bursts +system.physmem.perBankWrBursts::4 99113 # Per bank write bursts +system.physmem.perBankWrBursts::5 98946 # Per bank write bursts +system.physmem.perBankWrBursts::6 102275 # Per bank write bursts +system.physmem.perBankWrBursts::7 103989 # Per bank write bursts +system.physmem.perBankWrBursts::8 105110 # Per bank write bursts +system.physmem.perBankWrBursts::9 104316 # Per bank write bursts +system.physmem.perBankWrBursts::10 101973 # Per bank write bursts +system.physmem.perBankWrBursts::11 102390 # Per bank write bursts +system.physmem.perBankWrBursts::12 102662 # Per bank write bursts +system.physmem.perBankWrBursts::13 102242 # Per bank write bursts +system.physmem.perBankWrBursts::14 104082 # Per bank write bursts +system.physmem.perBankWrBursts::15 102504 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 787540140500 # Total gap between requests +system.physmem.totGap 787835924500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4686888 # Read request sizes (log2) +system.physmem.readPktSize::6 4685714 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1634386 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2728191 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1051856 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 328268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 233236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 157524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 89904 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 39917 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 24410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 17981 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1760 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 828 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 462 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1634268 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2727826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1050681 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 326941 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 233426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 158423 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 90275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 39813 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 24457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 17994 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4464 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1780 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 895 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 261 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -149,42 +149,42 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 24307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 26803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 73031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 84525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 99632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 105756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 106392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 107277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 108481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 109650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 110259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 109107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 102133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 101095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 24253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 26721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 72860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 84494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 99524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 104977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 106319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 107599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 108399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 109635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 109963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 109142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 102277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 101239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see @@ -198,132 +198,134 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4260550 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 94.836056 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.812158 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 102.756680 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3400540 79.81% 79.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 663329 15.57% 95.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 94665 2.22% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 34624 0.81% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22478 0.53% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12365 0.29% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7339 0.17% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5272 0.12% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19938 0.47% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4260550 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 97975 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.757050 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 99.440701 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 95549 97.52% 97.52% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 1198 1.22% 98.75% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 700 0.71% 99.46% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-1023 381 0.39% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1279 109 0.11% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1535 28 0.03% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1791 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1792-2047 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2304-2559 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2816-3071 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3328-3583 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 4259361 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 94.841028 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.814946 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 102.698820 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3400000 79.82% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 662329 15.55% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 94740 2.22% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35136 0.82% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22172 0.52% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12513 0.29% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7488 0.18% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5149 0.12% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19834 0.47% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4259361 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 98005 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.729004 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 99.044358 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 95588 97.53% 97.53% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 1180 1.20% 98.74% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 706 0.72% 99.46% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 397 0.41% 99.86% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1279 101 0.10% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1535 19 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 5 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1792-2047 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2303 3 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-2815 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-3327 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4608-4863 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 97975 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 97975 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.681133 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.640632 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.211305 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 70258 71.71% 71.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1952 1.99% 73.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 17579 17.94% 91.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 5262 5.37% 97.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1746 1.78% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 657 0.67% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 283 0.29% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 119 0.12% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 69 0.07% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 29 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 11 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 8 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 97975 # Writes before turning the bus around for reads -system.physmem.totQLat 162188930459 # Total ticks spent queuing -system.physmem.totMemAccLat 249920780459 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23395160000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34662.92 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 98005 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 98005 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.674761 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.634865 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.202481 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 70360 71.79% 71.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1982 2.02% 73.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 17660 18.02% 91.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 5209 5.32% 97.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1729 1.76% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 596 0.61% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 225 0.23% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 114 0.12% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 71 0.07% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 31 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 17 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 4 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 98005 # Writes before turning the bus around for reads +system.physmem.totQLat 162836208305 # Total ticks spent queuing +system.physmem.totMemAccLat 250543533305 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23388620000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34810.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53412.92 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 380.24 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 132.82 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 380.88 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 132.82 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 53560.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 380.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 132.76 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 380.64 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 132.76 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 4.01 # Data bus utilization in percentage system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.99 # Average write queue length when enqueuing -system.physmem.readRowHits 1713351 # Number of row buffer hits during reads -system.physmem.writeRowHits 339452 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 20.77 # Row buffer hit rate for writes -system.physmem.avgGap 124585.67 # Average gap between requests +system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing +system.physmem.readRowHits 1712017 # Number of row buffer hits during reads +system.physmem.writeRowHits 340548 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 20.84 # Row buffer hit rate for writes +system.physmem.avgGap 124657.94 # Average gap between requests system.physmem.pageHitRate 32.52 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 15118214580 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8035491255 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16509315060 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4221095580 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 59433229440.000015 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64449448560 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1619596800 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 222781261830 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 36127794240 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 16128721335 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 444435904680 # Total energy per rank (pJ) -system.physmem_0.averagePower 564.334256 # Core power per rank (mW) -system.physmem_0.totalIdleTime 641954026654 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 1425644900 # Time in different power states -system.physmem_0.memoryStateTime::REF 25162536000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 59321643250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 94080310817 # Time in different power states -system.physmem_0.memoryStateTime::ACT 118997964696 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 488552081837 # Time in different power states -system.physmem_1.actEnergy 15302205240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8133295995 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 16898973420 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4310127900 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 58889273040.000015 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 64896379290 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1612760640 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 219232237770 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 35640720960 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 18160779360 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 443087552175 # Total energy per rank (pJ) -system.physmem_1.averagePower 562.622143 # Core power per rank (mW) -system.physmem_1.totalIdleTime 640996653350 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 1453270191 # Time in different power states -system.physmem_1.memoryStateTime::REF 24933432000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 67412776000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 92813399032 # Time in different power states -system.physmem_1.memoryStateTime::ACT 120155386459 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 480771917818 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 286296319 # Number of BP lookups -system.cpu.branchPred.condPredicted 223413056 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14631953 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 158681776 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150365310 # Number of BTB hits +system.physmem_0.actEnergy 15118935720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8035889730 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16504816860 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4222619820 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 59457815040.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 64415436660 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1624122240 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 222796740750 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 36224267040 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 16152645360 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 444563646270 # Total energy per rank (pJ) +system.physmem_0.averagePower 564.284526 # Core power per rank (mW) +system.physmem_0.totalIdleTime 642315388170 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 1436139102 # Time in different power states +system.physmem_0.memoryStateTime::REF 25173062000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 59398115500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 94331998561 # Time in different power states +system.physmem_0.memoryStateTime::ACT 118911366978 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 488585283359 # Time in different power states +system.physmem_1.actEnergy 15292958940 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8128385265 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 16894132500 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4307956380 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 58918161120.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 64834688190 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1616111040 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 219342669570 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 35641510560 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 18222503400 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 443208649005 # Total energy per rank (pJ) +system.physmem_1.averagePower 562.564626 # Core power per rank (mW) +system.physmem_1.totalIdleTime 641423107931 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 1455389769 # Time in different power states +system.physmem_1.memoryStateTime::REF 24945910000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 67593570250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 92814429154 # Time in different power states +system.physmem_1.memoryStateTime::ACT 120009883050 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 481016783277 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 286288991 # Number of BP lookups +system.cpu.branchPred.condPredicted 223379889 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14638803 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 157014468 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150316303 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.759029 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16643535 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 63 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3038 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 1928 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1110 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 135 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 95.734046 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16636731 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3547 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2042 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1505 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -353,7 +355,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -383,7 +385,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -413,7 +415,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -444,133 +446,133 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 787540181500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1575080364 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 787835965500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1575671932 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13929690 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067600144 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286296319 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 167010773 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1546402654 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29288795 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 390 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 943 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656982335 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 916 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1574978074 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.406414 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.233446 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13942337 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067450540 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286288991 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166955076 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1546978368 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29302455 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 311 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 1029 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656906223 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 925 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1575573272 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.405744 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.233501 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 492512848 31.27% 31.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465448024 29.55% 60.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101428874 6.44% 67.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515588328 32.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 493163312 31.30% 31.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465492881 29.54% 60.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101391668 6.44% 67.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515525411 32.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1574978074 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.181766 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.312695 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74681637 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 577546655 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849949420 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58156641 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14643721 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42204470 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 713 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037236907 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52506596 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14643721 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139754890 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 492363005 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15806 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837855661 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 90344991 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976429927 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26743123 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45374465 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 126519 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1703162 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 29238118 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985901380 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9128373257 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432925820 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 137 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1575573272 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.181693 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.312107 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74679257 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 578142352 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849952798 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58148325 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14650540 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 135611620 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 746 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037153887 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52516232 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14650540 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139761664 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 493000122 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16309 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837842196 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 90302441 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976324662 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26749907 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45308958 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 126668 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1624936 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 29276583 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985726338 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9127758695 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432766069 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 161 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 311002435 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 176 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 310827393 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 177 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 174 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111413296 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542580071 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199306810 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26873371 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29046971 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1948011764 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 231 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857503284 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13502415 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 283979579 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 647409512 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1574978074 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.179384 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.151840 # Number of insts issued each cycle +system.cpu.rename.skidInsts 111376144 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542477238 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199268014 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26870545 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28963209 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1947887828 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 229 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1857408251 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13517769 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 283855641 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 647022412 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 59 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1575573272 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.178878 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.151815 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 622116780 39.50% 39.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 325952300 20.70% 60.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378187133 24.01% 84.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219716912 13.95% 98.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28998763 1.84% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6186 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 622703787 39.52% 39.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 326030740 20.69% 60.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378156304 24.00% 84.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219671219 13.94% 98.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 29004864 1.84% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6358 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1574978074 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1575573272 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166073423 40.98% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2008 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191445503 47.24% 88.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47741848 11.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166096777 40.98% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2401 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191354081 47.22% 88.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47812478 11.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 19 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 31 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 28 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138255860 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 800923 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138249696 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 803001 0.04% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -594,90 +596,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 30 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 34 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532128426 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186317966 10.03% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 33 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532063614 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186291823 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 37 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 24 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857503284 # Type of FU issued -system.cpu.iq.rate 1.179307 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405262832 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218176 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5708749627 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2232004447 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805721857 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 262 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 240 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 70 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262765960 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 156 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17817152 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857408251 # Type of FU issued +system.cpu.iq.rate 1.178804 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405265784 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218189 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5709173052 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2231756417 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805664221 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 275 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 288 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 75 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262673874 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 161 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17815816 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84273737 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66671 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13339 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24459765 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84170904 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66799 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13274 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24420969 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4534666 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4848313 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4535474 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4852528 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14643721 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25440287 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1476217 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1948012141 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14650540 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25426885 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1470128 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1947888203 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542580071 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199306810 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 169 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159536 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1315183 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13339 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7701795 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8704622 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16406417 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827836046 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516947496 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29667238 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 542477238 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199268014 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 167 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 159099 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1309527 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13274 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7696809 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8718333 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16415142 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827780120 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516898840 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29628131 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 146 # number of nop insts executed -system.cpu.iew.exec_refs 698700973 # number of memory reference insts executed -system.cpu.iew.exec_branches 229547821 # Number of branches executed -system.cpu.iew.exec_stores 181753477 # Number of stores executed -system.cpu.iew.exec_rate 1.160472 # Inst execution rate -system.cpu.iew.wb_sent 1808752239 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805721927 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169243033 # num instructions producing a value -system.cpu.iew.wb_consumers 1689661119 # num instructions consuming a value -system.cpu.iew.wb_rate 1.146432 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.691999 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 258080144 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 698650840 # number of memory reference insts executed +system.cpu.iew.exec_branches 229565077 # Number of branches executed +system.cpu.iew.exec_stores 181752000 # Number of stores executed +system.cpu.iew.exec_rate 1.160000 # Inst execution rate +system.cpu.iew.wb_sent 1808693799 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805664296 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169145221 # num instructions producing a value +system.cpu.iew.wb_consumers 1689395973 # num instructions consuming a value +system.cpu.iew.wb_rate 1.145965 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692049 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 257953466 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14631277 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1535484809 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.083718 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.009601 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14638116 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1536081048 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.083297 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.009309 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 955186516 62.21% 62.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250636789 16.32% 78.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110101292 7.17% 85.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55286350 3.60% 89.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29268667 1.91% 91.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34069623 2.22% 93.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24728092 1.61% 95.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18117164 1.18% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58090316 3.78% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 955788021 62.22% 62.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250630730 16.32% 78.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110093475 7.17% 85.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55285008 3.60% 89.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29278263 1.91% 91.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34064309 2.22% 93.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24750177 1.61% 95.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18104449 1.18% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58086616 3.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1535484809 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1536081048 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563042 # Number of instructions committed system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -727,78 +729,78 @@ system.cpu.commit.op_class_0::FloatMemWrite 24 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58090316 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3399506472 # The number of ROB reads -system.cpu.rob.rob_writes 3883723576 # The number of ROB writes -system.cpu.timesIdled 829 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 102290 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 58086616 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3399979733 # The number of ROB reads +system.cpu.rob.rob_writes 3883469027 # The number of ROB writes +system.cpu.timesIdled 836 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 98660 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563024 # Number of Instructions Simulated system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.019758 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.019758 # CPI: Total CPI of All Threads -system.cpu.ipc 0.980625 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.980625 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175817673 # number of integer regfile reads -system.cpu.int_regfile_writes 1261583983 # number of integer regfile writes -system.cpu.fp_regfile_reads 40 # number of floating regfile reads -system.cpu.fp_regfile_writes 52 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965793426 # number of cc regfile reads -system.cpu.cc_regfile_writes 551861251 # number of cc regfile writes -system.cpu.misc_regfile_reads 675850688 # number of misc regfile reads +system.cpu.cpi 1.020141 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.020141 # CPI: Total CPI of All Threads +system.cpu.ipc 0.980257 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.980257 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175723378 # number of integer regfile reads +system.cpu.int_regfile_writes 1261531313 # number of integer regfile writes +system.cpu.fp_regfile_reads 42 # number of floating regfile reads +system.cpu.fp_regfile_writes 57 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965468307 # number of cc regfile reads +system.cpu.cc_regfile_writes 551796531 # number of cc regfile writes +system.cpu.misc_regfile_reads 675796862 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 17003339 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.963435 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638067140 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17003851 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.524861 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 82999500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.963435 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999929 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999929 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 17001793 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.963908 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638014747 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17002305 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.525191 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 81846500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.963908 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999930 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999930 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 379 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 367 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335713311 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335713311 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 469350712 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469350712 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168716268 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168716268 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335598455 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335598455 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 469297691 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469297691 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168716899 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168716899 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638066980 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638066980 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638066980 # number of overall hits -system.cpu.dcache.overall_hits::total 638066980 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17417847 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17417847 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3869779 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3869779 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638014590 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638014590 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638014590 # number of overall hits +system.cpu.dcache.overall_hits::total 638014590 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17414213 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17414213 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3869148 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3869148 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21287626 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21287626 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21287628 # number of overall misses -system.cpu.dcache.overall_misses::total 21287628 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 440481080000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 440481080000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 157197656848 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 157197656848 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 217500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 217500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 597678736848 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 597678736848 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 597678736848 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 597678736848 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486768559 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486768559 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 21283361 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21283361 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21283363 # number of overall misses +system.cpu.dcache.overall_misses::total 21283363 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 440649629000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 440649629000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 157410000348 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 157410000348 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 389500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 389500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 598059629348 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 598059629348 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 598059629348 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 598059629348 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486711904 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486711904 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -807,70 +809,70 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659354606 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659354606 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659354608 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659354608 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035783 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022422 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.022422 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659297951 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659297951 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659297953 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659297953 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035779 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035779 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022419 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022419 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032286 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032286 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032286 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032286 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25289.065864 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25289.065864 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40621.869323 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40621.869323 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 54375 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 54375 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28076.345237 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28076.345237 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28076.342599 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28076.342599 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21218402 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3791861 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 939506 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67507 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.584637 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 56.169893 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 17003339 # number of writebacks -system.cpu.dcache.writebacks::total 17003339 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151564 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3151564 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1132202 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1132202 # number of WriteReq MSHR hits +system.cpu.dcache.demand_miss_rate::cpu.data 0.032282 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032282 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032282 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032282 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25304.022008 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25304.022008 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40683.375345 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40683.375345 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 97375 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 97375 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28099.867749 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28099.867749 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28099.865108 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28099.865108 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21246265 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3823077 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 940794 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67416 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.583334 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 56.708749 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 17001793 # number of writebacks +system.cpu.dcache.writebacks::total 17001793 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3149457 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3149457 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1131591 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1131591 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4283766 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4283766 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4283766 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4283766 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266283 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14266283 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737577 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737577 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4281048 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4281048 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4281048 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4281048 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14264756 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14264756 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737557 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737557 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17003860 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17003860 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17003861 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17003861 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 354100253000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 354100253000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 121015069211 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 121015069211 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 17002313 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17002313 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17002314 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17002314 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 354315671500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 354315671500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 121139018143 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 121139018143 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 75000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 75000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 475115322211 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 475115322211 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 475115397211 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 475115397211 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 475454689643 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 475454689643 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 475454764643 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 475454764643 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses @@ -881,400 +883,400 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24820.778685 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24820.778685 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44205.174580 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44205.174580 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24838.537126 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24838.537126 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44250.774739 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44250.774739 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 75000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 75000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27941.615740 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27941.615740 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27941.618507 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27941.618507 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 587 # number of replacements -system.cpu.icache.tags.tagsinuse 445.528749 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656980742 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1074 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 611713.912477 # Average number of references to valid blocks. +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27964.118155 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27964.118155 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27964.120922 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27964.120922 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 591 # number of replacements +system.cpu.icache.tags.tagsinuse 443.744305 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656904625 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1075 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 611074.069767 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 445.528749 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.870173 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.870173 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 487 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 443.744305 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.866688 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.866688 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 484 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 443 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.951172 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313965738 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313965738 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 656980742 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656980742 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656980742 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656980742 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656980742 # number of overall hits -system.cpu.icache.overall_hits::total 656980742 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1590 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1590 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1590 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1590 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1590 # number of overall misses -system.cpu.icache.overall_misses::total 1590 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 127348986 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 127348986 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 127348986 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 127348986 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 127348986 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 127348986 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 656982332 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 656982332 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 656982332 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 656982332 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 656982332 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 656982332 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 438 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1313813517 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1313813517 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 656904625 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 656904625 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 656904625 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 656904625 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 656904625 # number of overall hits +system.cpu.icache.overall_hits::total 656904625 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1596 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1596 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1596 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1596 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1596 # number of overall misses +system.cpu.icache.overall_misses::total 1596 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 121940986 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 121940986 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 121940986 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 121940986 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 121940986 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 121940986 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 656906221 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 656906221 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 656906221 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 656906221 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 656906221 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 656906221 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80093.701887 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 80093.701887 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 80093.701887 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 80093.701887 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 80093.701887 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 80093.701887 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 20708 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 276 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76404.126566 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76404.126566 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76404.126566 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76404.126566 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76404.126566 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76404.126566 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 19802 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 336 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 187 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 110.737968 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 30.666667 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 587 # number of writebacks -system.cpu.icache.writebacks::total 587 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 515 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 515 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 515 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 515 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 515 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 515 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1075 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1075 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1075 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1075 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1075 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1075 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 91881989 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 91881989 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 91881989 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 91881989 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 91881989 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 91881989 # number of overall MSHR miss cycles +system.cpu.icache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 105.893048 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 33.600000 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 591 # number of writebacks +system.cpu.icache.writebacks::total 591 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 520 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 520 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 520 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 520 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 520 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 520 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1076 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1076 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 89957490 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 89957490 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 89957490 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 89957490 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 89957490 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 89957490 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 85471.617674 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 85471.617674 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 85471.617674 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 85471.617674 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 85471.617674 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 85471.617674 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 11608007 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 11635645 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 18478 # number of redundant prefetches already in prefetch queue +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83603.615242 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83603.615242 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83603.615242 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 83603.615242 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83603.615242 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 83603.615242 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 11616550 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 11644306 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 18561 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped -system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4655443 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 4648753 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15870.733376 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 13264824 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4664667 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.843681 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfRemovedFull 1 # number of prefetches dropped due to prefetch queue size +system.cpu.l2cache.prefetcher.pfSpanPage 4655502 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 4647569 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15870.791949 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 13265757 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4663475 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.844608 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15649.436196 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 221.297180 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.955166 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013507 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.968673 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 130 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15784 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 6 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 105 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 19 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 423 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4048 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7174 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2624 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1515 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.007935 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.963379 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 561782498 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 561782498 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 4829115 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 4829115 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 12153582 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 12153582 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1756982 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1756982 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 57 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 57 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11509164 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 11509164 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 57 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 13266146 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13266203 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 57 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 13266146 # number of overall hits -system.cpu.l2cache.overall_hits::total 13266203 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 10 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 10 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 980646 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 980646 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1018 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1018 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2757059 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 2757059 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1018 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3737705 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3738723 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1018 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3737705 # number of overall misses -system.cpu.l2cache.overall_misses::total 3738723 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 212000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 212000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104379369500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 104379369500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 90393500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 90393500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 256509677500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 256509677500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 90393500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 360889047000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 360979440500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 90393500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 360889047000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 360979440500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 4829115 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 4829115 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 12153582 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 12153582 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 10 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 10 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737628 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2737628 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1075 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1075 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266223 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 14266223 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1075 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 17003851 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 17004926 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1075 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 17003851 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 17004926 # number of overall (read+write) accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 15652.012265 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 218.779684 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.955323 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013353 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.968676 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 135 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15771 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 3 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 109 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 23 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4017 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7150 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2693 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1496 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.008240 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962585 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 561731761 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 561731761 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 4837264 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 4837264 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 12143869 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 12143869 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1756642 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1756642 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 54 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 54 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11509702 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 11509702 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 54 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 13266344 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13266398 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 54 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 13266344 # number of overall hits +system.cpu.l2cache.overall_hits::total 13266398 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 980963 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 980963 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1022 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1022 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2754998 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 2754998 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1022 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3735961 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3736983 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1022 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3735961 # number of overall misses +system.cpu.l2cache.overall_misses::total 3736983 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 191500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 191500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104504427500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 104504427500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 88486500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 88486500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 256725449000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 256725449000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 88486500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 361229876500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 361318363000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 88486500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 361229876500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 361318363000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 4837264 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 4837264 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 12143869 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 12143869 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 9 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 9 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737605 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2737605 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1076 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1076 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14264700 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 14264700 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 17002305 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 17003381 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 17002305 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 17003381 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358210 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.358210 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.946977 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.946977 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.193258 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.193258 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.946977 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.219815 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.219861 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.946977 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.219815 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.219861 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21200 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21200 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106439.397601 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106439.397601 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 88795.186640 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 88795.186640 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93037.427745 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93037.427745 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 88795.186640 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96553.646422 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 96551.533906 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 88795.186640 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96553.646422 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 96551.533906 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 318 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358329 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.358329 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.949814 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.949814 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.193134 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.193134 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.949814 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.219733 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.219779 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.949814 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.219733 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.219779 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21277.777778 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21277.777778 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106532.486444 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106532.486444 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 86581.702544 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 86581.702544 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93185.348592 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93185.348592 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86581.702544 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96689.948450 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 96687.184020 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86581.702544 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96689.948450 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 96687.184020 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 159 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 58324 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 1634386 # number of writebacks -system.cpu.l2cache.writebacks::total 1634386 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3928 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 3928 # number of ReadExReq MSHR hits +system.cpu.l2cache.unused_prefetches 58080 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 1634268 # number of writebacks +system.cpu.l2cache.writebacks::total 1634268 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3942 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 3942 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45589 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45589 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45595 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45595 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 49517 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 49518 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 49537 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 49538 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 49517 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 49518 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1196489 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 1196489 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 976718 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 976718 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1017 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1017 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2711470 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2711470 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1017 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3688188 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3689205 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1017 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3688188 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1196489 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 4885694 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 84134366845 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 84134366845 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 152000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 152000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98135216000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98135216000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 84211500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 84211500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 237209473000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 237209473000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 84211500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 335344689000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 335428900500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 84211500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 335344689000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 84134366845 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 419563267345 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_hits::cpu.data 49537 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 49538 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1199044 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 1199044 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 977021 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 977021 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1021 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1021 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2709403 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2709403 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1021 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3686424 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3687445 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1021 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3686424 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1199044 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4886489 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 84363300436 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 84363300436 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 137500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 137500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98257390500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98257390500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 82266500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 82266500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 237433882500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 237433882500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 82266500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 335691273000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 335773539500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 82266500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 335691273000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 84363300436 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 420136839936 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356775 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356775 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.946047 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.190062 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.190062 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216903 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216949 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216903 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356889 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356889 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.948885 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.948885 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189938 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189938 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.948885 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216819 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216865 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.948885 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216819 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.287311 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70317.710271 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 70317.710271 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15200 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15200 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 100474.462434 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 100474.462434 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82803.834808 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82803.834808 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87483.716582 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87483.716582 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82803.834808 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 90923.968355 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90921.729885 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82803.834808 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 90923.968355 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70317.710271 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85875.879117 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 34008864 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 17003947 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21229 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 200156 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 200155 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.287383 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70358.802876 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 70358.802876 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15277.777778 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15277.777778 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 100568.350629 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 100568.350629 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 80574.436827 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 80574.436827 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87633.283974 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87633.283974 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 80574.436827 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91061.492926 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91058.589213 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 80574.436827 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91061.492926 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70358.802876 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85979.286956 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 34005774 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17002402 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21251 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 202098 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 202097 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 14267297 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 6463501 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 12174811 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 3014367 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1493474 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737628 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737628 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1075 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266223 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2736 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51011077 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 51013813 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176461184 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2176567488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 6142243 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 104601728 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 23147163 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009565 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.097331 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 14265775 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 6471532 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 12165120 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 3013301 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1495847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 14 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 9 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 9 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737605 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737605 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1076 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 14264700 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2742 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51006435 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 51009177 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176263168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2176369792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 6143430 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 104594048 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 23146806 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009650 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.097758 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 22925769 99.04% 99.04% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 221393 0.96% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 22923448 99.04% 99.04% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 223357 0.96% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 23147163 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 34008359033 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 23146806 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 34005271029 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 24049 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 21045 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1612497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1613498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25505785487 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 25503465992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 9335651 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 4669993 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 9333292 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 4668829 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 3710005 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1634386 # Transaction distribution -system.membus.trans_dist::CleanEvict 3014367 # Transaction distribution -system.membus.trans_dist::UpgradeReq 10 # Transaction distribution -system.membus.trans_dist::ReadExReq 976882 # Transaction distribution -system.membus.trans_dist::ReadExResp 976882 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3710006 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14022538 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14022538 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404561472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 404561472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 3708542 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1634268 # Transaction distribution +system.membus.trans_dist::CleanEvict 3013301 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9 # Transaction distribution +system.membus.trans_dist::ReadExReq 977171 # Transaction distribution +system.membus.trans_dist::ReadExResp 977171 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3708543 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14019005 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14019005 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404478784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 404478784 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 4686898 # Request fanout histogram +system.membus.snoop_fanout::samples 4685723 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4686898 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4685723 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4686898 # Request fanout histogram -system.membus.reqLayer0.occupancy 17643111757 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4685723 # Request fanout histogram +system.membus.reqLayer0.occupancy 17639856241 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 25454576781 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 25447920698 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index f4cf26547..aa0694fe0 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.132539 # Number of seconds simulated -sim_ticks 132538562500 # Number of ticks simulated -final_tick 132538562500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.132570 # Number of seconds simulated +sim_ticks 132570000500 # Number of ticks simulated +final_tick 132570000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 360845 # Simulator instruction rate (inst/s) -host_op_rate 380389 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 277544932 # Simulator tick rate (ticks/s) -host_mem_usage 274852 # Number of bytes of host memory used -host_seconds 477.54 # Real time elapsed on the host +host_inst_rate 373440 # Simulator instruction rate (inst/s) +host_op_rate 393666 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 287300012 # Simulator tick rate (ticks/s) +host_mem_usage 274936 # Number of bytes of host memory used +host_seconds 461.43 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 138240 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory system.physmem.bytes_read::total 247552 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 138240 # Nu system.physmem.num_reads::cpu.inst 2160 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory system.physmem.num_reads::total 3868 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1043017 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 824756 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1867773 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1043017 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1043017 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1043017 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 824756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1867773 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1042770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 824561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1867330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1042770 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1042770 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1042770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 824561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1867330 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 3868 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 3868 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 132538461500 # Total gap between requests +system.physmem.totGap 132569899500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 239 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -189,24 +189,24 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 928 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 265.103448 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.439776 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 277.287318 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 274 29.53% 29.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 366 39.44% 68.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 89 9.59% 78.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 57 6.14% 84.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 24 2.59% 87.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 19 2.05% 89.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 18 1.94% 91.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 18 1.94% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 63 6.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.513478 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 277.064139 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 273 29.42% 29.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 364 39.22% 68.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 95 10.24% 78.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 53 5.71% 84.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 24 2.59% 87.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 21 2.26% 89.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 18 1.94% 91.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 18 1.94% 93.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 62 6.68% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 928 # Bytes accessed per row activation -system.physmem.totQLat 84421250 # Total ticks spent queuing -system.physmem.totMemAccLat 156946250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 82551750 # Total ticks spent queuing +system.physmem.totMemAccLat 155076750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19340000 # Total ticks spent in databus transfers -system.physmem.avgQLat 21825.56 # Average queueing delay per DRAM burst +system.physmem.avgQLat 21342.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40575.56 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 40092.23 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.87 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.87 # Average system read bandwidth in MiByte/s @@ -221,62 +221,62 @@ system.physmem.readRowHits 2935 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 75.88 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34265372.67 # Average gap between requests +system.physmem.avgGap 34273500.39 # Average gap between requests system.physmem.pageHitRate 75.88 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2977380 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1582515 # Energy for precharge commands per rank (pJ) +system.physmem_0.actEnergy 2963100 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1574925 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 14822640 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 159806400.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 56564520 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 6779040 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 507399750 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 193240800 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 31407910590 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 32351114145 # Total energy per rank (pJ) -system.physmem_0.averagePower 244.088313 # Core power per rank (mW) -system.physmem_0.totalIdleTime 132395468250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 11004000 # Time in different power states -system.physmem_0.memoryStateTime::REF 67828000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 130780838250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 503202000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 62983500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 1112706750 # Time in different power states -system.physmem_1.actEnergy 3684240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1939245 # Energy for precharge commands per rank (pJ) +system.physmem_0.refreshEnergy 157347840.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 56147850 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 6612480 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 497768460 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 192585120 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 31420705950 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 32350562865 # Total energy per rank (pJ) +system.physmem_0.averagePower 244.026270 # Core power per rank (mW) +system.physmem_0.totalIdleTime 132428576750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 10716000 # Time in different power states +system.physmem_0.memoryStateTime::REF 66782000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 130836450000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 501553500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 62926000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 1091573000 # Time in different power states +system.physmem_1.actEnergy 3698520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1946835 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 12794880 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 142596480.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 50045430 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 5323200 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 514216380 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 148467840 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 31429438665 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 32308536150 # Total energy per rank (pJ) -system.physmem_1.averagePower 243.767063 # Core power per rank (mW) -system.physmem_1.totalIdleTime 132414854750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 7934000 # Time in different power states -system.physmem_1.memoryStateTime::REF 60464000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 130900584250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 386668500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 55249000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1127662750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 49693791 # Number of BP lookups -system.cpu.branchPred.condPredicted 39499604 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5516746 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24160971 # Number of BTB lookups -system.cpu.branchPred.BTBHits 22899506 # Number of BTB hits +system.physmem_1.refreshEnergy 143211120.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 50027190 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 5428800 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 512852940 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 149734560 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 31437405705 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 32317131480 # Total energy per rank (pJ) +system.physmem_1.averagePower 243.774090 # Core power per rank (mW) +system.physmem_1.totalIdleTime 132446049750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 8198000 # Time in different power states +system.physmem_1.memoryStateTime::REF 60730000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 130931475750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 389968500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 54962000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1124666250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 49693872 # Number of BP lookups +system.cpu.branchPred.condPredicted 39498414 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5520434 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24194736 # Number of BTB lookups +system.cpu.branchPred.BTBHits 22923274 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.778914 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1894448 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 94.744882 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1894785 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 213843 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 208090 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5753 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 40382 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 213909 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 208025 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5884 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 40447 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -306,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -336,7 +336,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -366,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -397,16 +397,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 132538562500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 265077125 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 132570000500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 265140001 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317810 # Number of instructions committed system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11524051 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 11517797 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.538304 # CPI: cycles per instruction -system.cpu.ipc 0.650067 # IPC: instructions per cycle +system.cpu.cpi 1.538669 # CPI: cycles per instruction +system.cpu.ipc 0.649913 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction system.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction @@ -446,18 +446,18 @@ system.cpu.op_class_0::FloatMemWrite 146246 0.08% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 181650743 # Class of committed instruction -system.cpu.tickCycles 256741537 # Number of cycles that the object actually ticked -system.cpu.idleCycles 8335588 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 256807085 # Number of cycles that the object actually ticked +system.cpu.idleCycles 8332916 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1378.587934 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40755397 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1378.592517 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40754461 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22504.360574 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22503.843733 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1378.587934 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.336569 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.336569 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1378.592517 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336570 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336570 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id @@ -465,73 +465,73 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81517417 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81517417 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 28347488 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28347488 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12362633 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12362633 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 81515543 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81515543 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 28346550 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28346550 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12362634 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12362634 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 463 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 463 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40710121 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40710121 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40710583 # number of overall hits -system.cpu.dcache.overall_hits::total 40710583 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 40709184 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40709184 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40709647 # number of overall hits +system.cpu.dcache.overall_hits::total 40709647 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 751 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 751 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1654 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1654 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1653 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1653 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2405 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2405 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2406 # number of overall misses -system.cpu.dcache.overall_misses::total 2406 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 64864500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 64864500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 147460000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 147460000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 212324500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 212324500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 212324500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 212324500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28348239 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28348239 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2404 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2404 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2405 # number of overall misses +system.cpu.dcache.overall_misses::total 2405 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 64086500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 64086500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 146233500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 146233500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 210320000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 210320000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 210320000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 210320000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28347301 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28347301 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 464 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 464 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40712526 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40712526 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40712989 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40712989 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 40711588 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40711588 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40712052 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40712052 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000134 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000134 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002155 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.002155 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000059 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000059 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000059 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 86370.838881 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 86370.838881 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89153.567110 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 89153.567110 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 88284.615385 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 88284.615385 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 88247.921862 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 88247.921862 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 85334.886818 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 85334.886818 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 88465.517241 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 88465.517241 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 87487.520799 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 87487.520799 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 87451.143451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 87451.143451 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -542,12 +542,12 @@ system.cpu.dcache.writebacks::writebacks 16 # nu system.cpu.dcache.writebacks::total 16 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 555 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 555 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 595 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 595 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 595 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 595 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 554 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 554 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 594 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 594 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 594 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 594 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1099 # number of WriteReq MSHR misses @@ -558,162 +558,162 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1810 system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 61185500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 61185500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 100181500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 100181500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 60392000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 60392000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 99618500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 99618500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 77000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 77000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161367000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 161367000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161444000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 161444000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160010500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 160010500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 160087500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 160087500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002155 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002155 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86055.555556 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86055.555556 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91156.960874 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91156.960874 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84939.521800 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84939.521800 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 90644.676979 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 90644.676979 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 77000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 77000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89153.038674 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 89153.038674 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89146.327996 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 89146.327996 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 2864 # number of replacements -system.cpu.icache.tags.tagsinuse 1424.889067 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 70941363 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4663 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15213.674244 # Average number of references to valid blocks. +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88403.591160 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 88403.591160 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88397.294313 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 88397.294313 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 2861 # number of replacements +system.cpu.icache.tags.tagsinuse 1424.892665 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 70991309 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4660 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 15234.186481 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1424.889067 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.695747 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.695747 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1424.892665 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.695748 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.695748 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1799 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 491 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 131 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.878418 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 141896717 # Number of tag accesses -system.cpu.icache.tags.data_accesses 141896717 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 70941363 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 70941363 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 70941363 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 70941363 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 70941363 # number of overall hits -system.cpu.icache.overall_hits::total 70941363 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4664 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4664 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4664 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4664 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4664 # number of overall misses -system.cpu.icache.overall_misses::total 4664 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 236552500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 236552500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 236552500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 236552500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 236552500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 236552500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 70946027 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 70946027 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 70946027 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 70946027 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 70946027 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 70946027 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 141996600 # Number of tag accesses +system.cpu.icache.tags.data_accesses 141996600 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 70991309 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 70991309 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 70991309 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 70991309 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 70991309 # number of overall hits +system.cpu.icache.overall_hits::total 70991309 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4661 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4661 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4661 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4661 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4661 # number of overall misses +system.cpu.icache.overall_misses::total 4661 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 236001500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 236001500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 236001500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 236001500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 236001500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 236001500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 70995970 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 70995970 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 70995970 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 70995970 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 70995970 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 70995970 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50718.803602 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 50718.803602 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 50718.803602 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 50718.803602 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 50718.803602 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 50718.803602 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50633.233212 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 50633.233212 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 50633.233212 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 50633.233212 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 50633.233212 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 50633.233212 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 2864 # number of writebacks -system.cpu.icache.writebacks::total 2864 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4664 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4664 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4664 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4664 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4664 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4664 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 231889500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 231889500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 231889500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 231889500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 231889500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 231889500 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 2861 # number of writebacks +system.cpu.icache.writebacks::total 2861 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4661 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4661 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4661 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4661 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4661 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4661 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 231341500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 231341500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 231341500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 231341500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 231341500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 231341500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49719.018010 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49719.018010 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49719.018010 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 49719.018010 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49719.018010 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 49719.018010 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49633.447758 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49633.447758 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49633.447758 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49633.447758 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49633.447758 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49633.447758 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2835.336724 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5160 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2835.344855 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5154 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3868 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.334023 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.332472 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.638236 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1327.698487 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046009 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.641960 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1327.702895 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046010 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.040518 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.086528 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 3868 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 535 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 534 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 367 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2841 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118042 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 76228 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 76228 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.tag_accesses 76180 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 76180 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 2534 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 2534 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::writebacks 2531 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 2531 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2502 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 2502 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2499 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 2499 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 80 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::total 80 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2502 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 2499 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 88 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2590 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2502 # number of overall hits +system.cpu.l2cache.demand_hits::total 2587 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2499 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 88 # number of overall hits -system.cpu.l2cache.overall_hits::total 2590 # number of overall hits +system.cpu.l2cache.overall_hits::total 2587 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 1091 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 1091 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2162 # number of ReadCleanReq misses @@ -726,58 +726,58 @@ system.cpu.l2cache.demand_misses::total 3885 # nu system.cpu.l2cache.overall_misses::cpu.inst 2162 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1723 # number of overall misses system.cpu.l2cache.overall_misses::total 3885 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 98447500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 98447500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 198239500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 198239500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 59270000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 59270000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 198239500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 157717500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 355957000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 198239500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 157717500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 355957000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 97884500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 97884500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 197728500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 197728500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 58476500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 58476500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 197728500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 156361000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 354089500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 197728500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 156361000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 354089500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 2534 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 2534 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 2531 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 2531 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1099 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1099 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4664 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 4664 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4661 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 4661 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 712 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4664 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 4661 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 1811 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 6475 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4664 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6472 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4661 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1811 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 6475 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 6472 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992721 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.992721 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.463551 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.463551 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.463849 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.463849 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.887640 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.887640 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463551 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463849 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.951408 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.600000 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463551 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.600278 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463849 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951408 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.600000 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90236.021998 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90236.021998 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 91692.645698 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 91692.645698 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93781.645570 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93781.645570 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 91692.645698 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91536.564132 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 91623.423423 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 91692.645698 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91536.564132 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 91623.423423 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.600278 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89719.981668 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89719.981668 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 91456.290472 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 91456.290472 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92526.107595 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92526.107595 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 91456.290472 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90749.274521 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 91142.728443 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 91456.290472 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90749.274521 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 91142.728443 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -806,79 +806,79 @@ system.cpu.l2cache.demand_mshr_misses::total 3869 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2161 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3869 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 87537500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 87537500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 176566000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 176566000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 51432500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 51432500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176566000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 138970000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 315536000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176566000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 138970000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 315536000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 86974500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 86974500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 176055000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 176055000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 50639500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 50639500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176055000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137614000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 313669000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176055000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137614000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 313669000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.463336 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.463634 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.866573 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.866573 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.597529 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.597806 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.597529 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80236.021998 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80236.021998 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 81705.691809 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 81705.691809 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83358.995138 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83358.995138 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 81705.691809 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81364.168618 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81554.923753 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 81705.691809 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81364.168618 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81554.923753 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 9381 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3042 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.597806 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79719.981668 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79719.981668 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 81469.227210 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 81469.227210 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82073.743922 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82073.743922 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 81469.227210 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80570.257611 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81072.370121 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 81469.227210 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80570.257611 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81072.370121 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 9375 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3038 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 336 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 5375 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 5372 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2864 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2861 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1099 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1099 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 4664 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4661 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12191 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12182 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3664 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 15855 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 15846 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481344 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 598656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 598272 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 6475 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.072896 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.259985 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 6472 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.072775 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.259787 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 6003 92.71% 92.71% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 472 7.29% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 6001 92.72% 92.72% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 471 7.28% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6475 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7570500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 6472 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7564500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6994999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6990499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2723985 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) @@ -888,7 +888,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 2777 # Transaction distribution system.membus.trans_dist::ReadExReq 1091 # Transaction distribution system.membus.trans_dist::ReadExResp 1091 # Transaction distribution @@ -909,9 +909,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3868 # Request fanout histogram -system.membus.reqLayer0.occupancy 4518000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4525000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20568250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20564500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 5040af9e4..8786b6479 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.086149 # Number of seconds simulated -sim_ticks 86149358000 # Number of ticks simulated -final_tick 86149358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.085986 # Number of seconds simulated +sim_ticks 85986203000 # Number of ticks simulated +final_tick 85986203000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 240669 # Simulator instruction rate (inst/s) -host_op_rate 253706 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 120331720 # Simulator tick rate (ticks/s) -host_mem_usage 272336 # Number of bytes of host memory used -host_seconds 715.93 # Real time elapsed on the host +host_inst_rate 210936 # Simulator instruction rate (inst/s) +host_op_rate 222361 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 105265513 # Simulator tick rate (ticks/s) +host_mem_usage 272504 # Number of bytes of host memory used +host_seconds 816.85 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 652096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 192896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 71744 # Number of bytes read from this memory -system.physmem.bytes_read::total 916736 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 652096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 652096 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 10189 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3014 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1121 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14324 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 7569366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2239088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 832786 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10641240 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7569366 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7569366 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7569366 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2239088 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 832786 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10641240 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 14324 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 651776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 193408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 71680 # Number of bytes read from this memory +system.physmem.bytes_read::total 916864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 651776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 651776 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 10184 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3022 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1120 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14326 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 7580007 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2249291 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 833622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10662920 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7580007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7580007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7580007 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2249291 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 833622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10662920 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 14327 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 14324 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 14327 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 916736 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 916928 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 916736 # Total read bytes from the system interface side +system.physmem.bytesReadSys 916928 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1375 # Per bank write bursts -system.physmem.perBankRdBursts::1 498 # Per bank write bursts -system.physmem.perBankRdBursts::2 5101 # Per bank write bursts -system.physmem.perBankRdBursts::3 808 # Per bank write bursts -system.physmem.perBankRdBursts::4 2279 # Per bank write bursts -system.physmem.perBankRdBursts::5 424 # Per bank write bursts -system.physmem.perBankRdBursts::6 384 # Per bank write bursts -system.physmem.perBankRdBursts::7 628 # Per bank write bursts +system.physmem.perBankRdBursts::0 1379 # Per bank write bursts +system.physmem.perBankRdBursts::1 501 # Per bank write bursts +system.physmem.perBankRdBursts::2 5100 # Per bank write bursts +system.physmem.perBankRdBursts::3 815 # Per bank write bursts +system.physmem.perBankRdBursts::4 2265 # Per bank write bursts +system.physmem.perBankRdBursts::5 427 # Per bank write bursts +system.physmem.perBankRdBursts::6 394 # Per bank write bursts +system.physmem.perBankRdBursts::7 623 # Per bank write bursts system.physmem.perBankRdBursts::8 270 # Per bank write bursts -system.physmem.perBankRdBursts::9 231 # Per bank write bursts +system.physmem.perBankRdBursts::9 230 # Per bank write bursts system.physmem.perBankRdBursts::10 354 # Per bank write bursts -system.physmem.perBankRdBursts::11 348 # Per bank write bursts -system.physmem.perBankRdBursts::12 320 # Per bank write bursts -system.physmem.perBankRdBursts::13 267 # Per bank write bursts -system.physmem.perBankRdBursts::14 240 # Per bank write bursts -system.physmem.perBankRdBursts::15 797 # Per bank write bursts +system.physmem.perBankRdBursts::11 345 # Per bank write bursts +system.physmem.perBankRdBursts::12 321 # Per bank write bursts +system.physmem.perBankRdBursts::13 266 # Per bank write bursts +system.physmem.perBankRdBursts::14 239 # Per bank write bursts +system.physmem.perBankRdBursts::15 798 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 86149299500 # Total gap between requests +system.physmem.totGap 85986194000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 14324 # Read request sizes (log2) +system.physmem.readPktSize::6 14327 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,15 +95,15 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 12783 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1071 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 12781 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1074 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 181 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 85 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see @@ -191,29 +191,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 8487 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.956168 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 86.535791 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 122.736079 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 5894 69.45% 69.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 2098 24.72% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 256 3.02% 97.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 63 0.74% 97.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 36 0.42% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 32 0.38% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 19 0.22% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 8483 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.969350 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 86.508882 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 122.734500 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 5897 69.52% 69.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 2092 24.66% 94.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 251 2.96% 97.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 65 0.77% 97.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 38 0.45% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 36 0.42% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 15 0.18% 98.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 10 0.12% 99.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 79 0.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 8487 # Bytes accessed per row activation -system.physmem.totQLat 1500750524 # Total ticks spent queuing -system.physmem.totMemAccLat 1769325524 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 71620000 # Total ticks spent in databus transfers -system.physmem.avgQLat 104771.75 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::total 8483 # Bytes accessed per row activation +system.physmem.totQLat 1497477800 # Total ticks spent queuing +system.physmem.totMemAccLat 1766109050 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 71635000 # Total ticks spent in databus transfers +system.physmem.avgQLat 104521.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 123521.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 10.64 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 123271.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 10.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 10.64 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 10.66 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.08 # Data bus utilization in percentage @@ -221,66 +221,66 @@ system.physmem.busUtilRead 0.08 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5833 # Number of row buffer hits during reads +system.physmem.readRowHits 5838 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.72 # Row buffer hit rate for reads +system.physmem.readRowHitRate 40.75 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 6014332.55 # Average gap between requests -system.physmem.pageHitRate 40.72 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 51543660 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 27384720 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 82088580 # Energy for read commands per rank (pJ) +system.physmem.avgGap 6001688.70 # Average gap between requests +system.physmem.pageHitRate 40.75 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 51557940 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 27392310 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 82138560 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5186946960.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1121176890 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 276161760 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 12273342600 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 8346662400 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 9294814230 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 36662152740 # Total energy per rank (pJ) -system.physmem_0.averagePower 425.565010 # Core power per rank (mW) -system.physmem_0.totalIdleTime 82965211526 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 532687000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2205840000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 34315599752 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 21736059604 # Time in different power states -system.physmem_0.memoryStateTime::ACT 443979474 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 26915192170 # Time in different power states -system.physmem_1.actEnergy 9082080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4823445 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20184780 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 5188176240.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1121049780 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 275286240 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 12230933460 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8389841280 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 9251896980 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 36621408690 # Total energy per rank (pJ) +system.physmem_0.averagePower 425.898657 # Core power per rank (mW) +system.physmem_0.totalIdleTime 82802255264 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 532741000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2206324000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 34133171250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 21848572364 # Time in different power states +system.physmem_0.memoryStateTime::ACT 443169236 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 26822225150 # Time in different power states +system.physmem_1.actEnergy 9046380 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4800675 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20149080 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 883852320.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 198703710 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 50905920 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 1989700140 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 1383894720 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 18830063895 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 23371485780 # Total energy per rank (pJ) -system.physmem_1.averagePower 271.290305 # Core power per rank (mW) -system.physmem_1.totalIdleTime 85580460271 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 101384000 # Time in different power states -system.physmem_1.memoryStateTime::REF 376118000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 77613150500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 3603890386 # Time in different power states -system.physmem_1.memoryStateTime::ACT 91368979 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 4363446135 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 85639426 # Number of BP lookups -system.cpu.branchPred.condPredicted 68185953 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5937258 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 39949340 # Number of BTB lookups -system.cpu.branchPred.BTBHits 38185565 # Number of BTB hits +system.physmem_1.refreshEnergy 880164480.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 198118890 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 50592480 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 1982659500 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 1381296480 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 18795083175 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 23322152130 # Total energy per rank (pJ) +system.physmem_1.averagePower 271.231327 # Core power per rank (mW) +system.physmem_1.totalIdleTime 85419499755 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 100592000 # Time in different power states +system.physmem_1.memoryStateTime::REF 374546000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 77474388250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 3597111150 # Time in different power states +system.physmem_1.memoryStateTime::ACT 91565245 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 4348000355 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 85644201 # Number of BP lookups +system.cpu.branchPred.condPredicted 68263451 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5948841 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 39900262 # Number of BTB lookups +system.cpu.branchPred.BTBHits 38156956 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.584971 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3683095 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81909 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 681696 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 653573 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 28123 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 40352 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 95.630841 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3658994 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81907 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 654149 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 629298 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 24851 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 40566 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -310,7 +310,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -340,7 +340,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -370,7 +370,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -401,242 +401,242 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 86149358000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 172298717 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 85986203000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 171972407 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5689617 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 347266831 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85639426 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42522233 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158380748 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11888463 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 4145 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5684699 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 346733793 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85644201 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42445248 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158074641 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11911485 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 4331 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 80 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 4281 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78346664 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 18062 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 170023102 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.137102 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.057569 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 4750 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78152122 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 17905 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169724243 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.137034 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.057596 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 18318468 10.77% 10.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30068726 17.69% 28.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31619725 18.60% 47.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 90016183 52.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18311667 10.79% 10.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29948653 17.65% 28.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31633861 18.64% 47.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 89830062 52.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 170023102 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.497040 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.015493 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17554244 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 18101467 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 121824905 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6773054 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5769432 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11065775 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 189948 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 305038109 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27237354 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5769432 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37539679 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8956907 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 601126 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108322423 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8833535 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 277447852 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13184486 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3097243 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 842563 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2612762 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 40533 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 26849 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 481448776 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1187920227 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 296497585 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3005089 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 169724243 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.498011 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.016218 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17545924 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 18077628 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 121579812 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6764631 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5756248 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 32661376 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 214759 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 304427843 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27289068 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5756248 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37507593 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8946109 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 602389 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108088153 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8823751 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 276998119 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13097154 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3089202 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 850461 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2596711 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 40764 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 26854 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 480912034 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1185877305 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 296009785 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3004340 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 188471847 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23626 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23625 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13449474 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 33921609 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14424624 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2552614 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1816807 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 263824183 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45978 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214443460 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5190288 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 82234207 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 216932052 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 762 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 170023102 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.261261 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.018489 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 187935105 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23572 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23567 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13428642 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 33801265 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14384966 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2539582 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1819756 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 263460878 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45929 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214221426 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5142742 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 81870853 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 215931448 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 713 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169724243 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.262173 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.018049 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 53215331 31.30% 31.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36043504 21.20% 52.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65536118 38.55% 91.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13631246 8.02% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1550810 0.91% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 45816 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 277 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 53012533 31.23% 31.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36041444 21.24% 52.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65469642 38.57% 91.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13608265 8.02% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1546158 0.91% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 45935 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 266 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 170023102 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169724243 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35671391 66.13% 66.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 153271 0.28% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1065 0.00% 66.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35712 0.07% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 263 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 556 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 40135 0.07% 66.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 13909773 25.79% 92.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3850022 7.14% 99.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 142020 0.26% 99.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 136319 0.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35637562 66.14% 66.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 153239 0.28% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1065 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35742 0.07% 66.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 263 0.00% 66.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 559 0.00% 66.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 40182 0.07% 66.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 13886588 25.77% 92.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3846845 7.14% 99.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 141772 0.26% 99.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 136229 0.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167011334 77.88% 77.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 919426 0.43% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33015 0.02% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165180 0.08% 78.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245708 0.11% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460349 0.21% 78.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206623 0.10% 78.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 318 0.00% 78.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 31296412 14.59% 93.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13233182 6.17% 99.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 576648 0.27% 99.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 147624 0.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 166877725 77.90% 77.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 919560 0.43% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33017 0.02% 78.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165187 0.08% 78.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245719 0.11% 78.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460300 0.21% 78.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206641 0.10% 78.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 318 0.00% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 31220842 14.57% 93.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13220710 6.17% 99.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 576371 0.27% 99.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 147395 0.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214443460 # Type of FU issued -system.cpu.iq.rate 1.244603 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53940732 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.251538 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654047721 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344100630 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204290427 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3993321 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2010682 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806323 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266209914 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2174278 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1590245 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214221426 # Type of FU issued +system.cpu.iq.rate 1.245673 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53880251 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.251517 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653198075 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 343375917 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204156399 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3992013 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2008700 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806249 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 265928183 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2173494 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1586831 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6025465 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7430 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7094 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1779990 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5905121 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6947 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7000 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1740332 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25605 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 790 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25012 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 810 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5769432 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5627104 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 174387 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 263890272 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5756248 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5611049 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 173372 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 263527171 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 33921609 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14424624 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23570 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3854 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 167353 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7094 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3148097 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3247402 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6395499 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207161825 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30639651 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7281635 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 33801265 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14384966 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23521 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3789 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 166382 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7000 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3130012 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3255540 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6385552 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 206995589 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30591856 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7225837 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 20111 # number of nop insts executed -system.cpu.iew.exec_refs 43786600 # number of memory reference insts executed -system.cpu.iew.exec_branches 44861358 # Number of branches executed -system.cpu.iew.exec_stores 13146949 # Number of stores executed -system.cpu.iew.exec_rate 1.202341 # Inst execution rate -system.cpu.iew.wb_sent 206406222 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206096750 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129381204 # num instructions producing a value -system.cpu.iew.wb_consumers 221650091 # num instructions consuming a value -system.cpu.iew.wb_rate 1.196160 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.583718 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 68697467 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 20364 # number of nop insts executed +system.cpu.iew.exec_refs 43730352 # number of memory reference insts executed +system.cpu.iew.exec_branches 44853428 # Number of branches executed +system.cpu.iew.exec_stores 13138496 # Number of stores executed +system.cpu.iew.exec_rate 1.203656 # Inst execution rate +system.cpu.iew.wb_sent 206269583 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 205962648 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129302452 # num instructions producing a value +system.cpu.iew.wb_consumers 221536410 # num instructions consuming a value +system.cpu.iew.wb_rate 1.197649 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.583662 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 68402964 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5762459 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158721175 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.144462 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.650716 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5749347 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158452610 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.146402 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.651768 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 74120611 46.70% 46.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41150811 25.93% 72.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22560961 14.21% 86.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9504738 5.99% 92.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3552513 2.24% 95.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2129219 1.34% 96.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1299436 0.82% 97.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1012456 0.64% 97.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3390430 2.14% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73893836 46.63% 46.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41104048 25.94% 72.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22555911 14.24% 86.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9496527 5.99% 92.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3557786 2.25% 95.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2129951 1.34% 96.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1320929 0.83% 97.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1010558 0.64% 97.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3383064 2.14% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158721175 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158452610 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317410 # Number of instructions committed system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -686,383 +686,389 @@ system.cpu.commit.op_class_0::FloatMemWrite 146246 0.08% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction -system.cpu.commit.bw_lim_events 3390430 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 405673353 # The number of ROB reads -system.cpu.rob.rob_writes 512011515 # The number of ROB writes -system.cpu.timesIdled 9971 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2275615 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3383064 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 405117651 # The number of ROB reads +system.cpu.rob.rob_writes 511394543 # The number of ROB writes +system.cpu.timesIdled 9924 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2248164 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303022 # Number of Instructions Simulated system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.999975 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.999975 # CPI: Total CPI of All Threads -system.cpu.ipc 1.000025 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.000025 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218762027 # number of integer regfile reads -system.cpu.int_regfile_writes 114194444 # number of integer regfile writes -system.cpu.fp_regfile_reads 2903946 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441681 # number of floating regfile writes -system.cpu.cc_regfile_reads 708323214 # number of cc regfile reads -system.cpu.cc_regfile_writes 229513810 # number of cc regfile writes -system.cpu.misc_regfile_reads 57456345 # number of misc regfile reads +system.cpu.cpi 0.998081 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.998081 # CPI: Total CPI of All Threads +system.cpu.ipc 1.001922 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.001922 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218599432 # number of integer regfile reads +system.cpu.int_regfile_writes 114087616 # number of integer regfile writes +system.cpu.fp_regfile_reads 2903991 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441715 # number of floating regfile writes +system.cpu.cc_regfile_reads 707769294 # number of cc regfile reads +system.cpu.cc_regfile_writes 229397390 # number of cc regfile writes +system.cpu.misc_regfile_reads 57427586 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 72586 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.401008 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41045518 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73098 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 561.513557 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 555248500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.401008 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998830 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998830 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 72391 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.400200 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40997604 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 72903 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 562.358257 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 554902500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.400200 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998829 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998829 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 230 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82389396 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82389396 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 28659277 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28659277 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341322 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341322 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 365 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 365 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22147 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22147 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 82292817 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82292817 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 28611296 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28611296 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341384 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341384 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 362 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 362 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22154 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22154 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41000599 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41000599 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41000964 # number of overall hits -system.cpu.dcache.overall_hits::total 41000964 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89290 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89290 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22965 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22965 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 260 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 260 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 112255 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 112255 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 112371 # number of overall misses -system.cpu.dcache.overall_misses::total 112371 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1989594500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1989594500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 244666499 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 244666499 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2316500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2316500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 2234260999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 2234260999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 2234260999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 2234260999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28748567 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28748567 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40952680 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40952680 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40953042 # number of overall hits +system.cpu.dcache.overall_hits::total 40953042 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89081 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89081 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22903 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22903 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 117 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 117 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 253 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 253 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 111984 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 111984 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112101 # number of overall misses +system.cpu.dcache.overall_misses::total 112101 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1981259500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1981259500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 246570499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 246570499 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2257000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2257000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 2227829999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 2227829999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 2227829999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 2227829999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28700377 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28700377 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 481 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 481 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 479 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 479 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41112854 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41112854 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41113335 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41113335 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003106 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003106 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001857 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001857 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.241164 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.241164 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011604 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011604 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002730 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002730 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002733 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002733 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22282.388845 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22282.388845 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10653.886305 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10653.886305 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8909.615385 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8909.615385 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19903.443045 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19903.443045 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19882.896824 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19882.896824 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 41064664 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41064664 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41065143 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41065143 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003104 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003104 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001852 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001852 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.244259 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.244259 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011291 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011291 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002727 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002727 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002730 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002730 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22241.100796 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22241.100796 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10765.860324 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10765.860324 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8920.948617 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8920.948617 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19894.181303 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19894.181303 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19873.417713 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19873.417713 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 180 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 11152 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 11209 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 864 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 865 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 90 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 12.907407 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 72586 # number of writebacks -system.cpu.dcache.writebacks::total 72586 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24872 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24872 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14398 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 14398 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 260 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 260 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 39270 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 39270 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 39270 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 39270 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64418 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64418 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8567 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8567 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 72985 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 72985 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 73098 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 73098 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1060539500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1060539500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 87795999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 87795999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 969000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 969000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1148335499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 1148335499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1149304499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 1149304499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002241 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002241 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000693 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000693 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.234927 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.234927 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001775 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001775 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001778 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001778 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16463.403086 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16463.403086 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10248.161433 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10248.161433 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8575.221239 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8575.221239 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15733.856258 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15733.856258 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15722.789940 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15722.789940 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 53582 # number of replacements -system.cpu.icache.tags.tagsinuse 510.578561 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78288973 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 54094 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1447.276463 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 85378568500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.578561 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997224 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997224 # Average percentage of cache occupancy +system.cpu.dcache.avg_blocked_cycles::no_targets 12.958382 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 72391 # number of writebacks +system.cpu.dcache.writebacks::total 72391 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24849 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24849 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14345 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14345 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 253 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 253 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 39194 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39194 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39194 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39194 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64232 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64232 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8558 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8558 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 114 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 114 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 72790 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 72790 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 72904 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 72904 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1056234000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1056234000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 88380499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 88380499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 977000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 977000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1144614499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 1144614499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1145591499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 1145591499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002238 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002238 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.237996 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.237996 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001773 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001773 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001775 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001775 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16444.046581 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16444.046581 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10327.237556 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10327.237556 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8570.175439 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8570.175439 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15724.886647 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15724.886647 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15713.698823 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15713.698823 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 53106 # number of replacements +system.cpu.icache.tags.tagsinuse 510.578015 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78094905 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 53618 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1456.505371 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 85215430500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.578015 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997223 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997223 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 49 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 156747350 # Number of tag accesses -system.cpu.icache.tags.data_accesses 156747350 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 78288973 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78288973 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78288973 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78288973 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78288973 # number of overall hits -system.cpu.icache.overall_hits::total 78288973 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 57655 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 57655 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 57655 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 57655 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 57655 # number of overall misses -system.cpu.icache.overall_misses::total 57655 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2247853926 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2247853926 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2247853926 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2247853926 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2247853926 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2247853926 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78346628 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78346628 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78346628 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78346628 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78346628 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78346628 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000736 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000736 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000736 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000736 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000736 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000736 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38988.013633 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 38988.013633 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 38988.013633 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 38988.013633 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 38988.013633 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 38988.013633 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 94468 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 55 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3203 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 29.493600 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 27.500000 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 53582 # number of writebacks -system.cpu.icache.writebacks::total 53582 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3560 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3560 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3560 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3560 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3560 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3560 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54095 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 54095 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 54095 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 54095 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 54095 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 54095 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2052751452 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2052751452 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2052751452 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2052751452 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2052751452 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2052751452 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000690 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000690 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000690 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000690 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000690 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000690 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37947.156891 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37947.156891 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37947.156891 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37947.156891 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37947.156891 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37947.156891 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 9257 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 9257 # number of prefetch candidates identified +system.cpu.icache.tags.tag_accesses 156357779 # Number of tag accesses +system.cpu.icache.tags.data_accesses 156357779 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 78094905 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78094905 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78094905 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78094905 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78094905 # number of overall hits +system.cpu.icache.overall_hits::total 78094905 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 57175 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 57175 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 57175 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 57175 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 57175 # number of overall misses +system.cpu.icache.overall_misses::total 57175 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2239186435 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2239186435 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2239186435 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2239186435 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2239186435 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2239186435 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78152080 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78152080 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78152080 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78152080 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78152080 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78152080 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000732 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000732 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000732 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000732 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000732 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000732 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39163.733013 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 39163.733013 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 39163.733013 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 39163.733013 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 39163.733013 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 39163.733013 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 91615 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 88 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3140 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 29.176752 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 29.333333 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 53106 # number of writebacks +system.cpu.icache.writebacks::total 53106 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3554 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3554 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3554 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3554 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3554 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3554 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 53621 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 53621 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 53621 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 53621 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 53621 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 53621 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2047106952 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2047106952 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2047106952 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2047106952 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2047106952 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2047106952 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000686 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000686 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000686 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38177.336342 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38177.336342 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38177.336342 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 38177.336342 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38177.336342 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 38177.336342 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 9132 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 9132 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 1327 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.pfSpanPage 1308 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1809.107747 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 98955 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2836 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 34.892454 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 1811.625085 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 98153 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2844 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 34.512307 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1727.095683 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 82.012064 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.105414 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005006 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.110419 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 131 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2705 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 1727.578627 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 84.046457 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.105443 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005130 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.110573 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 138 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2706 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::2 46 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 66 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 77 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1127 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 198 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 958 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.007996 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.165100 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4002973 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4002973 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 64701 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 64701 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 50991 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 50991 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 8404 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 8404 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 43901 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 43901 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 61671 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 61671 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 43901 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 70075 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 113976 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 43901 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 70075 # number of overall hits -system.cpu.l2cache.overall_hits::total 113976 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 230 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 230 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10194 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 10194 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2793 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 2793 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 10194 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3023 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 13217 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 10194 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3023 # number of overall misses -system.cpu.l2cache.overall_misses::total 13217 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 20353000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 20353000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1710678000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1710678000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 556147500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 556147500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1710678000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 576500500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2287178500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1710678000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 576500500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2287178500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 64701 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 64701 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 50991 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 50991 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 8634 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 8634 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 54095 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 54095 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64464 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 64464 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 54095 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 73098 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 127193 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 54095 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 73098 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 127193 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.026639 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.026639 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.188446 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.188446 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043327 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043327 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.188446 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.041355 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.103913 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.188446 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.041355 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.103913 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88491.304348 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88491.304348 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 167812.242496 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 167812.242496 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 199121.911923 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 199121.911923 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 167812.242496 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 190704.763480 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 173048.233336 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 167812.242496 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 190704.763480 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 173048.233336 # average overall miss latency +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1128 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 205 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 955 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.008423 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.165161 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3980963 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3980963 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 64558 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 64558 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 50469 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 50469 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8390 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8390 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 43430 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 43430 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 61482 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 61482 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 43430 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 69872 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 113302 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 43430 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 69872 # number of overall hits +system.cpu.l2cache.overall_hits::total 113302 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 236 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 236 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10190 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 10190 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2795 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 2795 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 10190 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3031 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 13221 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 10190 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3031 # number of overall misses +system.cpu.l2cache.overall_misses::total 13221 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 21033000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 21033000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1708556000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1708556000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 553419500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 553419500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1708556000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 574452500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2283008500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1708556000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 574452500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2283008500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 64558 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 64558 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 50469 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 50469 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 8626 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 8626 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 53620 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 53620 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64277 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 64277 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 53620 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 72903 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 126523 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 53620 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 72903 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 126523 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.027359 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.027359 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.190041 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.190041 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043484 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043484 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.190041 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.041576 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.104495 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.190041 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.041576 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.104495 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89122.881356 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89122.881356 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 167669.872424 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 167669.872424 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 198003.398927 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 198003.398927 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 167669.872424 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 189525.734081 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 172680.470464 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 167669.872424 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 189525.734081 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 172680.470464 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1081,136 +1087,147 @@ system.cpu.l2cache.demand_mshr_hits::total 14 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 2048 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 2048 # number of HardPFReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 229 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 229 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10189 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10189 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2785 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2785 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10189 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3014 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 13203 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10189 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3014 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 2048 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15251 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 98123639 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 98123639 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 18771000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 18771000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1648684500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1648684500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 538898000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 538898000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1648684500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 557669000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2206353500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1648684500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 557669000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 98123639 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2304477139 # number of overall MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1986 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 1986 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 235 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 235 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10185 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10185 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2787 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2787 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10185 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3022 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 13207 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10185 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3022 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1986 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15193 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 99174661 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 99174661 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 16000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 16000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 19399000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 19399000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1646592500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1646592500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 536158000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 536158000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1646592500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 555557000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2202149500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1646592500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 555557000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 99174661 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2301324161 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.026523 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.026523 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.188354 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.188354 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043202 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043202 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188354 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.041232 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.103803 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188354 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.041232 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027243 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027243 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.189948 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.189948 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043359 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043359 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.189948 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.041452 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.104384 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.189948 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.041452 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.119904 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47911.933105 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 47911.933105 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81969.432314 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81969.432314 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161810.236530 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161810.236530 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 193500.179533 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 193500.179533 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161810.236530 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185026.211015 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167110.012876 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161810.236530 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185026.211015 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47911.933105 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 151103.346600 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 253361 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 126188 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10476 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 927 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 926 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.120081 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 49936.888721 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 49936.888721 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82548.936170 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82548.936170 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161668.384880 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161668.384880 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 192378.184428 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 192378.184428 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161668.384880 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 183837.524818 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 166741.084273 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161668.384880 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 183837.524818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 49936.888721 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 151472.662476 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 252022 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 125518 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10474 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 866 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 865 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 118558 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 64701 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 61467 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2398 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8634 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8634 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 54095 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 64464 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161771 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218782 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 380553 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6891264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9323776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 16215040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2398 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 129591 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.088154 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.283547 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 117896 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 64558 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 60939 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2337 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8626 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8626 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 53621 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 64277 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 160345 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218199 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 378544 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6830336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9298816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 16129152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2338 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 64 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 128862 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.088172 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.283573 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 118168 91.19% 91.19% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 11422 8.81% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 117501 91.18% 91.18% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11360 8.82% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 129591 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 252848500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 128862 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 251508000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 81149483 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 80437981 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 109651491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 109359491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 14324 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 10483 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 14328 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 10478 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 14094 # Transaction distribution -system.membus.trans_dist::ReadExReq 229 # Transaction distribution -system.membus.trans_dist::ReadExResp 229 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 14095 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28647 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28647 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 916672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 916672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 14090 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 235 # Transaction distribution +system.membus.trans_dist::ReadExResp 235 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 14092 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28653 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28653 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 916800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 916800 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 14324 # Request fanout histogram +system.membus.snoop_fanout::samples 14328 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 14324 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 14328 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 14324 # Request fanout histogram -system.membus.reqLayer0.occupancy 18004660 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 14328 # Request fanout histogram +system.membus.reqLayer0.occupancy 18011178 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 77243027 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 77254535 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 4554501a1..059c65964 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.103324 # Number of seconds simulated -sim_ticks 103323995500 # Number of ticks simulated -final_tick 103323995500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.102721 # Number of seconds simulated +sim_ticks 102721386000 # Number of ticks simulated +final_tick 102721386000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113414 # Simulator instruction rate (inst/s) -host_op_rate 190092 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 88727502 # Simulator tick rate (ticks/s) -host_mem_usage 308112 # Number of bytes of host memory used -host_seconds 1164.51 # Real time elapsed on the host +host_inst_rate 115023 # Simulator instruction rate (inst/s) +host_op_rate 192789 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 89461870 # Simulator tick rate (ticks/s) +host_mem_usage 308536 # Number of bytes of host memory used +host_seconds 1148.21 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 232832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 130880 # Number of bytes read from this memory -system.physmem.bytes_read::total 363712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 232832 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 232832 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3638 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2045 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5683 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2253417 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1266695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3520112 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2253417 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2253417 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2253417 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1266695 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3520112 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5683 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 235072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 130944 # Number of bytes read from this memory +system.physmem.bytes_read::total 366016 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 235072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 235072 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3673 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2046 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5719 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2288443 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1274749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3563192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2288443 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2288443 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2288443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1274749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3563192 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5719 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5683 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5719 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 363712 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 366016 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 363712 # Total read bytes from the system interface side +system.physmem.bytesReadSys 366016 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 307 # Per bank write bursts -system.physmem.perBankRdBursts::1 383 # Per bank write bursts -system.physmem.perBankRdBursts::2 475 # Per bank write bursts -system.physmem.perBankRdBursts::3 366 # Per bank write bursts -system.physmem.perBankRdBursts::4 364 # Per bank write bursts -system.physmem.perBankRdBursts::5 336 # Per bank write bursts -system.physmem.perBankRdBursts::6 422 # Per bank write bursts -system.physmem.perBankRdBursts::7 392 # Per bank write bursts -system.physmem.perBankRdBursts::8 390 # Per bank write bursts -system.physmem.perBankRdBursts::9 296 # Per bank write bursts -system.physmem.perBankRdBursts::10 255 # Per bank write bursts -system.physmem.perBankRdBursts::11 273 # Per bank write bursts -system.physmem.perBankRdBursts::12 229 # Per bank write bursts -system.physmem.perBankRdBursts::13 485 # Per bank write bursts -system.physmem.perBankRdBursts::14 425 # Per bank write bursts -system.physmem.perBankRdBursts::15 285 # Per bank write bursts +system.physmem.perBankRdBursts::0 315 # Per bank write bursts +system.physmem.perBankRdBursts::1 393 # Per bank write bursts +system.physmem.perBankRdBursts::2 481 # Per bank write bursts +system.physmem.perBankRdBursts::3 362 # Per bank write bursts +system.physmem.perBankRdBursts::4 367 # Per bank write bursts +system.physmem.perBankRdBursts::5 335 # Per bank write bursts +system.physmem.perBankRdBursts::6 442 # Per bank write bursts +system.physmem.perBankRdBursts::7 357 # Per bank write bursts +system.physmem.perBankRdBursts::8 405 # Per bank write bursts +system.physmem.perBankRdBursts::9 298 # Per bank write bursts +system.physmem.perBankRdBursts::10 258 # Per bank write bursts +system.physmem.perBankRdBursts::11 270 # Per bank write bursts +system.physmem.perBankRdBursts::12 235 # Per bank write bursts +system.physmem.perBankRdBursts::13 489 # Per bank write bursts +system.physmem.perBankRdBursts::14 424 # Per bank write bursts +system.physmem.perBankRdBursts::15 288 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 103323737000 # Total gap between requests +system.physmem.totGap 102721127000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5683 # Read request sizes (log2) +system.physmem.readPktSize::6 5719 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,12 +91,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4460 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 973 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 211 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4464 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 987 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 224 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -187,29 +187,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1258 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 287.745628 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 162.611559 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.712964 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 571 45.39% 45.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 250 19.87% 65.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 94 7.47% 72.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 65 5.17% 77.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 43 3.42% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 57 4.53% 85.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 29 2.31% 88.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 22 1.75% 89.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 127 10.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1258 # Bytes accessed per row activation -system.physmem.totQLat 187208250 # Total ticks spent queuing -system.physmem.totMemAccLat 293764500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 28415000 # Total ticks spent in databus transfers -system.physmem.avgQLat 32941.80 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1259 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 289.245433 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 165.404896 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 321.969258 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 547 43.45% 43.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 270 21.45% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 107 8.50% 73.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 51 4.05% 77.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 47 3.73% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 64 5.08% 86.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 24 1.91% 88.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 25 1.99% 90.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 124 9.85% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1259 # Bytes accessed per row activation +system.physmem.totQLat 198070500 # Total ticks spent queuing +system.physmem.totMemAccLat 305301750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 28595000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34633.76 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51691.80 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.52 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 53383.76 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.56 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.56 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage @@ -217,309 +217,309 @@ system.physmem.busUtilRead 0.03 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4417 # Number of row buffer hits during reads +system.physmem.readRowHits 4452 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.72 # Row buffer hit rate for reads +system.physmem.readRowHitRate 77.85 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 18181196.02 # Average gap between requests -system.physmem.pageHitRate 77.72 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5404980 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2853840 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 21741300 # Energy for read commands per rank (pJ) +system.physmem.avgGap 17961379.09 # Average gap between requests +system.physmem.pageHitRate 77.85 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5319300 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2808300 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 21791280 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 298715040.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 95918460 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 16609440 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 744016440 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 410144160 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 24152474700 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 25747878360 # Total energy per rank (pJ) -system.physmem_0.averagePower 249.195533 # Core power per rank (mW) -system.physmem_0.totalIdleTime 103070096750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 32003500 # Time in different power states -system.physmem_0.memoryStateTime::REF 127050000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 100370697500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 1068078250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 94522250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 1631644000 # Time in different power states -system.physmem_1.actEnergy 3634260 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1920270 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18835320 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 308549280.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 94282560 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 17303520 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 739487790 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 445716000 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 23991769245 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 25627073595 # Total energy per rank (pJ) +system.physmem_0.averagePower 249.481384 # Core power per rank (mW) +system.physmem_0.totalIdleTime 102469123000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 33581500 # Time in different power states +system.physmem_0.memoryStateTime::REF 131264000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 99687058000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 1160707250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 87094500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 1621680750 # Time in different power states +system.physmem_1.actEnergy 3727080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1969605 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 19042380 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 228031440.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 73672500 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 12688320 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 586536840 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 299079840 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 24303470280 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 25527869070 # Total energy per rank (pJ) -system.physmem_1.averagePower 247.066219 # Core power per rank (mW) -system.physmem_1.totalIdleTime 103129135750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 24348000 # Time in different power states -system.physmem_1.memoryStateTime::REF 96994000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 101064274500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 778849000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 73295500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1286234500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 40855234 # Number of BP lookups -system.cpu.branchPred.condPredicted 40855234 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6727710 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 35293159 # Number of BTB lookups +system.physmem_1.refreshEnergy 233563200.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 75326640 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12588960 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 599034660 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 319716000 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 24137455500 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 25402424025 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.294404 # Core power per rank (mW) +system.physmem_1.totalIdleTime 102523153750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 23880000 # Time in different power states +system.physmem_1.memoryStateTime::REF 99310000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 100377149750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 832585250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 74819500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1313641500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 40475108 # Number of BP lookups +system.cpu.branchPred.condPredicted 40475108 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6616133 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 34806541 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3199678 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 605841 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 35293159 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 9878902 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 25414257 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 5019418 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 3130768 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 590894 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 34806541 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 9997740 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 24808801 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 4890379 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 103323995500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 206647992 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 102721386000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 205442773 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 46314104 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 419677545 # Number of instructions fetch has processed -system.cpu.fetch.Branches 40855234 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13078580 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 152558577 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14911731 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 146 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 6162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 75545 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 535 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 173 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 41227932 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1521125 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 10 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 206411107 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.413574 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.660203 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 45893468 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 415890095 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40475108 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13128508 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 151898710 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14677491 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 200 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5835 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 64355 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 603 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 40893606 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1496111 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 12 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 205202132 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.402306 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.658033 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 99253613 48.09% 48.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5140686 2.49% 50.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5371591 2.60% 53.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5329252 2.58% 55.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6011005 2.91% 58.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5851603 2.83% 61.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5726027 2.77% 64.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4748810 2.30% 66.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 68978520 33.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 98918732 48.21% 48.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5142243 2.51% 50.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5340112 2.60% 53.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5342271 2.60% 55.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5947890 2.90% 58.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5817544 2.84% 61.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5684313 2.77% 64.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4746268 2.31% 66.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 68262759 33.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 206411107 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.197704 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.030881 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32267820 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 86650194 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 62332865 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17704363 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 7455865 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 590435256 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 7455865 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42053837 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 46607662 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 29929 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 68827187 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 41436627 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 551754102 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1587 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 36503796 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4817365 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 169314 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 629088770 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1485013522 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 974082903 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 15054868 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 205202132 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.197014 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.024360 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31935878 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 86571693 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 61623233 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17732583 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 7338745 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 585424017 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 7338745 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 41662208 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 46227710 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 28975 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 68218759 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 41725735 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 547333455 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1808 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 36710047 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4936211 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 172798 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 624155686 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1473918398 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 966803184 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 14714209 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 369659320 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2323 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2340 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 89508181 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 128738720 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 45872059 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 77414851 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 25246681 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 490126112 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 61893 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 338153574 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1099180 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 268824621 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 526308720 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 60648 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 206411107 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.638253 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.802953 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 364726236 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2257 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2274 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 89803577 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 127813025 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 45569326 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 76700063 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 25076085 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 486700618 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 63617 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 336591199 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1075816 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 265400851 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 520101355 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 62372 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 205202132 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.640291 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.801229 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 73313522 35.52% 35.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 46679908 22.62% 58.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32876430 15.93% 74.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20896006 10.12% 84.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 15048824 7.29% 91.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8392050 4.07% 95.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5201413 2.52% 98.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2354868 1.14% 99.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1648086 0.80% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 72558879 35.36% 35.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46563371 22.69% 58.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32833591 16.00% 74.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20829399 10.15% 84.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 14957397 7.29% 91.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8327086 4.06% 95.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5158088 2.51% 98.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2335665 1.14% 99.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1638656 0.80% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 206411107 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 205202132 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 756912 19.27% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2690839 68.51% 87.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 431049 10.97% 98.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 45501 1.16% 99.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 3340 0.09% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 746075 18.99% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2709270 68.98% 87.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 425878 10.84% 98.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 43262 1.10% 99.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 3383 0.09% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1211791 0.36% 0.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 216412325 64.00% 64.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 800256 0.24% 64.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7047583 2.08% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1802667 0.53% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 82552665 24.41% 91.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 26471074 7.83% 99.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 1726255 0.51% 99.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 128958 0.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212158 0.36% 0.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 215249611 63.95% 64.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 800532 0.24% 64.55% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7048368 2.09% 66.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1789279 0.53% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 82235879 24.43% 91.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 26412297 7.85% 99.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 1712250 0.51% 99.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 130825 0.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 338153574 # Type of FU issued -system.cpu.iq.rate 1.636375 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3927641 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011615 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 879585731 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 744431622 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 315835107 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 8159345 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 15410519 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3544176 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 336768258 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 4101166 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18155454 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 336591199 # Type of FU issued +system.cpu.iq.rate 1.638370 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3927868 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011670 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 875283157 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 737961913 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 314539873 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 8105057 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 15024545 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3526208 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 335233754 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 4073155 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18221671 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 72089133 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 55091 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 866955 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 25356342 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 71163438 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 53029 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 858947 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 25053609 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 50448 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 55 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 50433 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 53 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 7455865 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35715167 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 589866 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 490188005 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1248811 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 128738720 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 45872059 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22561 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 546009 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 38338 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 866955 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1295323 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6857589 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8152912 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 326241588 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 80652390 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 11911986 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 7338745 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35257397 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 584477 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 486764235 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1231542 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 127813025 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 45569326 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23100 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 542722 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 38323 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 858947 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1297189 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6715157 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8012346 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 324846022 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 80370790 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11745177 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 106269865 # number of memory reference insts executed -system.cpu.iew.exec_branches 18918443 # Number of branches executed -system.cpu.iew.exec_stores 25617475 # Number of stores executed -system.cpu.iew.exec_rate 1.578731 # Inst execution rate -system.cpu.iew.wb_sent 322387752 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 319379283 # cumulative count of insts written-back -system.cpu.iew.wb_producers 256328359 # num instructions producing a value -system.cpu.iew.wb_consumers 435429845 # num instructions consuming a value -system.cpu.iew.wb_rate 1.545523 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.588679 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 268850223 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 105939673 # number of memory reference insts executed +system.cpu.iew.exec_branches 18800592 # Number of branches executed +system.cpu.iew.exec_stores 25568883 # Number of stores executed +system.cpu.iew.exec_rate 1.581200 # Inst execution rate +system.cpu.iew.wb_sent 321037948 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 318066081 # cumulative count of insts written-back +system.cpu.iew.wb_producers 255309822 # num instructions producing a value +system.cpu.iew.wb_consumers 434053597 # num instructions consuming a value +system.cpu.iew.wb_rate 1.548198 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.588199 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 265431223 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6732902 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 163914906 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.350477 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.932475 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6620631 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 163283495 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.355700 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.936592 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 67189595 40.99% 40.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 54970007 33.54% 74.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13274329 8.10% 82.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 10696589 6.53% 89.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5450081 3.32% 92.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3128441 1.91% 94.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1086544 0.66% 95.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1161401 0.71% 95.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6957919 4.24% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 66681947 40.84% 40.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 54877402 33.61% 74.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13218916 8.10% 82.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 10716769 6.56% 89.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5408933 3.31% 92.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3143149 1.92% 94.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1097453 0.67% 95.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1149760 0.70% 95.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6989166 4.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 163914906 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 163283495 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -569,469 +569,469 @@ system.cpu.commit.op_class_0::FloatMemWrite 105487 0.05% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 6957919 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 647170594 # The number of ROB reads -system.cpu.rob.rob_writes 1023323556 # The number of ROB writes -system.cpu.timesIdled 2853 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 236885 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 6989166 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 643088936 # The number of ROB reads +system.cpu.rob.rob_writes 1015902477 # The number of ROB writes +system.cpu.timesIdled 2803 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 240641 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.564671 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.564671 # CPI: Total CPI of All Threads -system.cpu.ipc 0.639112 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.639112 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 524350393 # number of integer regfile reads -system.cpu.int_regfile_writes 288862618 # number of integer regfile writes -system.cpu.fp_regfile_reads 4510095 # number of floating regfile reads -system.cpu.fp_regfile_writes 3309705 # number of floating regfile writes -system.cpu.cc_regfile_reads 106995415 # number of cc regfile reads -system.cpu.cc_regfile_writes 65768687 # number of cc regfile writes -system.cpu.misc_regfile_reads 176729824 # number of misc regfile reads +system.cpu.cpi 1.555546 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.555546 # CPI: Total CPI of All Threads +system.cpu.ipc 0.642861 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.642861 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 522853571 # number of integer regfile reads +system.cpu.int_regfile_writes 287693953 # number of integer regfile writes +system.cpu.fp_regfile_reads 4488277 # number of floating regfile reads +system.cpu.fp_regfile_writes 3288210 # number of floating regfile writes +system.cpu.cc_regfile_reads 106934935 # number of cc regfile reads +system.cpu.cc_regfile_writes 65654592 # number of cc regfile writes +system.cpu.misc_regfile_reads 175824659 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 82 # number of replacements -system.cpu.dcache.tags.tagsinuse 1514.501359 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 82730891 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2127 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 38895.576399 # Average number of references to valid blocks. +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 101 # number of replacements +system.cpu.dcache.tags.tagsinuse 1519.152295 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 82373071 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2121 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 38836.902876 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1514.501359 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.369751 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.369751 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2045 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 418 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1470 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.499268 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 165469279 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 165469279 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 62216578 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 62216578 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513684 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513684 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 82730262 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 82730262 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 82730262 # number of overall hits -system.cpu.dcache.overall_hits::total 82730262 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1267 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1267 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2047 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2047 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3314 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3314 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3314 # number of overall misses -system.cpu.dcache.overall_misses::total 3314 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 112642500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 112642500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 136500000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 136500000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 249142500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 249142500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 249142500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 249142500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 62217845 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 62217845 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 1519.152295 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.370887 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.370887 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2020 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 426 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1452 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.493164 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 164753603 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 164753603 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 61858750 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 61858750 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513717 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513717 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 82372467 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 82372467 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 82372467 # number of overall hits +system.cpu.dcache.overall_hits::total 82372467 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1260 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1260 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2014 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2014 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3274 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3274 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3274 # number of overall misses +system.cpu.dcache.overall_misses::total 3274 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 128800000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 128800000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 138047000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 138047000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 266847000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 266847000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 266847000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 266847000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 61860010 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 61860010 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 82733576 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 82733576 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 82733576 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 82733576 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 82375741 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 82375741 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 82375741 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 82375741 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000100 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000100 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000098 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000098 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88904.893449 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 88904.893449 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66682.950660 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66682.950660 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75178.786964 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75178.786964 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75178.786964 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75178.786964 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 331 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 143 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 82.750000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 71.500000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 17 # number of writebacks -system.cpu.dcache.writebacks::total 17 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 658 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 658 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 664 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 664 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 664 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 664 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 609 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 609 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2041 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2041 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2650 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2650 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2650 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2650 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70639000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 70639000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 134072000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 134072000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204711000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 204711000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204711000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 204711000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102222.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 102222.222222 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68543.694141 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 68543.694141 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 81504.886988 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 81504.886988 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 81504.886988 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 81504.886988 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 635 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 58 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 127 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 58 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 22 # number of writebacks +system.cpu.dcache.writebacks::total 22 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 652 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 652 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 663 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 663 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 663 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 663 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 608 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 608 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2003 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2003 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2611 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2611 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2611 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2611 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79597500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 79597500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 135457500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 135457500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215055000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 215055000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215055000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 215055000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000099 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000099 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000098 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000098 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115991.789819 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115991.789819 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65689.367957 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65689.367957 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77249.433962 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77249.433962 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77249.433962 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77249.433962 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 6640 # number of replacements -system.cpu.icache.tags.tagsinuse 1671.571610 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 41214631 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8628 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4776.846430 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 130916.940789 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 130916.940789 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67627.309036 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67627.309036 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82364.994255 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82364.994255 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82364.994255 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82364.994255 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 6438 # number of replacements +system.cpu.icache.tags.tagsinuse 1691.823634 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 40880551 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8435 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4846.538352 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1671.571610 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.816197 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.816197 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1988 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 860 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 163 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 713 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.970703 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 82465000 # Number of tag accesses -system.cpu.icache.tags.data_accesses 82465000 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 41214631 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 41214631 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 41214631 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 41214631 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 41214631 # number of overall hits -system.cpu.icache.overall_hits::total 41214631 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13297 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13297 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13297 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13297 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13297 # number of overall misses -system.cpu.icache.overall_misses::total 13297 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 657223000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 657223000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 657223000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 657223000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 657223000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 657223000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 41227928 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 41227928 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 41227928 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 41227928 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 41227928 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 41227928 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000323 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000323 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000323 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000323 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000323 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000323 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49426.411973 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49426.411973 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49426.411973 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49426.411973 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49426.411973 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49426.411973 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2020 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 107 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 32 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 63.125000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 107 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 6640 # number of writebacks -system.cpu.icache.writebacks::total 6640 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4152 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4152 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4152 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4152 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4152 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4152 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9145 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 9145 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 9145 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 9145 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 9145 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 9145 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 457240000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 457240000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 457240000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 457240000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 457240000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 457240000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000222 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000222 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000222 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000222 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000222 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000222 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49998.906506 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49998.906506 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49998.906506 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 49998.906506 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49998.906506 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 49998.906506 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.occ_blocks::cpu.inst 1691.823634 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.826086 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.826086 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1997 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 850 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 153 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 731 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.975098 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 81796128 # Number of tag accesses +system.cpu.icache.tags.data_accesses 81796128 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 40880552 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 40880552 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 40880552 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 40880552 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 40880552 # number of overall hits +system.cpu.icache.overall_hits::total 40880552 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13050 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13050 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13050 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13050 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13050 # number of overall misses +system.cpu.icache.overall_misses::total 13050 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 646702000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 646702000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 646702000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 646702000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 646702000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 646702000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 40893602 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 40893602 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 40893602 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 40893602 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 40893602 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 40893602 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000319 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000319 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000319 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000319 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000319 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000319 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49555.708812 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49555.708812 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49555.708812 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49555.708812 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49555.708812 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49555.708812 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2923 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 38 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 76.921053 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 6438 # number of writebacks +system.cpu.icache.writebacks::total 6438 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4125 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4125 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4125 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4125 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4125 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4125 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8925 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 8925 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 8925 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 8925 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 8925 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 8925 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 457055500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 457055500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 457055500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 457055500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 457055500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 457055500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000218 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000218 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000218 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51210.700280 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51210.700280 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51210.700280 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51210.700280 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51210.700280 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51210.700280 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3890.572014 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 12247 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5683 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.155024 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3920.889398 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 11824 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5719 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.067494 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2409.860843 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1480.711171 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073543 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.045188 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.118731 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5683 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2430.261173 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1490.628224 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074166 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.045490 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.119656 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5719 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1019 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 527 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3926 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.173431 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 149123 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 149123 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 17 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 17 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 6583 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 6583 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 523 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 523 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4982 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 4982 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 75 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 75 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 4982 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 82 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 5064 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 4982 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 82 # number of overall hits -system.cpu.l2cache.overall_hits::total 5064 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 1513 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1513 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3638 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3638 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 532 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 532 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3638 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2045 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5683 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3638 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2045 # number of overall misses -system.cpu.l2cache.overall_misses::total 5683 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 125080500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 125080500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 390212000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 390212000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 68692500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 68692500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 390212000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 193773000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 583985000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 390212000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 193773000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 583985000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 17 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 17 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 6583 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 6583 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 523 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 523 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1520 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1520 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8620 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 8620 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 607 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 607 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 8620 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2127 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 10747 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 8620 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2127 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 10747 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995395 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.995395 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.422042 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.422042 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.876442 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.876442 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.422042 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.961448 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.528799 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.422042 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.961448 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.528799 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82670.522141 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82670.522141 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107260.032985 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107260.032985 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 129121.240602 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 129121.240602 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107260.032985 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94754.523227 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 102759.985923 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107260.032985 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94754.523227 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 102759.985923 # average overall miss latency +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1010 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 536 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3957 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.174530 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 146063 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 146063 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 22 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 22 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 6400 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 6400 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 490 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 490 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4761 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 4761 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 67 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 67 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 4761 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 75 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 4836 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 4761 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 75 # number of overall hits +system.cpu.l2cache.overall_hits::total 4836 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 1507 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1507 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3673 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3673 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 539 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 539 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3673 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2046 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5719 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3673 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2046 # number of overall misses +system.cpu.l2cache.overall_misses::total 5719 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 126886000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 126886000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 392741000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 392741000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 77762500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 77762500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 392741000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 204648500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 597389500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 392741000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 204648500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 597389500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 22 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 22 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 6400 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 6400 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 490 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 490 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1515 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1515 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8434 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 8434 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 606 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 606 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 8434 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2121 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 10555 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 8434 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2121 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 10555 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994719 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.994719 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.435499 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.435499 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.889439 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.889439 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.435499 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964639 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.541829 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.435499 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964639 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.541829 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84197.743862 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84197.743862 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 106926.490607 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 106926.490607 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 144271.799629 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 144271.799629 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 106926.490607 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 100023.704790 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 104456.985487 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 106926.490607 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 100023.704790 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 104456.985487 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1513 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1513 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3638 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3638 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 532 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 532 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3638 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2045 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5683 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3638 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2045 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5683 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 109950500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 109950500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 353832000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 353832000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 63372500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 63372500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 353832000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 173323000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 527155000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 353832000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 173323000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 527155000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995395 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995395 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.422042 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.422042 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.876442 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.876442 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.422042 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.961448 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.528799 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.422042 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.961448 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.528799 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72670.522141 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72670.522141 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97260.032985 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97260.032985 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 119121.240602 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 119121.240602 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97260.032985 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84754.523227 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 92759.985923 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97260.032985 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84754.523227 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 92759.985923 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18517 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 6823 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1046 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1507 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1507 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3673 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3673 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 539 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 539 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3673 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2046 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5719 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2046 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5719 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111816000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111816000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 356011000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 356011000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 72372500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 72372500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 356011000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 184188500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 540199500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 356011000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 184188500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 540199500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994719 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994719 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.435499 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.435499 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.889439 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.889439 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.435499 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964639 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.541829 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.435499 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964639 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.541829 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74197.743862 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74197.743862 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96926.490607 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96926.490607 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 134271.799629 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 134271.799629 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96926.490607 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 90023.704790 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94456.985487 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96926.490607 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 90023.704790 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94456.985487 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18075 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 6619 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 979 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 9751 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 6640 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 65 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 523 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 523 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1520 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1520 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 9145 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 607 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24404 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5382 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 29786 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 976576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 137216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1113792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 525 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 33600 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11795 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.096651 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.295495 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 9530 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 22 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6438 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 79 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 490 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 490 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1515 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1515 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 8925 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 606 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23796 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5323 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 29119 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 951744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 137152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1088896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 491 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 31424 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11536 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.091713 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.288633 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 10655 90.33% 90.33% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1140 9.67% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 10478 90.83% 90.83% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1058 9.17% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11795 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15915500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11536 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15497500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 13716000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 13386000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3452000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3426999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 5683 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 5719 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4170 # Transaction distribution -system.membus.trans_dist::ReadExReq 1513 # Transaction distribution -system.membus.trans_dist::ReadExResp 1513 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4170 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11366 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11366 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11366 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 363712 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 363712 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 363712 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 4212 # Transaction distribution +system.membus.trans_dist::ReadExReq 1507 # Transaction distribution +system.membus.trans_dist::ReadExResp 1507 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4212 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11438 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11438 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11438 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 366016 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 366016 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 366016 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 5683 # Request fanout histogram +system.membus.snoop_fanout::samples 5719 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5683 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5719 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5683 # Request fanout histogram -system.membus.reqLayer0.occupancy 6909500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5719 # Request fanout histogram +system.membus.reqLayer0.occupancy 6957500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 30126750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 30309750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |