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authorNilay Vaish <nilay@cs.wisc.edu>2012-01-28 19:09:04 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2012-01-28 19:09:04 -0600
commit5c2fc35e029d8cd8e69e983e1baef6b86e47d64d (patch)
tree03e3f37b4cef15a165f79b5dde0a7abee14e0523 /tests/long
parent4acca8a0536d4445ed25b67edf571ae460446ab9 (diff)
downloadgem5-5c2fc35e029d8cd8e69e983e1baef6b86e47d64d.tar.xz
O3 CPU LSQ: Implement TSO
This patch makes O3's LSQ maintain total order between stores. Essentially only the store at the head of the store buffer is allowed to be in flight. Only after that store completes, the next store is issued to the memory system. By default, the x86 architecture will have TSO.
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