diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-09-28 13:22:34 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-09-28 13:22:34 -0400 |
| commit | 272d867402e50dba49f1f78976711388a8056427 (patch) | |
| tree | 4542f12377fae4e2f31a592b161997487856cd74 /tests/long | |
| parent | d2a4f595d6e70f5f9f5c7cae4f496c2db1e39ca5 (diff) | |
| download | gem5-272d867402e50dba49f1f78976711388a8056427.tar.xz | |
Update statistics for the last three revisions
--HG--
extra : convert_revision : 117e2a40bd6e0867d013a3a6076fb758ac526d24
Diffstat (limited to 'tests/long')
25 files changed, 121 insertions, 157 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt index 0a81b23fb..c535b6427 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 4207318 # Nu global.BPredUnit.condPredicted 70088985 # Number of conditional branches predicted global.BPredUnit.lookups 76017379 # Number of BP lookups global.BPredUnit.usedRAS 1692882 # Number of times the RAS was used to get a target. -host_inst_rate 211348 # Simulator instruction rate (inst/s) -host_mem_usage 182448 # Number of bytes of host memory used -host_seconds 2675.93 # Real time elapsed on the host -host_tick_rate 60738573 # Simulator tick rate (ticks/s) +host_inst_rate 209676 # Simulator instruction rate (inst/s) +host_mem_usage 200632 # Number of bytes of host memory used +host_seconds 2697.27 # Real time elapsed on the host +host_tick_rate 60257939 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 16721732 # Number of conflicting loads. memdepunit.memDep.conflictingStores 11866335 # Number of conflicting stores. memdepunit.memDep.insertedLoads 126743752 # Number of loads inserted to the mem dependence unit. @@ -157,7 +157,7 @@ system.cpu.fetch.SquashCycles 4233156 # Nu system.cpu.fetch.branchRate 0.233854 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 65923007 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 67369318 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.146836 # Number of inst fetches per cycle +system.cpu.fetch.rate 2.146834 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.samples 325063615 system.cpu.fetch.rateDist.min_value 0 @@ -236,10 +236,10 @@ system.cpu.icache.tagsinuse 770.534444 # Cy system.cpu.icache.total_refs 65922018 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 190397 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 278 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 67319692 # Number of branches executed system.cpu.iew.EXEC:nop 42991424 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.842347 # Inst execution rate +system.cpu.iew.EXEC:rate 1.842345 # Inst execution rate system.cpu.iew.EXEC:refs 163918711 # number of memory reference insts executed system.cpu.iew.EXEC:stores 41167815 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed @@ -249,7 +249,7 @@ system.cpu.iew.WB:fanout 0.805927 # av system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:producers 395691865 # num instructions producing a value -system.cpu.iew.WB:rate 1.832664 # insts written-back per cycle +system.cpu.iew.WB:rate 1.832662 # insts written-back per cycle system.cpu.iew.WB:sent 596897738 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 4671822 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 211982 # Number of cycles IEW is blocking @@ -279,8 +279,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 3229074 # system.cpu.iew.memOrderViolationEvents 28955 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 540642 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 4131180 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.739821 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.739821 # IPC: Total IPC of All Threads +system.cpu.ipc 1.739819 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.739819 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 605296760 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued @@ -331,7 +331,7 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.862087 # Inst issue rate +system.cpu.iq.ISSUE:rate 1.862085 # Inst issue rate system.cpu.iq.iqInstsAdded 619382498 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 605296760 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ @@ -428,7 +428,7 @@ system.cpu.l2cache.tagsinuse 8150.643180 # Cy system.cpu.l2cache.total_refs 66110 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 325063615 # number of cpu cycles simulated +system.cpu.numCycles 325063893 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 11040699 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 31586100 # Number of times rename has blocked due to IQ full diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt index b76b4e6c1..9e54c6441 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1730291 # Simulator instruction rate (inst/s) -host_mem_usage 181616 # Number of bytes of host memory used -host_seconds 347.84 # Real time elapsed on the host -host_tick_rate 2208778962 # Simulator tick rate (ticks/s) +host_inst_rate 1400395 # Simulator instruction rate (inst/s) +host_mem_usage 199872 # Number of bytes of host memory used +host_seconds 429.78 # Real time elapsed on the host +host_tick_rate 1787654853 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.768293 # Number of seconds simulated @@ -245,7 +245,7 @@ system.cpu.l2cache.total_refs 52084 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 768292872000 # number of cpu cycles simulated +system.cpu.numCycles 1536585744 # number of cpu cycles simulated system.cpu.num_insts 601856964 # Number of instructions executed system.cpu.num_refs 154866966 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt index f737a8e3b..ae6ff07ca 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 84447535 # Nu global.BPredUnit.condPredicted 256528366 # Number of conditional branches predicted global.BPredUnit.lookups 256528366 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 94020 # Simulator instruction rate (inst/s) -host_mem_usage 184848 # Number of bytes of host memory used -host_seconds 14950.16 # Real time elapsed on the host -host_tick_rate 73409017 # Simulator tick rate (ticks/s) +host_inst_rate 101903 # Simulator instruction rate (inst/s) +host_mem_usage 202864 # Number of bytes of host memory used +host_seconds 13793.57 # Real time elapsed on the host +host_tick_rate 79564409 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 458856790 # Number of conflicting loads. memdepunit.memDep.conflictingStores 141228058 # Number of conflicting stores. memdepunit.memDep.insertedLoads 745627925 # Number of loads inserted to the mem dependence unit. @@ -229,7 +229,7 @@ system.cpu.icache.tagsinuse 1042.348080 # Cy system.cpu.icache.total_refs 355014725 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 94965 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 155 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 128778452 # Number of branches executed system.cpu.iew.EXEC:nop 354384689 # number of nop insts executed system.cpu.iew.EXEC:rate 0.865881 # Inst execution rate @@ -242,7 +242,7 @@ system.cpu.iew.WB:fanout 0.963032 # av system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:producers 1442442170 # num instructions producing a value -system.cpu.iew.WB:rate 0.850638 # insts written-back per cycle +system.cpu.iew.WB:rate 0.850637 # insts written-back per cycle system.cpu.iew.WB:sent 1877161076 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 91327681 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 454443 # Number of cycles IEW is blocking @@ -417,7 +417,7 @@ system.cpu.l2cache.tagsinuse 8527.413561 # Cy system.cpu.l2cache.total_refs 96715 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 2194953627 # number of cpu cycles simulated +system.cpu.numCycles 2194953782 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 13000888 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1244771057 # Number of HB maps that are committed system.cpu.rename.RENAME:FullRegisterEvents 9 # Number of times there has been no free registers diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr index 6fe2fe04f..70bd1351f 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr @@ -1,6 +1,2 @@ -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0xb4000 length 0x10. -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x0 length 0x0. warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr index 6fe2fe04f..70bd1351f 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr @@ -1,6 +1,2 @@ -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0xb4000 length 0x10. -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x0 length 0x0. warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt index 2a33edee7..50e7d390e 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1120793 # Simulator instruction rate (inst/s) -host_mem_usage 183848 # Number of bytes of host memory used -host_seconds 1328.98 # Real time elapsed on the host -host_tick_rate 1558243449 # Simulator tick rate (ticks/s) +host_inst_rate 1001521 # Simulator instruction rate (inst/s) +host_mem_usage 201940 # Number of bytes of host memory used +host_seconds 1487.25 # Real time elapsed on the host +host_tick_rate 1392419330 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489514761 # Number of instructions simulated sim_seconds 2.070880 # Number of seconds simulated @@ -239,7 +239,7 @@ system.cpu.l2cache.total_refs 62289 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2070879986000 # number of cpu cycles simulated +system.cpu.numCycles 4141759972 # number of cpu cycles simulated system.cpu.num_insts 1489514761 # Number of instructions executed system.cpu.num_refs 569364430 # Number of memory references system.cpu.workload.PROG:num_syscalls 19 # Number of system calls diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr index 6fe2fe04f..70bd1351f 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr @@ -1,6 +1,2 @@ -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0xb4000 length 0x10. -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x0 length 0x0. warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr index cf178f133..70bd1351f 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr @@ -1,6 +1,2 @@ -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0xa2000 length 0x10. -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x0 length 0x0. warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt index 7fd034515..825271309 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1059302 # Simulator instruction rate (inst/s) -host_mem_usage 184256 # Number of bytes of host memory used -host_seconds 230.18 # Real time elapsed on the host -host_tick_rate 1578613892 # Simulator tick rate (ticks/s) +host_inst_rate 981553 # Simulator instruction rate (inst/s) +host_mem_usage 203224 # Number of bytes of host memory used +host_seconds 248.41 # Real time elapsed on the host +host_tick_rate 1462749007 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 243829010 # Number of instructions simulated sim_seconds 0.363364 # Number of seconds simulated @@ -239,7 +239,7 @@ system.cpu.l2cache.total_refs 553407 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 363364127000 # number of cpu cycles simulated +system.cpu.numCycles 726728254 # number of cpu cycles simulated system.cpu.num_insts 243829010 # Number of instructions executed system.cpu.num_refs 105710359 # Number of memory references system.cpu.workload.PROG:num_syscalls 428 # Number of system calls diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr index cf178f133..70bd1351f 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr @@ -1,6 +1,2 @@ -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0xa2000 length 0x10. -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x0 length 0x0. warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt index 373ebcd68..f75afa011 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 5797485 # Nu global.BPredUnit.condPredicted 35586107 # Number of conditional branches predicted global.BPredUnit.lookups 62816866 # Number of BP lookups global.BPredUnit.usedRAS 12584281 # Number of times the RAS was used to get a target. -host_inst_rate 159982 # Simulator instruction rate (inst/s) -host_mem_usage 190068 # Number of bytes of host memory used -host_seconds 2347.61 # Real time elapsed on the host -host_tick_rate 55593251 # Simulator tick rate (ticks/s) +host_inst_rate 162238 # Simulator instruction rate (inst/s) +host_mem_usage 208244 # Number of bytes of host memory used +host_seconds 2314.96 # Real time elapsed on the host +host_tick_rate 56377317 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 72605768 # Number of conflicting loads. memdepunit.memDep.conflictingStores 52678550 # Number of conflicting stores. memdepunit.memDep.insertedLoads 125601766 # Number of loads inserted to the mem dependence unit. @@ -49,8 +49,8 @@ system.cpu.commit.commitNonSpecStalls 215 # Th system.cpu.commit.commitSquashedInsts 97412298 # The number of squashed insts skipped by commit system.cpu.committedInsts 375574833 # Number of Instructions Simulated system.cpu.committedInsts_total 375574833 # Number of Instructions Simulated -system.cpu.cpi 0.694992 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.694992 # CPI: Total CPI of All Threads +system.cpu.cpi 0.694995 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.694995 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits system.cpu.dcache.ReadReq_accesses 96463931 # number of ReadReq accesses(hits+misses) @@ -154,10 +154,10 @@ system.cpu.fetch.Cycles 169349894 # Nu system.cpu.fetch.IcacheSquashes 1380085 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 550063393 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 6176073 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.240658 # Number of branch fetches per cycle +system.cpu.fetch.branchRate 0.240657 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 64526365 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 49445851 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.107348 # Number of inst fetches per cycle +system.cpu.fetch.rate 2.107339 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.samples 261021562 system.cpu.fetch.rateDist.min_value 0 @@ -236,10 +236,10 @@ system.cpu.icache.tagsinuse 1827.041992 # Cy system.cpu.icache.total_refs 64522273 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 787561 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 1138 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 51184181 # Number of branches executed system.cpu.iew.EXEC:nop 27521515 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.613810 # Inst execution rate +system.cpu.iew.EXEC:rate 1.613803 # Inst execution rate system.cpu.iew.EXEC:refs 192783461 # number of memory reference insts executed system.cpu.iew.EXEC:stores 80743835 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed @@ -249,7 +249,7 @@ system.cpu.iew.WB:fanout 0.706015 # av system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:producers 200824371 # num instructions producing a value -system.cpu.iew.WB:rate 1.598292 # insts written-back per cycle +system.cpu.iew.WB:rate 1.598285 # insts written-back per cycle system.cpu.iew.WB:sent 418096768 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 6170690 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 1426561 # Number of cycles IEW is blocking @@ -279,8 +279,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 19324087 # system.cpu.iew.memOrderViolationEvents 574238 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 908757 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 5261933 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.438865 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.438865 # IPC: Total IPC of All Threads +system.cpu.ipc 1.438859 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.438859 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 431234771 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 33581 0.01% # Type of FU issued @@ -331,7 +331,7 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.652104 # Inst issue rate +system.cpu.iq.ISSUE:rate 1.652097 # Inst issue rate system.cpu.iq.iqInstsAdded 468556087 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 431234771 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 239 # Number of non-speculative instructions added to the IQ @@ -428,7 +428,7 @@ system.cpu.l2cache.tagsinuse 3522.085649 # Cy system.cpu.l2cache.total_refs 573 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 261021562 # number of cpu cycles simulated +system.cpu.numCycles 261022700 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 4632657 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 259532351 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 371371 # Number of times rename has blocked due to IQ full diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt index 9be74e08a..ebb18ce61 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1404632 # Simulator instruction rate (inst/s) -host_mem_usage 189192 # Number of bytes of host memory used -host_seconds 283.82 # Real time elapsed on the host -host_tick_rate 1998169503 # Simulator tick rate (ticks/s) +host_inst_rate 1238026 # Simulator instruction rate (inst/s) +host_mem_usage 207368 # Number of bytes of host memory used +host_seconds 322.02 # Real time elapsed on the host +host_tick_rate 1761163764 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664609 # Number of instructions simulated sim_seconds 0.567124 # Number of seconds simulated @@ -245,7 +245,7 @@ system.cpu.l2cache.total_refs 510 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 567124013000 # number of cpu cycles simulated +system.cpu.numCycles 1134248026 # number of cpu cycles simulated system.cpu.num_insts 398664609 # Number of instructions executed system.cpu.num_refs 174183455 # Number of memory references system.cpu.workload.PROG:num_syscalls 215 # Number of system calls diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt index 4725fc27c..0c4f37988 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1524477 # Simulator instruction rate (inst/s) -host_mem_usage 188336 # Number of bytes of host memory used -host_seconds 1317.82 # Real time elapsed on the host -host_tick_rate 2100501698 # Simulator tick rate (ticks/s) +host_inst_rate 1159414 # Simulator instruction rate (inst/s) +host_mem_usage 206548 # Number of bytes of host memory used +host_seconds 1732.76 # Real time elapsed on the host +host_tick_rate 1597499589 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 2.768086 # Number of seconds simulated @@ -245,7 +245,7 @@ system.cpu.l2cache.total_refs 22612 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2768085828000 # number of cpu cycles simulated +system.cpu.numCycles 5536171656 # number of cpu cycles simulated system.cpu.num_insts 2008987605 # Number of instructions executed system.cpu.num_refs 722823898 # Number of memory references system.cpu.workload.PROG:num_syscalls 39 # Number of system calls diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt index b4b0c54a3..15ee80644 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 455902 # Nu global.BPredUnit.condPredicted 10551273 # Number of conditional branches predicted global.BPredUnit.lookups 16246333 # Number of BP lookups global.BPredUnit.usedRAS 1941036 # Number of times the RAS was used to get a target. -host_inst_rate 173213 # Simulator instruction rate (inst/s) -host_mem_usage 193376 # Number of bytes of host memory used -host_seconds 459.50 # Real time elapsed on the host -host_tick_rate 54150958 # Simulator tick rate (ticks/s) +host_inst_rate 178455 # Simulator instruction rate (inst/s) +host_mem_usage 211564 # Number of bytes of host memory used +host_seconds 446.00 # Real time elapsed on the host +host_tick_rate 55789781 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 12304370 # Number of conflicting loads. memdepunit.memDep.conflictingStores 10964244 # Number of conflicting stores. memdepunit.memDep.insertedLoads 22974359 # Number of loads inserted to the mem dependence unit. @@ -49,8 +49,8 @@ system.cpu.commit.commitNonSpecStalls 4583 # Th system.cpu.commit.commitSquashedInsts 8051078 # The number of squashed insts skipped by commit system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.625230 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.625230 # CPI: Total CPI of All Threads +system.cpu.cpi 0.625252 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.625252 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 44 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 44 # number of LoadLockedReq hits system.cpu.dcache.ReadReq_accesses 20377695 # number of ReadReq accesses(hits+misses) @@ -154,10 +154,10 @@ system.cpu.fetch.Cycles 33194597 # Nu system.cpu.fetch.IcacheSquashes 152184 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 103251284 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 572846 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.326473 # Number of branch fetches per cycle +system.cpu.fetch.branchRate 0.326461 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 13375683 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 9942709 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.074854 # Number of inst fetches per cycle +system.cpu.fetch.rate 2.074780 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.samples 49763148 system.cpu.fetch.rateDist.min_value 0 @@ -236,10 +236,10 @@ system.cpu.icache.tagsinuse 1922.769682 # Cy system.cpu.icache.total_refs 13289333 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 21643859000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1231826 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 1791 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 14739683 # Number of branches executed system.cpu.iew.EXEC:nop 9380523 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.704450 # Inst execution rate +system.cpu.iew.EXEC:rate 1.704389 # Inst execution rate system.cpu.iew.EXEC:refs 36969776 # number of memory reference insts executed system.cpu.iew.EXEC:stores 15295559 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed @@ -249,7 +249,7 @@ system.cpu.iew.WB:fanout 0.765386 # av system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:producers 32456867 # num instructions producing a value -system.cpu.iew.WB:rate 1.694688 # insts written-back per cycle +system.cpu.iew.WB:rate 1.694627 # insts written-back per cycle system.cpu.iew.WB:sent 84566644 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 400717 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 20492 # Number of cycles IEW is blocking @@ -279,8 +279,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 1453767 # system.cpu.iew.memOrderViolationEvents 19531 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 108348 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 292369 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.599412 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.599412 # IPC: Total IPC of All Threads +system.cpu.ipc 1.599354 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.599354 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 85364731 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued @@ -331,7 +331,7 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.715421 # Inst issue rate +system.cpu.iq.ISSUE:rate 1.715359 # Inst issue rate system.cpu.iq.iqInstsAdded 89442204 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 85364731 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 4987 # Number of non-speculative instructions added to the IQ @@ -428,7 +428,7 @@ system.cpu.l2cache.tagsinuse 4581.530519 # Cy system.cpu.l2cache.total_refs 102503 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 49763148 # number of cpu cycles simulated +system.cpu.numCycles 49764939 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 263435 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 34724 # Number of times rename has blocked due to IQ full diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt index 42618bd93..c05407db8 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1453070 # Simulator instruction rate (inst/s) -host_mem_usage 191752 # Number of bytes of host memory used -host_seconds 60.80 # Real time elapsed on the host -host_tick_rate 2124138006 # Simulator tick rate (ticks/s) +host_inst_rate 1210019 # Simulator instruction rate (inst/s) +host_mem_usage 209960 # Number of bytes of host memory used +host_seconds 73.01 # Real time elapsed on the host +host_tick_rate 1768843958 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.129140 # Number of seconds simulated @@ -245,7 +245,7 @@ system.cpu.l2cache.total_refs 93692 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 129139604000 # number of cpu cycles simulated +system.cpu.numCycles 258279208 # number of cpu cycles simulated system.cpu.num_insts 88340673 # Number of instructions executed system.cpu.num_refs 35321418 # Number of memory references system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr index 08cfb2451..2e627b821 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr @@ -1,7 +1,3 @@ -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x1838c0 length 0x10. -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x0 length 0x0. warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. warn: ignoring syscall time(4026527856, 4026528256, ...) diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt index 2bb84bd57..8b535e51e 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 960220 # Simulator instruction rate (inst/s) -host_mem_usage 192724 # Number of bytes of host memory used -host_seconds 141.78 # Real time elapsed on the host -host_tick_rate 1412855280 # Simulator tick rate (ticks/s) +host_inst_rate 941673 # Simulator instruction rate (inst/s) +host_mem_usage 210848 # Number of bytes of host memory used +host_seconds 144.57 # Real time elapsed on the host +host_tick_rate 1385565564 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136141055 # Number of instructions simulated sim_seconds 0.200317 # Number of seconds simulated @@ -239,7 +239,7 @@ system.cpu.l2cache.total_refs 193951 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 200316584000 # number of cpu cycles simulated +system.cpu.numCycles 400633168 # number of cpu cycles simulated system.cpu.num_insts 136141055 # Number of instructions executed system.cpu.num_refs 58160249 # Number of memory references system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr index 08cfb2451..2e627b821 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr @@ -1,7 +1,3 @@ -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x1838c0 length 0x10. -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x0 length 0x0. warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. warn: ignoring syscall time(4026527856, 4026528256, ...) diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt index 57430d61b..752f725e4 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 19407214 # Nu global.BPredUnit.condPredicted 254124044 # Number of conditional branches predicted global.BPredUnit.lookups 329654644 # Number of BP lookups global.BPredUnit.usedRAS 23321143 # Number of times the RAS was used to get a target. -host_inst_rate 153530 # Simulator instruction rate (inst/s) -host_mem_usage 182552 # Number of bytes of host memory used -host_seconds 11307.49 # Real time elapsed on the host -host_tick_rate 57851122 # Simulator tick rate (ticks/s) +host_inst_rate 162413 # Simulator instruction rate (inst/s) +host_mem_usage 200732 # Number of bytes of host memory used +host_seconds 10689.07 # Real time elapsed on the host +host_tick_rate 61198134 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 71970991 # Number of conflicting loads. memdepunit.memDep.conflictingStores 36581423 # Number of conflicting stores. memdepunit.memDep.insertedLoads 594992654 # Number of loads inserted to the mem dependence unit. @@ -244,10 +244,10 @@ system.cpu.icache.tagsinuse 710.981871 # Cy system.cpu.icache.total_refs 338458990 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 287621 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 197 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 270496646 # Number of branches executed system.cpu.iew.EXEC:nop 123104849 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.690527 # Inst execution rate +system.cpu.iew.EXEC:rate 1.690526 # Inst execution rate system.cpu.iew.EXEC:refs 759555990 # number of memory reference insts executed system.cpu.iew.EXEC:stores 199980185 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed @@ -436,7 +436,7 @@ system.cpu.l2cache.tagsinuse 18802.772660 # Cy system.cpu.l2cache.total_refs 5868601 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 505903232000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 1308302031 # number of cpu cycles simulated +system.cpu.numCycles 1308302228 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 9337867 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 3445352 # Number of times rename has blocked due to IQ full diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt index a6eb50453..afbd9c385 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1514723 # Simulator instruction rate (inst/s) -host_mem_usage 181532 # Number of bytes of host memory used -host_seconds 1201.39 # Real time elapsed on the host -host_tick_rate 2161875158 # Simulator tick rate (ticks/s) +host_inst_rate 1279505 # Simulator instruction rate (inst/s) +host_mem_usage 199716 # Number of bytes of host memory used +host_seconds 1422.25 # Real time elapsed on the host +host_tick_rate 1826162604 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 2.597265 # Number of seconds simulated @@ -245,7 +245,7 @@ system.cpu.l2cache.total_refs 5824390 # To system.cpu.l2cache.warmup_cycle 2034930554000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2597265186000 # number of cpu cycles simulated +system.cpu.numCycles 5194530372 # number of cpu cycles simulated system.cpu.num_insts 1819780127 # Number of instructions executed system.cpu.num_refs 613169725 # Number of memory references system.cpu.workload.PROG:num_syscalls 29 # Number of system calls diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt index 0262f8e2d..93bbafeb5 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 1944478 # Nu global.BPredUnit.condPredicted 14575632 # Number of conditional branches predicted global.BPredUnit.lookups 19422613 # Number of BP lookups global.BPredUnit.usedRAS 1713685 # Number of times the RAS was used to get a target. -host_inst_rate 134486 # Simulator instruction rate (inst/s) -host_mem_usage 187512 # Number of bytes of host memory used -host_seconds 625.94 # Real time elapsed on the host -host_tick_rate 64866574 # Simulator tick rate (ticks/s) +host_inst_rate 135551 # Simulator instruction rate (inst/s) +host_mem_usage 205692 # Number of bytes of host memory used +host_seconds 621.02 # Real time elapsed on the host +host_tick_rate 65380263 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 17216912 # Number of conflicting loads. memdepunit.memDep.conflictingStores 5017487 # Number of conflicting stores. memdepunit.memDep.insertedLoads 33831723 # Number of loads inserted to the mem dependence unit. @@ -49,8 +49,8 @@ system.cpu.commit.commitNonSpecStalls 389 # Th system.cpu.commit.commitSquashedInsts 55442802 # The number of squashed insts skipped by commit system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.964650 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.964650 # CPI: Total CPI of All Threads +system.cpu.cpi 0.964659 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.964659 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits system.cpu.dcache.ReadReq_accesses 23305151 # number of ReadReq accesses(hits+misses) @@ -154,10 +154,10 @@ system.cpu.fetch.Cycles 50102609 # Nu system.cpu.fetch.IcacheSquashes 509210 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 167066208 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 2080138 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.239183 # Number of branch fetches per cycle +system.cpu.fetch.branchRate 0.239181 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 19195045 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 14724343 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.057366 # Number of inst fetches per cycle +system.cpu.fetch.rate 2.057346 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.samples 81203929 system.cpu.fetch.rateDist.min_value 0 @@ -236,10 +236,10 @@ system.cpu.icache.tagsinuse 1547.586704 # Cy system.cpu.icache.total_refs 19184655 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 554685 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 795 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 12760718 # Number of branches executed system.cpu.iew.EXEC:nop 12520368 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.249722 # Inst execution rate +system.cpu.iew.EXEC:rate 1.249709 # Inst execution rate system.cpu.iew.EXEC:refs 31851627 # number of memory reference insts executed system.cpu.iew.EXEC:stores 7184817 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed @@ -249,7 +249,7 @@ system.cpu.iew.WB:fanout 0.723301 # av system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:producers 65598879 # num instructions producing a value -system.cpu.iew.WB:rate 1.226153 # insts written-back per cycle +system.cpu.iew.WB:rate 1.226141 # insts written-back per cycle system.cpu.iew.WB:sent 100495413 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 2106580 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 285272 # Number of cycles IEW is blocking @@ -279,8 +279,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 4054272 # system.cpu.iew.memOrderViolationEvents 250644 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 202889 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 1903691 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.036646 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.036646 # IPC: Total IPC of All Threads +system.cpu.ipc 1.036636 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.036636 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 103670386 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 7 0.00% # Type of FU issued @@ -331,7 +331,7 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.276667 # Inst issue rate +system.cpu.iq.ISSUE:rate 1.276655 # Inst issue rate system.cpu.iq.iqInstsAdded 134823640 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 103670386 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 429 # Number of non-speculative instructions added to the IQ @@ -428,7 +428,7 @@ system.cpu.l2cache.tagsinuse 2248.754865 # Cy system.cpu.l2cache.total_refs 7137 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 81203929 # number of cpu cycles simulated +system.cpu.numCycles 81204724 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 1670922 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 1021107 # Number of times rename has blocked due to IQ full diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt index beacdcee0..d2756f127 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1574277 # Simulator instruction rate (inst/s) -host_mem_usage 186464 # Number of bytes of host memory used -host_seconds 58.38 # Real time elapsed on the host -host_tick_rate 2031398471 # Simulator tick rate (ticks/s) +host_inst_rate 1354641 # Simulator instruction rate (inst/s) +host_mem_usage 204632 # Number of bytes of host memory used +host_seconds 67.84 # Real time elapsed on the host +host_tick_rate 1747991543 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.118590 # Number of seconds simulated @@ -245,7 +245,7 @@ system.cpu.l2cache.total_refs 5916 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 118589630000 # number of cpu cycles simulated +system.cpu.numCycles 237179260 # number of cpu cycles simulated system.cpu.num_insts 91903056 # Number of instructions executed system.cpu.num_refs 26537141 # Number of memory references system.cpu.workload.PROG:num_syscalls 389 # Number of system calls diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr index 18e13818c..2dcd5f795 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr @@ -1,7 +1,3 @@ -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x11e394 length 0x10. -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x0 length 0x0. warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt index bb82b8cc2..8855ab575 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1002711 # Simulator instruction rate (inst/s) -host_mem_usage 188412 # Number of bytes of host memory used -host_seconds 192.91 # Real time elapsed on the host -host_tick_rate 1401662479 # Simulator tick rate (ticks/s) +host_inst_rate 958305 # Simulator instruction rate (inst/s) +host_mem_usage 206472 # Number of bytes of host memory used +host_seconds 201.85 # Real time elapsed on the host +host_tick_rate 1339588721 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193435005 # Number of instructions simulated sim_seconds 0.270398 # Number of seconds simulated @@ -239,7 +239,7 @@ system.cpu.l2cache.total_refs 8679 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 270397899000 # number of cpu cycles simulated +system.cpu.numCycles 540795798 # number of cpu cycles simulated system.cpu.num_insts 193435005 # Number of instructions executed system.cpu.num_refs 76733003 # Number of memory references system.cpu.workload.PROG:num_syscalls 396 # Number of system calls diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr index 18e13818c..2dcd5f795 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr @@ -1,7 +1,3 @@ -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x11e394 length 0x10. -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x0 length 0x0. warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. warn: Increasing stack size by one page. |